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core_cm4.h
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00001 /**************************************************************************//** 00002 * @file core_cm4.h 00003 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File 00004 * @version V5.1.1 00005 * @date 19. August 2019 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__clang__) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_CM4_H_GENERIC 00032 #define __CORE_CM4_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_M4 00060 @{ 00061 */ 00062 00063 #include "cmsis_version.h" 00064 00065 /* CMSIS CM4 definitions */ 00066 #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 00067 #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 00068 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ 00069 __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 00070 00071 #define __CORTEX_M (4U) /*!< Cortex-M Core */ 00072 00073 /** __FPU_USED indicates whether an FPU is used or not. 00074 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 00075 */ 00076 #if defined ( __CC_ARM ) 00077 #if defined __TARGET_FPU_VFP 00078 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00079 #define __FPU_USED 1U 00080 #else 00081 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00082 #define __FPU_USED 0U 00083 #endif 00084 #else 00085 #define __FPU_USED 0U 00086 #endif 00087 00088 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00089 #if defined __ARM_FP 00090 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00091 #define __FPU_USED 1U 00092 #else 00093 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00094 #define __FPU_USED 0U 00095 #endif 00096 #else 00097 #define __FPU_USED 0U 00098 #endif 00099 00100 #elif defined ( __GNUC__ ) 00101 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00103 #define __FPU_USED 1U 00104 #else 00105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00106 #define __FPU_USED 0U 00107 #endif 00108 #else 00109 #define __FPU_USED 0U 00110 #endif 00111 00112 #elif defined ( __ICCARM__ ) 00113 #if defined __ARMVFP__ 00114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00115 #define __FPU_USED 1U 00116 #else 00117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00118 #define __FPU_USED 0U 00119 #endif 00120 #else 00121 #define __FPU_USED 0U 00122 #endif 00123 00124 #elif defined ( __TI_ARM__ ) 00125 #if defined __TI_VFP_SUPPORT__ 00126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00127 #define __FPU_USED 1U 00128 #else 00129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00130 #define __FPU_USED 0U 00131 #endif 00132 #else 00133 #define __FPU_USED 0U 00134 #endif 00135 00136 #elif defined ( __TASKING__ ) 00137 #if defined __FPU_VFP__ 00138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00139 #define __FPU_USED 1U 00140 #else 00141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00142 #define __FPU_USED 0U 00143 #endif 00144 #else 00145 #define __FPU_USED 0U 00146 #endif 00147 00148 #elif defined ( __CSMC__ ) 00149 #if ( __CSMC__ & 0x400U) 00150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00151 #define __FPU_USED 1U 00152 #else 00153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00154 #define __FPU_USED 0U 00155 #endif 00156 #else 00157 #define __FPU_USED 0U 00158 #endif 00159 00160 #endif 00161 00162 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00163 00164 00165 #ifdef __cplusplus 00166 } 00167 #endif 00168 00169 #endif /* __CORE_CM4_H_GENERIC */ 00170 00171 #ifndef __CMSIS_GENERIC 00172 00173 #ifndef __CORE_CM4_H_DEPENDANT 00174 #define __CORE_CM4_H_DEPENDANT 00175 00176 #ifdef __cplusplus 00177 extern "C" { 00178 #endif 00179 00180 /* check device defines and use defaults */ 00181 #if defined __CHECK_DEVICE_DEFINES 00182 #ifndef __CM4_REV 00183 #define __CM4_REV 0x0000U 00184 #warning "__CM4_REV not defined in device header file; using default!" 00185 #endif 00186 00187 #ifndef __FPU_PRESENT 00188 #define __FPU_PRESENT 0U 00189 #warning "__FPU_PRESENT not defined in device header file; using default!" 00190 #endif 00191 00192 #ifndef __MPU_PRESENT 00193 #define __MPU_PRESENT 0U 00194 #warning "__MPU_PRESENT not defined in device header file; using default!" 00195 #endif 00196 00197 #ifndef __NVIC_PRIO_BITS 00198 #define __NVIC_PRIO_BITS 3U 00199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00200 #endif 00201 00202 #ifndef __Vendor_SysTickConfig 00203 #define __Vendor_SysTickConfig 0U 00204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00205 #endif 00206 #endif 00207 00208 /* IO definitions (access restrictions to peripheral registers) */ 00209 /** 00210 \defgroup CMSIS_glob_defs CMSIS Global Defines 00211 00212 <strong>IO Type Qualifiers</strong> are used 00213 \li to specify the access to peripheral variables. 00214 \li for automatic generation of peripheral register debug information. 00215 */ 00216 #ifdef __cplusplus 00217 #define __I volatile /*!< Defines 'read only' permissions */ 00218 #else 00219 #define __I volatile const /*!< Defines 'read only' permissions */ 00220 #endif 00221 #define __O volatile /*!< Defines 'write only' permissions */ 00222 #define __IO volatile /*!< Defines 'read / write' permissions */ 00223 00224 /* following defines should be used for structure members */ 00225 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00226 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00227 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00228 00229 /*@} end of group Cortex_M4 */ 00230 00231 00232 00233 /******************************************************************************* 00234 * Register Abstraction 00235 Core Register contain: 00236 - Core Register 00237 - Core NVIC Register 00238 - Core SCB Register 00239 - Core SysTick Register 00240 - Core Debug Register 00241 - Core MPU Register 00242 - Core FPU Register 00243 ******************************************************************************/ 00244 /** 00245 \defgroup CMSIS_core_register Defines and Type Definitions 00246 \brief Type definitions and defines for Cortex-M processor based devices. 00247 */ 00248 00249 /** 00250 \ingroup CMSIS_core_register 00251 \defgroup CMSIS_CORE Status and Control Registers 00252 \brief Core Register type definitions. 00253 @{ 00254 */ 00255 00256 /** 00257 \brief Union type to access the Application Program Status Register (APSR). 00258 */ 00259 typedef union 00260 { 00261 struct 00262 { 00263 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00264 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00265 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00266 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00271 } b; /*!< Structure used for bit access */ 00272 uint32_t w; /*!< Type used for word access */ 00273 } APSR_Type; 00274 00275 /* APSR Register Definitions */ 00276 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00277 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00278 00279 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00280 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00281 00282 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00283 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00284 00285 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00286 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00287 00288 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 00289 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 00290 00291 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 00292 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 00293 00294 00295 /** 00296 \brief Union type to access the Interrupt Program Status Register (IPSR). 00297 */ 00298 typedef union 00299 { 00300 struct 00301 { 00302 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00303 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00304 } b; /*!< Structure used for bit access */ 00305 uint32_t w; /*!< Type used for word access */ 00306 } IPSR_Type; 00307 00308 /* IPSR Register Definitions */ 00309 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00310 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00311 00312 00313 /** 00314 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00315 */ 00316 typedef union 00317 { 00318 struct 00319 { 00320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00321 uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 00322 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 00323 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00324 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00325 uint32_t T:1; /*!< bit: 24 Thumb bit */ 00326 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 00327 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00328 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00329 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00330 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00331 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00332 } b; /*!< Structure used for bit access */ 00333 uint32_t w; /*!< Type used for word access */ 00334 } xPSR_Type; 00335 00336 /* xPSR Register Definitions */ 00337 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00338 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00339 00340 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00341 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00342 00343 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00344 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00345 00346 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00347 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00348 00349 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 00350 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 00351 00352 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ 00353 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ 00354 00355 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00356 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00357 00358 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 00359 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 00360 00361 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ 00362 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ 00363 00364 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00365 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00366 00367 00368 /** 00369 \brief Union type to access the Control Registers (CONTROL). 00370 */ 00371 typedef union 00372 { 00373 struct 00374 { 00375 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00376 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00377 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00378 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00379 } b; /*!< Structure used for bit access */ 00380 uint32_t w; /*!< Type used for word access */ 00381 } CONTROL_Type; 00382 00383 /* CONTROL Register Definitions */ 00384 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 00385 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 00386 00387 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00388 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00389 00390 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00391 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00392 00393 /*@} end of group CMSIS_CORE */ 00394 00395 00396 /** 00397 \ingroup CMSIS_core_register 00398 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00399 \brief Type definitions for the NVIC Registers 00400 @{ 00401 */ 00402 00403 /** 00404 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00405 */ 00406 typedef struct 00407 { 00408 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00409 uint32_t RESERVED0[24U]; 00410 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00411 uint32_t RESERVED1[24U]; 00412 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00413 uint32_t RESERVED2[24U]; 00414 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00415 uint32_t RESERVED3[24U]; 00416 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00417 uint32_t RESERVED4[56U]; 00418 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00419 uint32_t RESERVED5[644U]; 00420 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00421 } NVIC_Type; 00422 00423 /* Software Triggered Interrupt Register Definitions */ 00424 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 00425 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 00426 00427 /*@} end of group CMSIS_NVIC */ 00428 00429 00430 /** 00431 \ingroup CMSIS_core_register 00432 \defgroup CMSIS_SCB System Control Block (SCB) 00433 \brief Type definitions for the System Control Block Registers 00434 @{ 00435 */ 00436 00437 /** 00438 \brief Structure type to access the System Control Block (SCB). 00439 */ 00440 typedef struct 00441 { 00442 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00443 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00444 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00445 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00446 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00447 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00448 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00449 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00450 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00451 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00452 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00453 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00454 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00455 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00456 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00457 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00458 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00459 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00460 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00461 uint32_t RESERVED0[5U]; 00462 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00463 } SCB_Type; 00464 00465 /* SCB CPUID Register Definitions */ 00466 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00467 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00468 00469 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00470 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00471 00472 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00473 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00474 00475 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00476 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00477 00478 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00479 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00480 00481 /* SCB Interrupt Control State Register Definitions */ 00482 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 00483 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00484 00485 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00486 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00487 00488 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00489 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00490 00491 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00492 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00493 00494 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00495 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00496 00497 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00498 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00499 00500 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00501 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00502 00503 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00504 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00505 00506 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00507 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00508 00509 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00510 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00511 00512 /* SCB Vector Table Offset Register Definitions */ 00513 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00514 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00515 00516 /* SCB Application Interrupt and Reset Control Register Definitions */ 00517 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00518 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00519 00520 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00521 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00522 00523 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00524 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00525 00526 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 00527 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00528 00529 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00530 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00531 00532 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00533 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00534 00535 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ 00536 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 00537 00538 /* SCB System Control Register Definitions */ 00539 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00540 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00541 00542 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00543 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00544 00545 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00546 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00547 00548 /* SCB Configuration Control Register Definitions */ 00549 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 00550 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00551 00552 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00553 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00554 00555 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00556 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00557 00558 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00559 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00560 00561 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00562 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00563 00564 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ 00565 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 00566 00567 /* SCB System Handler Control and State Register Definitions */ 00568 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 00569 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00570 00571 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 00572 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00573 00574 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 00575 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00576 00577 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00578 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00579 00580 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00581 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00582 00583 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00584 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00585 00586 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 00587 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00588 00589 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00590 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00591 00592 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00593 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00594 00595 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 00596 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00597 00598 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00599 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00600 00601 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 00602 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00603 00604 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 00605 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00606 00607 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 00608 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00609 00610 /* SCB Configurable Fault Status Register Definitions */ 00611 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 00612 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00613 00614 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 00615 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00616 00617 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00618 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00619 00620 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 00621 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 00622 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 00623 00624 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ 00625 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ 00626 00627 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 00628 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 00629 00630 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 00631 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 00632 00633 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 00634 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 00635 00636 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 00637 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 00638 00639 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 00640 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 00641 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 00642 00643 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ 00644 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ 00645 00646 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 00647 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 00648 00649 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 00650 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 00651 00652 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 00653 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 00654 00655 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 00656 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 00657 00658 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 00659 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 00660 00661 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 00662 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 00663 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 00664 00665 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 00666 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 00667 00668 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 00669 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 00670 00671 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 00672 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 00673 00674 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 00675 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 00676 00677 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 00678 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 00679 00680 /* SCB Hard Fault Status Register Definitions */ 00681 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 00682 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00683 00684 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 00685 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00686 00687 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 00688 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00689 00690 /* SCB Debug Fault Status Register Definitions */ 00691 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 00692 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00693 00694 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 00695 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00696 00697 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 00698 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00699 00700 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 00701 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00702 00703 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 00704 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 00705 00706 /*@} end of group CMSIS_SCB */ 00707 00708 00709 /** 00710 \ingroup CMSIS_core_register 00711 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00712 \brief Type definitions for the System Control and ID Register not in the SCB 00713 @{ 00714 */ 00715 00716 /** 00717 \brief Structure type to access the System Control and ID Register not in the SCB. 00718 */ 00719 typedef struct 00720 { 00721 uint32_t RESERVED0[1U]; 00722 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00723 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00724 } SCnSCB_Type; 00725 00726 /* Interrupt Controller Type Register Definitions */ 00727 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 00728 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 00729 00730 /* Auxiliary Control Register Definitions */ 00731 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ 00732 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ 00733 00734 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ 00735 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ 00736 00737 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ 00738 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 00739 00740 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ 00741 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 00742 00743 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 00744 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 00745 00746 /*@} end of group CMSIS_SCnotSCB */ 00747 00748 00749 /** 00750 \ingroup CMSIS_core_register 00751 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00752 \brief Type definitions for the System Timer Registers. 00753 @{ 00754 */ 00755 00756 /** 00757 \brief Structure type to access the System Timer (SysTick). 00758 */ 00759 typedef struct 00760 { 00761 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00762 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00763 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00764 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00765 } SysTick_Type; 00766 00767 /* SysTick Control / Status Register Definitions */ 00768 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00769 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00770 00771 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00772 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00773 00774 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00775 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00776 00777 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00778 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00779 00780 /* SysTick Reload Register Definitions */ 00781 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00782 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00783 00784 /* SysTick Current Register Definitions */ 00785 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00786 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00787 00788 /* SysTick Calibration Register Definitions */ 00789 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00790 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00791 00792 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00793 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00794 00795 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00796 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00797 00798 /*@} end of group CMSIS_SysTick */ 00799 00800 00801 /** 00802 \ingroup CMSIS_core_register 00803 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 00804 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 00805 @{ 00806 */ 00807 00808 /** 00809 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 00810 */ 00811 typedef struct 00812 { 00813 __OM union 00814 { 00815 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 00816 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 00817 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 00818 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 00819 uint32_t RESERVED0[864U]; 00820 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 00821 uint32_t RESERVED1[15U]; 00822 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 00823 uint32_t RESERVED2[15U]; 00824 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 00825 uint32_t RESERVED3[32U]; 00826 uint32_t RESERVED4[43U]; 00827 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 00828 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 00829 uint32_t RESERVED5[6U]; 00830 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 00831 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 00832 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 00833 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 00834 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 00835 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 00836 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 00837 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 00838 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 00839 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 00840 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 00841 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 00842 } ITM_Type; 00843 00844 /* ITM Trace Privilege Register Definitions */ 00845 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 00846 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 00847 00848 /* ITM Trace Control Register Definitions */ 00849 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 00850 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 00851 00852 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ 00853 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 00854 00855 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 00856 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 00857 00858 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ 00859 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 00860 00861 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 00862 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 00863 00864 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 00865 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 00866 00867 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 00868 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 00869 00870 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 00871 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 00872 00873 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 00874 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 00875 00876 /* ITM Lock Status Register Definitions */ 00877 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 00878 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 00879 00880 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 00881 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 00882 00883 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 00884 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 00885 00886 /*@}*/ /* end of group CMSIS_ITM */ 00887 00888 00889 /** 00890 \ingroup CMSIS_core_register 00891 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00892 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00893 @{ 00894 */ 00895 00896 /** 00897 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00898 */ 00899 typedef struct 00900 { 00901 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 00902 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 00903 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 00904 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 00905 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 00906 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 00907 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 00908 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00909 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00910 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 00911 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00912 uint32_t RESERVED0[1U]; 00913 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00914 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 00915 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00916 uint32_t RESERVED1[1U]; 00917 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 00918 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 00919 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 00920 uint32_t RESERVED2[1U]; 00921 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 00922 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 00923 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 00924 } DWT_Type; 00925 00926 /* DWT Control Register Definitions */ 00927 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 00928 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 00929 00930 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 00931 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 00932 00933 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 00934 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 00935 00936 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 00937 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 00938 00939 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 00940 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 00941 00942 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 00943 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 00944 00945 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 00946 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 00947 00948 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 00949 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 00950 00951 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 00952 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 00953 00954 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 00955 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 00956 00957 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 00958 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 00959 00960 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 00961 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 00962 00963 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 00964 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 00965 00966 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 00967 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 00968 00969 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 00970 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 00971 00972 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 00973 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 00974 00975 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 00976 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 00977 00978 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 00979 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 00980 00981 /* DWT CPI Count Register Definitions */ 00982 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 00983 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 00984 00985 /* DWT Exception Overhead Count Register Definitions */ 00986 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 00987 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 00988 00989 /* DWT Sleep Count Register Definitions */ 00990 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 00991 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 00992 00993 /* DWT LSU Count Register Definitions */ 00994 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 00995 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 00996 00997 /* DWT Folded-instruction Count Register Definitions */ 00998 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 00999 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 01000 01001 /* DWT Comparator Mask Register Definitions */ 01002 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ 01003 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 01004 01005 /* DWT Comparator Function Register Definitions */ 01006 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 01007 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 01008 01009 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ 01010 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 01011 01012 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ 01013 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 01014 01015 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 01016 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 01017 01018 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ 01019 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 01020 01021 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ 01022 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 01023 01024 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ 01025 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 01026 01027 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ 01028 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 01029 01030 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ 01031 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 01032 01033 /*@}*/ /* end of group CMSIS_DWT */ 01034 01035 01036 /** 01037 \ingroup CMSIS_core_register 01038 \defgroup CMSIS_TPI Trace Port Interface (TPI) 01039 \brief Type definitions for the Trace Port Interface (TPI) 01040 @{ 01041 */ 01042 01043 /** 01044 \brief Structure type to access the Trace Port Interface Register (TPI). 01045 */ 01046 typedef struct 01047 { 01048 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 01049 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 01050 uint32_t RESERVED0[2U]; 01051 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 01052 uint32_t RESERVED1[55U]; 01053 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 01054 uint32_t RESERVED2[131U]; 01055 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 01056 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 01057 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 01058 uint32_t RESERVED3[759U]; 01059 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 01060 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 01061 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 01062 uint32_t RESERVED4[1U]; 01063 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 01064 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 01065 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 01066 uint32_t RESERVED5[39U]; 01067 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 01068 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 01069 uint32_t RESERVED7[8U]; 01070 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 01071 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 01072 } TPI_Type; 01073 01074 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01075 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 01076 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 01077 01078 /* TPI Selected Pin Protocol Register Definitions */ 01079 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 01080 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 01081 01082 /* TPI Formatter and Flush Status Register Definitions */ 01083 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 01084 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01085 01086 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 01087 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01088 01089 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 01090 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01091 01092 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 01093 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 01094 01095 /* TPI Formatter and Flush Control Register Definitions */ 01096 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 01097 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01098 01099 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 01100 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 01101 01102 /* TPI TRIGGER Register Definitions */ 01103 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 01104 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 01105 01106 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 01107 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 01108 #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 01109 01110 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 01111 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 01112 01113 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 01114 #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 01115 01116 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 01117 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 01118 01119 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 01120 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 01121 01122 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 01123 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 01124 01125 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 01126 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 01127 01128 /* TPI ITATBCTR2 Register Definitions */ 01129 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ 01130 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ 01131 01132 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ 01133 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ 01134 01135 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 01136 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 01137 #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 01138 01139 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 01140 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 01141 01142 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 01143 #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 01144 01145 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 01146 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 01147 01148 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 01149 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 01150 01151 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 01152 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 01153 01154 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 01155 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 01156 01157 /* TPI ITATBCTR0 Register Definitions */ 01158 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ 01159 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ 01160 01161 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ 01162 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ 01163 01164 /* TPI Integration Mode Control Register Definitions */ 01165 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 01166 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 01167 01168 /* TPI DEVID Register Definitions */ 01169 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 01170 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01171 01172 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 01173 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01174 01175 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 01176 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01177 01178 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 01179 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 01180 01181 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 01182 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01183 01184 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 01185 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 01186 01187 /* TPI DEVTYPE Register Definitions */ 01188 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 01189 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 01190 01191 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 01192 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01193 01194 /*@}*/ /* end of group CMSIS_TPI */ 01195 01196 01197 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01198 /** 01199 \ingroup CMSIS_core_register 01200 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01201 \brief Type definitions for the Memory Protection Unit (MPU) 01202 @{ 01203 */ 01204 01205 /** 01206 \brief Structure type to access the Memory Protection Unit (MPU). 01207 */ 01208 typedef struct 01209 { 01210 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01211 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01212 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 01213 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01214 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 01215 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 01216 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 01217 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 01218 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 01219 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 01220 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 01221 } MPU_Type; 01222 01223 #define MPU_TYPE_RALIASES 4U 01224 01225 /* MPU Type Register Definitions */ 01226 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 01227 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01228 01229 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 01230 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01231 01232 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 01233 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 01234 01235 /* MPU Control Register Definitions */ 01236 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 01237 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01238 01239 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 01240 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01241 01242 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 01243 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 01244 01245 /* MPU Region Number Register Definitions */ 01246 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 01247 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 01248 01249 /* MPU Region Base Address Register Definitions */ 01250 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 01251 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 01252 01253 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 01254 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 01255 01256 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 01257 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 01258 01259 /* MPU Region Attribute and Size Register Definitions */ 01260 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 01261 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 01262 01263 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 01264 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 01265 01266 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 01267 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 01268 01269 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 01270 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 01271 01272 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 01273 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 01274 01275 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 01276 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 01277 01278 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 01279 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 01280 01281 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 01282 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 01283 01284 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 01285 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 01286 01287 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 01288 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 01289 01290 /*@} end of group CMSIS_MPU */ 01291 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 01292 01293 01294 /** 01295 \ingroup CMSIS_core_register 01296 \defgroup CMSIS_FPU Floating Point Unit (FPU) 01297 \brief Type definitions for the Floating Point Unit (FPU) 01298 @{ 01299 */ 01300 01301 /** 01302 \brief Structure type to access the Floating Point Unit (FPU). 01303 */ 01304 typedef struct 01305 { 01306 uint32_t RESERVED0[1U]; 01307 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 01308 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 01309 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 01310 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 01311 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 01312 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ 01313 } FPU_Type; 01314 01315 /* Floating-Point Context Control Register Definitions */ 01316 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 01317 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 01318 01319 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 01320 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 01321 01322 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 01323 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 01324 01325 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 01326 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 01327 01328 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 01329 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 01330 01331 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 01332 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 01333 01334 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 01335 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 01336 01337 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 01338 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 01339 01340 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 01341 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 01342 01343 /* Floating-Point Context Address Register Definitions */ 01344 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 01345 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 01346 01347 /* Floating-Point Default Status Control Register Definitions */ 01348 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 01349 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 01350 01351 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 01352 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 01353 01354 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 01355 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 01356 01357 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 01358 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 01359 01360 /* Media and FP Feature Register 0 Definitions */ 01361 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ 01362 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 01363 01364 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ 01365 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 01366 01367 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ 01368 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 01369 01370 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ 01371 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 01372 01373 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ 01374 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 01375 01376 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ 01377 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 01378 01379 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ 01380 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 01381 01382 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ 01383 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 01384 01385 /* Media and FP Feature Register 1 Definitions */ 01386 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ 01387 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 01388 01389 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 01390 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 01391 01392 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 01393 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 01394 01395 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 01396 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 01397 01398 /* Media and FP Feature Register 2 Definitions */ 01399 01400 #define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ 01401 #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ 01402 01403 /*@} end of group CMSIS_FPU */ 01404 01405 01406 /** 01407 \ingroup CMSIS_core_register 01408 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01409 \brief Type definitions for the Core Debug Registers 01410 @{ 01411 */ 01412 01413 /** 01414 \brief Structure type to access the Core Debug Register (CoreDebug). 01415 */ 01416 typedef struct 01417 { 01418 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01419 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01420 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01421 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01422 } CoreDebug_Type; 01423 01424 /* Debug Halting Control and Status Register Definitions */ 01425 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01426 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01427 01428 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01429 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01430 01431 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01432 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01433 01434 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01435 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01436 01437 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01438 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01439 01440 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01441 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01442 01443 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01444 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01445 01446 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01447 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01448 01449 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01450 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01451 01452 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01453 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01454 01455 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01456 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01457 01458 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01459 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01460 01461 /* Debug Core Register Selector Register Definitions */ 01462 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01463 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01464 01465 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01466 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01467 01468 /* Debug Exception and Monitor Control Register Definitions */ 01469 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 01470 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01471 01472 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 01473 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01474 01475 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 01476 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01477 01478 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 01479 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01480 01481 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 01482 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01483 01484 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01485 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01486 01487 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 01488 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01489 01490 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01491 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01492 01493 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 01494 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01495 01496 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01497 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01498 01499 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01500 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01501 01502 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 01503 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01504 01505 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01506 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01507 01508 /*@} end of group CMSIS_CoreDebug */ 01509 01510 01511 /** 01512 \ingroup CMSIS_core_register 01513 \defgroup CMSIS_core_bitfield Core register bit field macros 01514 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01515 @{ 01516 */ 01517 01518 /** 01519 \brief Mask and shift a bit field value for use in a register bit range. 01520 \param[in] field Name of the register bit field. 01521 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01522 \return Masked and shifted value. 01523 */ 01524 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01525 01526 /** 01527 \brief Mask and shift a register value to extract a bit filed value. 01528 \param[in] field Name of the register bit field. 01529 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01530 \return Masked and shifted bit field value. 01531 */ 01532 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01533 01534 /*@} end of group CMSIS_core_bitfield */ 01535 01536 01537 /** 01538 \ingroup CMSIS_core_register 01539 \defgroup CMSIS_core_base Core Definitions 01540 \brief Definitions for base addresses, unions, and structures. 01541 @{ 01542 */ 01543 01544 /* Memory mapping of Core Hardware */ 01545 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01546 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01547 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01548 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01549 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01550 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01551 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01552 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01553 01554 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01555 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01556 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01557 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01558 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01559 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01560 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01561 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 01562 01563 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01564 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01565 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01566 #endif 01567 01568 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 01569 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 01570 01571 /*@} */ 01572 01573 01574 01575 /******************************************************************************* 01576 * Hardware Abstraction Layer 01577 Core Function Interface contains: 01578 - Core NVIC Functions 01579 - Core SysTick Functions 01580 - Core Debug Functions 01581 - Core Register Access Functions 01582 ******************************************************************************/ 01583 /** 01584 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01585 */ 01586 01587 01588 01589 /* ########################## NVIC functions #################################### */ 01590 /** 01591 \ingroup CMSIS_Core_FunctionInterface 01592 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01593 \brief Functions that manage interrupts and exceptions via the NVIC. 01594 @{ 01595 */ 01596 01597 #ifdef CMSIS_NVIC_VIRTUAL 01598 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 01599 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 01600 #endif 01601 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 01602 #else 01603 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 01604 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 01605 #define NVIC_EnableIRQ __NVIC_EnableIRQ 01606 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 01607 #define NVIC_DisableIRQ __NVIC_DisableIRQ 01608 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 01609 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 01610 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 01611 #define NVIC_GetActive __NVIC_GetActive 01612 #define NVIC_SetPriority __NVIC_SetPriority 01613 #define NVIC_GetPriority __NVIC_GetPriority 01614 #define NVIC_SystemReset __NVIC_SystemReset 01615 #endif /* CMSIS_NVIC_VIRTUAL */ 01616 01617 #ifdef CMSIS_VECTAB_VIRTUAL 01618 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01619 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 01620 #endif 01621 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01622 #else 01623 #define NVIC_SetVector __NVIC_SetVector 01624 #define NVIC_GetVector __NVIC_GetVector 01625 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 01626 01627 #define NVIC_USER_IRQ_OFFSET 16 01628 01629 01630 /* The following EXC_RETURN values are saved the LR on exception entry */ 01631 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 01632 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 01633 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 01634 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ 01635 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ 01636 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ 01637 01638 01639 /** 01640 \brief Set Priority Grouping 01641 \details Sets the priority grouping field using the required unlock sequence. 01642 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 01643 Only values from 0..7 are used. 01644 In case of a conflict between priority grouping and available 01645 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01646 \param [in] PriorityGroup Priority grouping field. 01647 */ 01648 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01649 { 01650 uint32_t reg_value; 01651 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01652 01653 reg_value = SCB->AIRCR; /* read old register configuration */ 01654 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 01655 reg_value = (reg_value | 01656 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01657 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 01658 SCB->AIRCR = reg_value; 01659 } 01660 01661 01662 /** 01663 \brief Get Priority Grouping 01664 \details Reads the priority grouping field from the NVIC Interrupt Controller. 01665 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 01666 */ 01667 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 01668 { 01669 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 01670 } 01671 01672 01673 /** 01674 \brief Enable Interrupt 01675 \details Enables a device specific interrupt in the NVIC interrupt controller. 01676 \param [in] IRQn Device specific interrupt number. 01677 \note IRQn must not be negative. 01678 */ 01679 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 01680 { 01681 if ((int32_t)(IRQn) >= 0) 01682 { 01683 __COMPILER_BARRIER(); 01684 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01685 __COMPILER_BARRIER(); 01686 } 01687 } 01688 01689 01690 /** 01691 \brief Get Interrupt Enable status 01692 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 01693 \param [in] IRQn Device specific interrupt number. 01694 \return 0 Interrupt is not enabled. 01695 \return 1 Interrupt is enabled. 01696 \note IRQn must not be negative. 01697 */ 01698 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 01699 { 01700 if ((int32_t)(IRQn) >= 0) 01701 { 01702 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01703 } 01704 else 01705 { 01706 return(0U); 01707 } 01708 } 01709 01710 01711 /** 01712 \brief Disable Interrupt 01713 \details Disables a device specific interrupt in the NVIC interrupt controller. 01714 \param [in] IRQn Device specific interrupt number. 01715 \note IRQn must not be negative. 01716 */ 01717 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 01718 { 01719 if ((int32_t)(IRQn) >= 0) 01720 { 01721 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01722 __DSB(); 01723 __ISB(); 01724 } 01725 } 01726 01727 01728 /** 01729 \brief Get Pending Interrupt 01730 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 01731 \param [in] IRQn Device specific interrupt number. 01732 \return 0 Interrupt status is not pending. 01733 \return 1 Interrupt status is pending. 01734 \note IRQn must not be negative. 01735 */ 01736 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 01737 { 01738 if ((int32_t)(IRQn) >= 0) 01739 { 01740 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01741 } 01742 else 01743 { 01744 return(0U); 01745 } 01746 } 01747 01748 01749 /** 01750 \brief Set Pending Interrupt 01751 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 01752 \param [in] IRQn Device specific interrupt number. 01753 \note IRQn must not be negative. 01754 */ 01755 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 01756 { 01757 if ((int32_t)(IRQn) >= 0) 01758 { 01759 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01760 } 01761 } 01762 01763 01764 /** 01765 \brief Clear Pending Interrupt 01766 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 01767 \param [in] IRQn Device specific interrupt number. 01768 \note IRQn must not be negative. 01769 */ 01770 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01771 { 01772 if ((int32_t)(IRQn) >= 0) 01773 { 01774 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01775 } 01776 } 01777 01778 01779 /** 01780 \brief Get Active Interrupt 01781 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 01782 \param [in] IRQn Device specific interrupt number. 01783 \return 0 Interrupt status is not active. 01784 \return 1 Interrupt status is active. 01785 \note IRQn must not be negative. 01786 */ 01787 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 01788 { 01789 if ((int32_t)(IRQn) >= 0) 01790 { 01791 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01792 } 01793 else 01794 { 01795 return(0U); 01796 } 01797 } 01798 01799 01800 /** 01801 \brief Set Interrupt Priority 01802 \details Sets the priority of a device specific interrupt or a processor exception. 01803 The interrupt number can be positive to specify a device specific interrupt, 01804 or negative to specify a processor exception. 01805 \param [in] IRQn Interrupt number. 01806 \param [in] priority Priority to set. 01807 \note The priority cannot be set for every processor exception. 01808 */ 01809 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01810 { 01811 if ((int32_t)(IRQn) >= 0) 01812 { 01813 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01814 } 01815 else 01816 { 01817 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01818 } 01819 } 01820 01821 01822 /** 01823 \brief Get Interrupt Priority 01824 \details Reads the priority of a device specific interrupt or a processor exception. 01825 The interrupt number can be positive to specify a device specific interrupt, 01826 or negative to specify a processor exception. 01827 \param [in] IRQn Interrupt number. 01828 \return Interrupt Priority. 01829 Value is aligned automatically to the implemented priority bits of the microcontroller. 01830 */ 01831 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 01832 { 01833 01834 if ((int32_t)(IRQn) >= 0) 01835 { 01836 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 01837 } 01838 else 01839 { 01840 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 01841 } 01842 } 01843 01844 01845 /** 01846 \brief Encode Priority 01847 \details Encodes the priority for an interrupt with the given priority group, 01848 preemptive priority value, and subpriority value. 01849 In case of a conflict between priority grouping and available 01850 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01851 \param [in] PriorityGroup Used priority group. 01852 \param [in] PreemptPriority Preemptive priority value (starting from 0). 01853 \param [in] SubPriority Subpriority value (starting from 0). 01854 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 01855 */ 01856 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01857 { 01858 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01859 uint32_t PreemptPriorityBits; 01860 uint32_t SubPriorityBits; 01861 01862 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01863 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01864 01865 return ( 01866 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 01867 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 01868 ); 01869 } 01870 01871 01872 /** 01873 \brief Decode Priority 01874 \details Decodes an interrupt priority value with a given priority group to 01875 preemptive priority value and subpriority value. 01876 In case of a conflict between priority grouping and available 01877 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 01878 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 01879 \param [in] PriorityGroup Used priority group. 01880 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 01881 \param [out] pSubPriority Subpriority value (starting from 0). 01882 */ 01883 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 01884 { 01885 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01886 uint32_t PreemptPriorityBits; 01887 uint32_t SubPriorityBits; 01888 01889 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01890 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01891 01892 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 01893 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 01894 } 01895 01896 01897 /** 01898 \brief Set Interrupt Vector 01899 \details Sets an interrupt vector in SRAM based interrupt vector table. 01900 The interrupt number can be positive to specify a device specific interrupt, 01901 or negative to specify a processor exception. 01902 VTOR must been relocated to SRAM before. 01903 \param [in] IRQn Interrupt number 01904 \param [in] vector Address of interrupt handler function 01905 */ 01906 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 01907 { 01908 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01909 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 01910 /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ 01911 } 01912 01913 01914 /** 01915 \brief Get Interrupt Vector 01916 \details Reads an interrupt vector from interrupt vector table. 01917 The interrupt number can be positive to specify a device specific interrupt, 01918 or negative to specify a processor exception. 01919 \param [in] IRQn Interrupt number. 01920 \return Address of interrupt handler function 01921 */ 01922 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 01923 { 01924 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01925 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 01926 } 01927 01928 01929 /** 01930 \brief System Reset 01931 \details Initiates a system reset request to reset the MCU. 01932 */ 01933 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 01934 { 01935 __DSB(); /* Ensure all outstanding memory accesses included 01936 buffered write are completed before reset */ 01937 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01938 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 01939 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 01940 __DSB(); /* Ensure completion of memory access */ 01941 01942 for(;;) /* wait until reset */ 01943 { 01944 __NOP(); 01945 } 01946 } 01947 01948 /*@} end of CMSIS_Core_NVICFunctions */ 01949 01950 01951 /* ########################## MPU functions #################################### */ 01952 01953 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01954 01955 #include "mpu_armv7.h" 01956 01957 #endif 01958 01959 01960 /* ########################## FPU functions #################################### */ 01961 /** 01962 \ingroup CMSIS_Core_FunctionInterface 01963 \defgroup CMSIS_Core_FpuFunctions FPU Functions 01964 \brief Function that provides FPU type. 01965 @{ 01966 */ 01967 01968 /** 01969 \brief get FPU type 01970 \details returns the FPU type 01971 \returns 01972 - \b 0: No FPU 01973 - \b 1: Single precision FPU 01974 - \b 2: Double + Single precision FPU 01975 */ 01976 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 01977 { 01978 uint32_t mvfr0; 01979 01980 mvfr0 = FPU->MVFR0; 01981 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) 01982 { 01983 return 1U; /* Single precision FPU */ 01984 } 01985 else 01986 { 01987 return 0U; /* No FPU */ 01988 } 01989 } 01990 01991 01992 /*@} end of CMSIS_Core_FpuFunctions */ 01993 01994 01995 01996 /* ################################## SysTick function ############################################ */ 01997 /** 01998 \ingroup CMSIS_Core_FunctionInterface 01999 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 02000 \brief Functions that configure the System. 02001 @{ 02002 */ 02003 02004 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 02005 02006 /** 02007 \brief System Tick Configuration 02008 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 02009 Counter is in free running mode to generate periodic interrupts. 02010 \param [in] ticks Number of ticks between two interrupts. 02011 \return 0 Function succeeded. 02012 \return 1 Function failed. 02013 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 02014 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 02015 must contain a vendor-specific implementation of this function. 02016 */ 02017 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 02018 { 02019 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 02020 { 02021 return (1UL); /* Reload value impossible */ 02022 } 02023 02024 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 02025 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 02026 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 02027 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02028 SysTick_CTRL_TICKINT_Msk | 02029 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02030 return (0UL); /* Function successful */ 02031 } 02032 02033 #endif 02034 02035 /*@} end of CMSIS_Core_SysTickFunctions */ 02036 02037 02038 02039 /* ##################################### Debug In/Output function ########################################### */ 02040 /** 02041 \ingroup CMSIS_Core_FunctionInterface 02042 \defgroup CMSIS_core_DebugFunctions ITM Functions 02043 \brief Functions that access the ITM debug interface. 02044 @{ 02045 */ 02046 02047 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 02048 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 02049 02050 02051 /** 02052 \brief ITM Send Character 02053 \details Transmits a character via the ITM channel 0, and 02054 \li Just returns when no debugger is connected that has booked the output. 02055 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 02056 \param [in] ch Character to transmit. 02057 \returns Character to transmit. 02058 */ 02059 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 02060 { 02061 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 02062 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 02063 { 02064 while (ITM->PORT[0U].u32 == 0UL) 02065 { 02066 __NOP(); 02067 } 02068 ITM->PORT[0U].u8 = (uint8_t)ch; 02069 } 02070 return (ch); 02071 } 02072 02073 02074 /** 02075 \brief ITM Receive Character 02076 \details Inputs a character via the external variable \ref ITM_RxBuffer. 02077 \return Received character. 02078 \return -1 No character pending. 02079 */ 02080 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 02081 { 02082 int32_t ch = -1; /* no character available */ 02083 02084 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 02085 { 02086 ch = ITM_RxBuffer; 02087 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 02088 } 02089 02090 return (ch); 02091 } 02092 02093 02094 /** 02095 \brief ITM Check Character 02096 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 02097 \return 0 No character available. 02098 \return 1 Character available. 02099 */ 02100 __STATIC_INLINE int32_t ITM_CheckChar (void) 02101 { 02102 02103 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 02104 { 02105 return (0); /* no character available */ 02106 } 02107 else 02108 { 02109 return (1); /* character available */ 02110 } 02111 } 02112 02113 /*@} end of CMSIS_core_DebugFunctions */ 02114 02115 02116 02117 02118 #ifdef __cplusplus 02119 } 02120 #endif 02121 02122 #endif /* __CORE_CM4_H_DEPENDANT */ 02123 02124 #endif /* __CMSIS_GENERIC */
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