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core_cm3.h
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00001 /**************************************************************************//** 00002 * @file core_cm3.h 00003 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File 00004 * @version V5.1.1 00005 * @date 19. August 2019 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__clang__) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_CM3_H_GENERIC 00032 #define __CORE_CM3_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_M3 00060 @{ 00061 */ 00062 00063 #include "cmsis_version.h" 00064 00065 /* CMSIS CM3 definitions */ 00066 #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 00067 #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 00068 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ 00069 __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 00070 00071 #define __CORTEX_M (3U) /*!< Cortex-M Core */ 00072 00073 /** __FPU_USED indicates whether an FPU is used or not. 00074 This core does not support an FPU at all 00075 */ 00076 #define __FPU_USED 0U 00077 00078 #if defined ( __CC_ARM ) 00079 #if defined __TARGET_FPU_VFP 00080 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00081 #endif 00082 00083 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00084 #if defined __ARM_FP 00085 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00086 #endif 00087 00088 #elif defined ( __GNUC__ ) 00089 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00090 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00091 #endif 00092 00093 #elif defined ( __ICCARM__ ) 00094 #if defined __ARMVFP__ 00095 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00096 #endif 00097 00098 #elif defined ( __TI_ARM__ ) 00099 #if defined __TI_VFP_SUPPORT__ 00100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00101 #endif 00102 00103 #elif defined ( __TASKING__ ) 00104 #if defined __FPU_VFP__ 00105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00106 #endif 00107 00108 #elif defined ( __CSMC__ ) 00109 #if ( __CSMC__ & 0x400U) 00110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00111 #endif 00112 00113 #endif 00114 00115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00116 00117 00118 #ifdef __cplusplus 00119 } 00120 #endif 00121 00122 #endif /* __CORE_CM3_H_GENERIC */ 00123 00124 #ifndef __CMSIS_GENERIC 00125 00126 #ifndef __CORE_CM3_H_DEPENDANT 00127 #define __CORE_CM3_H_DEPENDANT 00128 00129 #ifdef __cplusplus 00130 extern "C" { 00131 #endif 00132 00133 /* check device defines and use defaults */ 00134 #if defined __CHECK_DEVICE_DEFINES 00135 #ifndef __CM3_REV 00136 #define __CM3_REV 0x0200U 00137 #warning "__CM3_REV not defined in device header file; using default!" 00138 #endif 00139 00140 #ifndef __MPU_PRESENT 00141 #define __MPU_PRESENT 0U 00142 #warning "__MPU_PRESENT not defined in device header file; using default!" 00143 #endif 00144 00145 #ifndef __NVIC_PRIO_BITS 00146 #define __NVIC_PRIO_BITS 3U 00147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00148 #endif 00149 00150 #ifndef __Vendor_SysTickConfig 00151 #define __Vendor_SysTickConfig 0U 00152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00153 #endif 00154 #endif 00155 00156 /* IO definitions (access restrictions to peripheral registers) */ 00157 /** 00158 \defgroup CMSIS_glob_defs CMSIS Global Defines 00159 00160 <strong>IO Type Qualifiers</strong> are used 00161 \li to specify the access to peripheral variables. 00162 \li for automatic generation of peripheral register debug information. 00163 */ 00164 #ifdef __cplusplus 00165 #define __I volatile /*!< Defines 'read only' permissions */ 00166 #else 00167 #define __I volatile const /*!< Defines 'read only' permissions */ 00168 #endif 00169 #define __O volatile /*!< Defines 'write only' permissions */ 00170 #define __IO volatile /*!< Defines 'read / write' permissions */ 00171 00172 /* following defines should be used for structure members */ 00173 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00174 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00176 00177 /*@} end of group Cortex_M3 */ 00178 00179 00180 00181 /******************************************************************************* 00182 * Register Abstraction 00183 Core Register contain: 00184 - Core Register 00185 - Core NVIC Register 00186 - Core SCB Register 00187 - Core SysTick Register 00188 - Core Debug Register 00189 - Core MPU Register 00190 ******************************************************************************/ 00191 /** 00192 \defgroup CMSIS_core_register Defines and Type Definitions 00193 \brief Type definitions and defines for Cortex-M processor based devices. 00194 */ 00195 00196 /** 00197 \ingroup CMSIS_core_register 00198 \defgroup CMSIS_CORE Status and Control Registers 00199 \brief Core Register type definitions. 00200 @{ 00201 */ 00202 00203 /** 00204 \brief Union type to access the Application Program Status Register (APSR). 00205 */ 00206 typedef union 00207 { 00208 struct 00209 { 00210 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00211 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00212 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00213 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00214 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00215 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00216 } b; /*!< Structure used for bit access */ 00217 uint32_t w; /*!< Type used for word access */ 00218 } APSR_Type; 00219 00220 /* APSR Register Definitions */ 00221 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00222 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00223 00224 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00225 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00226 00227 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00228 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00229 00230 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00231 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00232 00233 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 00234 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 00235 00236 00237 /** 00238 \brief Union type to access the Interrupt Program Status Register (IPSR). 00239 */ 00240 typedef union 00241 { 00242 struct 00243 { 00244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00246 } b; /*!< Structure used for bit access */ 00247 uint32_t w; /*!< Type used for word access */ 00248 } IPSR_Type; 00249 00250 /* IPSR Register Definitions */ 00251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00253 00254 00255 /** 00256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00257 */ 00258 typedef union 00259 { 00260 struct 00261 { 00262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00263 uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 00264 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 00265 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ 00266 uint32_t T:1; /*!< bit: 24 Thumb bit */ 00267 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 00268 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00269 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00270 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00271 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00272 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00273 } b; /*!< Structure used for bit access */ 00274 uint32_t w; /*!< Type used for word access */ 00275 } xPSR_Type; 00276 00277 /* xPSR Register Definitions */ 00278 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00279 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00280 00281 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00282 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00283 00284 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00285 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00286 00287 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00288 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00289 00290 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 00291 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 00292 00293 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ 00294 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ 00295 00296 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00297 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00298 00299 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ 00300 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ 00301 00302 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00304 00305 00306 /** 00307 \brief Union type to access the Control Registers (CONTROL). 00308 */ 00309 typedef union 00310 { 00311 struct 00312 { 00313 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00314 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00315 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00316 } b; /*!< Structure used for bit access */ 00317 uint32_t w; /*!< Type used for word access */ 00318 } CONTROL_Type; 00319 00320 /* CONTROL Register Definitions */ 00321 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00322 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00323 00324 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00325 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00326 00327 /*@} end of group CMSIS_CORE */ 00328 00329 00330 /** 00331 \ingroup CMSIS_core_register 00332 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00333 \brief Type definitions for the NVIC Registers 00334 @{ 00335 */ 00336 00337 /** 00338 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00339 */ 00340 typedef struct 00341 { 00342 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00343 uint32_t RESERVED0[24U]; 00344 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00345 uint32_t RESERVED1[24U]; 00346 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00347 uint32_t RESERVED2[24U]; 00348 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00349 uint32_t RESERVED3[24U]; 00350 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00351 uint32_t RESERVED4[56U]; 00352 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00353 uint32_t RESERVED5[644U]; 00354 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00355 } NVIC_Type; 00356 00357 /* Software Triggered Interrupt Register Definitions */ 00358 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 00359 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 00360 00361 /*@} end of group CMSIS_NVIC */ 00362 00363 00364 /** 00365 \ingroup CMSIS_core_register 00366 \defgroup CMSIS_SCB System Control Block (SCB) 00367 \brief Type definitions for the System Control Block Registers 00368 @{ 00369 */ 00370 00371 /** 00372 \brief Structure type to access the System Control Block (SCB). 00373 */ 00374 typedef struct 00375 { 00376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00377 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00378 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00379 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00380 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00381 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00382 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00383 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00384 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00385 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00386 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00387 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00388 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00389 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00390 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00392 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00393 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00394 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00395 uint32_t RESERVED0[5U]; 00396 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00397 } SCB_Type; 00398 00399 /* SCB CPUID Register Definitions */ 00400 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00401 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00402 00403 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00404 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00405 00406 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00407 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00408 00409 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00410 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00411 00412 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00413 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00414 00415 /* SCB Interrupt Control State Register Definitions */ 00416 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 00417 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00418 00419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00421 00422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00424 00425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00427 00428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00430 00431 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00432 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00433 00434 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00435 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00436 00437 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00438 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00439 00440 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00441 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00442 00443 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00444 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00445 00446 /* SCB Vector Table Offset Register Definitions */ 00447 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ 00448 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ 00449 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ 00450 00451 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00452 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00453 #else 00454 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00455 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00456 #endif 00457 00458 /* SCB Application Interrupt and Reset Control Register Definitions */ 00459 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00460 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00461 00462 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00463 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00464 00465 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00466 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00467 00468 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 00469 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00470 00471 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00472 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00473 00474 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00475 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00476 00477 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ 00478 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 00479 00480 /* SCB System Control Register Definitions */ 00481 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00483 00484 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00485 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00486 00487 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00488 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00489 00490 /* SCB Configuration Control Register Definitions */ 00491 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 00492 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00493 00494 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00495 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00496 00497 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00498 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00499 00500 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00501 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00502 00503 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00504 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00505 00506 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ 00507 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 00508 00509 /* SCB System Handler Control and State Register Definitions */ 00510 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 00511 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00512 00513 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 00514 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00515 00516 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 00517 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00518 00519 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00520 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00521 00522 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00523 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00524 00525 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00526 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00527 00528 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 00529 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00530 00531 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00532 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00533 00534 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00535 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00536 00537 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 00538 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00539 00540 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00541 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00542 00543 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 00544 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00545 00546 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 00547 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00548 00549 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 00550 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00551 00552 /* SCB Configurable Fault Status Register Definitions */ 00553 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 00554 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00555 00556 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 00557 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00558 00559 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00560 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00561 00562 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 00563 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 00564 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 00565 00566 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 00567 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 00568 00569 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 00570 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 00571 00572 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 00573 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 00574 00575 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 00576 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 00577 00578 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 00579 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 00580 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 00581 00582 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 00583 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 00584 00585 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 00586 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 00587 00588 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 00589 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 00590 00591 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 00592 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 00593 00594 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 00595 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 00596 00597 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 00598 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 00599 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 00600 00601 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 00602 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 00603 00604 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 00605 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 00606 00607 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 00608 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 00609 00610 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 00611 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 00612 00613 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 00614 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 00615 00616 /* SCB Hard Fault Status Register Definitions */ 00617 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 00618 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00619 00620 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 00621 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00622 00623 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 00624 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00625 00626 /* SCB Debug Fault Status Register Definitions */ 00627 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 00628 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00629 00630 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 00631 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00632 00633 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 00634 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00635 00636 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 00637 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00638 00639 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 00640 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 00641 00642 /*@} end of group CMSIS_SCB */ 00643 00644 00645 /** 00646 \ingroup CMSIS_core_register 00647 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00648 \brief Type definitions for the System Control and ID Register not in the SCB 00649 @{ 00650 */ 00651 00652 /** 00653 \brief Structure type to access the System Control and ID Register not in the SCB. 00654 */ 00655 typedef struct 00656 { 00657 uint32_t RESERVED0[1U]; 00658 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00659 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) 00660 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00661 #else 00662 uint32_t RESERVED1[1U]; 00663 #endif 00664 } SCnSCB_Type; 00665 00666 /* Interrupt Controller Type Register Definitions */ 00667 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 00668 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 00669 00670 /* Auxiliary Control Register Definitions */ 00671 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) 00672 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ 00673 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ 00674 00675 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ 00676 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ 00677 00678 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ 00679 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 00680 00681 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ 00682 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 00683 00684 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 00685 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 00686 #endif 00687 00688 /*@} end of group CMSIS_SCnotSCB */ 00689 00690 00691 /** 00692 \ingroup CMSIS_core_register 00693 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00694 \brief Type definitions for the System Timer Registers. 00695 @{ 00696 */ 00697 00698 /** 00699 \brief Structure type to access the System Timer (SysTick). 00700 */ 00701 typedef struct 00702 { 00703 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00704 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00705 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00706 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00707 } SysTick_Type; 00708 00709 /* SysTick Control / Status Register Definitions */ 00710 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00711 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00712 00713 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00714 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00715 00716 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00717 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00718 00719 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00720 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00721 00722 /* SysTick Reload Register Definitions */ 00723 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00724 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00725 00726 /* SysTick Current Register Definitions */ 00727 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00728 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00729 00730 /* SysTick Calibration Register Definitions */ 00731 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00732 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00733 00734 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00735 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00736 00737 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00738 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00739 00740 /*@} end of group CMSIS_SysTick */ 00741 00742 00743 /** 00744 \ingroup CMSIS_core_register 00745 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 00746 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 00747 @{ 00748 */ 00749 00750 /** 00751 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 00752 */ 00753 typedef struct 00754 { 00755 __OM union 00756 { 00757 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 00758 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 00759 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 00760 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 00761 uint32_t RESERVED0[864U]; 00762 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 00763 uint32_t RESERVED1[15U]; 00764 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 00765 uint32_t RESERVED2[15U]; 00766 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 00767 uint32_t RESERVED3[32U]; 00768 uint32_t RESERVED4[43U]; 00769 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 00770 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 00771 uint32_t RESERVED5[6U]; 00772 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 00773 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 00774 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 00775 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 00776 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 00777 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 00778 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 00779 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 00780 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 00781 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 00782 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 00783 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 00784 } ITM_Type; 00785 00786 /* ITM Trace Privilege Register Definitions */ 00787 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 00788 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 00789 00790 /* ITM Trace Control Register Definitions */ 00791 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 00792 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 00793 00794 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ 00795 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 00796 00797 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 00798 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 00799 00800 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ 00801 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 00802 00803 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 00804 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 00805 00806 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 00807 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 00808 00809 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 00810 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 00811 00812 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 00813 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 00814 00815 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 00816 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 00817 00818 /* ITM Lock Status Register Definitions */ 00819 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 00820 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 00821 00822 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 00823 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 00824 00825 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 00826 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 00827 00828 /*@}*/ /* end of group CMSIS_ITM */ 00829 00830 00831 /** 00832 \ingroup CMSIS_core_register 00833 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00834 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00835 @{ 00836 */ 00837 00838 /** 00839 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00840 */ 00841 typedef struct 00842 { 00843 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 00844 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 00845 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 00846 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 00847 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 00848 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 00849 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 00850 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00851 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00852 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 00853 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00854 uint32_t RESERVED0[1U]; 00855 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00856 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 00857 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00858 uint32_t RESERVED1[1U]; 00859 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 00860 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 00861 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 00862 uint32_t RESERVED2[1U]; 00863 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 00864 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 00865 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 00866 } DWT_Type; 00867 00868 /* DWT Control Register Definitions */ 00869 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 00870 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 00871 00872 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 00873 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 00874 00875 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 00876 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 00877 00878 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 00879 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 00880 00881 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 00882 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 00883 00884 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 00885 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 00886 00887 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 00888 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 00889 00890 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 00891 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 00892 00893 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 00894 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 00895 00896 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 00897 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 00898 00899 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 00900 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 00901 00902 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 00903 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 00904 00905 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 00906 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 00907 00908 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 00909 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 00910 00911 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 00912 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 00913 00914 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 00915 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 00916 00917 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 00918 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 00919 00920 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 00921 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 00922 00923 /* DWT CPI Count Register Definitions */ 00924 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 00925 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 00926 00927 /* DWT Exception Overhead Count Register Definitions */ 00928 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 00929 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 00930 00931 /* DWT Sleep Count Register Definitions */ 00932 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 00933 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 00934 00935 /* DWT LSU Count Register Definitions */ 00936 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 00937 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 00938 00939 /* DWT Folded-instruction Count Register Definitions */ 00940 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 00941 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 00942 00943 /* DWT Comparator Mask Register Definitions */ 00944 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ 00945 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 00946 00947 /* DWT Comparator Function Register Definitions */ 00948 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 00949 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 00950 00951 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ 00952 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 00953 00954 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ 00955 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 00956 00957 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 00958 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 00959 00960 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ 00961 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 00962 00963 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ 00964 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 00965 00966 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ 00967 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 00968 00969 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ 00970 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 00971 00972 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ 00973 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 00974 00975 /*@}*/ /* end of group CMSIS_DWT */ 00976 00977 00978 /** 00979 \ingroup CMSIS_core_register 00980 \defgroup CMSIS_TPI Trace Port Interface (TPI) 00981 \brief Type definitions for the Trace Port Interface (TPI) 00982 @{ 00983 */ 00984 00985 /** 00986 \brief Structure type to access the Trace Port Interface Register (TPI). 00987 */ 00988 typedef struct 00989 { 00990 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 00991 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 00992 uint32_t RESERVED0[2U]; 00993 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 00994 uint32_t RESERVED1[55U]; 00995 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 00996 uint32_t RESERVED2[131U]; 00997 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 00998 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 00999 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 01000 uint32_t RESERVED3[759U]; 01001 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 01002 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 01003 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 01004 uint32_t RESERVED4[1U]; 01005 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 01006 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 01007 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 01008 uint32_t RESERVED5[39U]; 01009 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 01010 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 01011 uint32_t RESERVED7[8U]; 01012 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 01013 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 01014 } TPI_Type; 01015 01016 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01017 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 01018 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 01019 01020 /* TPI Selected Pin Protocol Register Definitions */ 01021 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 01022 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 01023 01024 /* TPI Formatter and Flush Status Register Definitions */ 01025 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 01026 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01027 01028 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 01029 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01030 01031 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 01032 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01033 01034 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 01035 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 01036 01037 /* TPI Formatter and Flush Control Register Definitions */ 01038 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 01039 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01040 01041 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 01042 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 01043 01044 /* TPI TRIGGER Register Definitions */ 01045 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 01046 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 01047 01048 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 01049 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 01050 #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 01051 01052 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 01053 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 01054 01055 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 01056 #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 01057 01058 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 01059 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 01060 01061 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 01062 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 01063 01064 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 01065 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 01066 01067 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 01068 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 01069 01070 /* TPI ITATBCTR2 Register Definitions */ 01071 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ 01072 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ 01073 01074 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ 01075 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ 01076 01077 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 01078 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 01079 #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 01080 01081 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 01082 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 01083 01084 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 01085 #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 01086 01087 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 01088 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 01089 01090 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 01091 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 01092 01093 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 01094 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 01095 01096 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 01097 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 01098 01099 /* TPI ITATBCTR0 Register Definitions */ 01100 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ 01101 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ 01102 01103 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ 01104 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ 01105 01106 /* TPI Integration Mode Control Register Definitions */ 01107 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 01108 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 01109 01110 /* TPI DEVID Register Definitions */ 01111 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 01112 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01113 01114 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 01115 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01116 01117 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 01118 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01119 01120 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 01121 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 01122 01123 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 01124 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01125 01126 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 01127 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 01128 01129 /* TPI DEVTYPE Register Definitions */ 01130 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 01131 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 01132 01133 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 01134 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01135 01136 /*@}*/ /* end of group CMSIS_TPI */ 01137 01138 01139 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01140 /** 01141 \ingroup CMSIS_core_register 01142 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01143 \brief Type definitions for the Memory Protection Unit (MPU) 01144 @{ 01145 */ 01146 01147 /** 01148 \brief Structure type to access the Memory Protection Unit (MPU). 01149 */ 01150 typedef struct 01151 { 01152 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01153 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01154 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 01155 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01156 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 01157 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 01158 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 01159 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 01160 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 01161 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 01162 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 01163 } MPU_Type; 01164 01165 #define MPU_TYPE_RALIASES 4U 01166 01167 /* MPU Type Register Definitions */ 01168 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 01169 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01170 01171 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 01172 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01173 01174 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 01175 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 01176 01177 /* MPU Control Register Definitions */ 01178 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 01179 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01180 01181 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 01182 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01183 01184 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 01185 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 01186 01187 /* MPU Region Number Register Definitions */ 01188 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 01189 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 01190 01191 /* MPU Region Base Address Register Definitions */ 01192 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 01193 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 01194 01195 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 01196 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 01197 01198 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 01199 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 01200 01201 /* MPU Region Attribute and Size Register Definitions */ 01202 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 01203 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 01204 01205 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 01206 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 01207 01208 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 01209 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 01210 01211 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 01212 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 01213 01214 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 01215 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 01216 01217 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 01218 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 01219 01220 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 01221 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 01222 01223 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 01224 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 01225 01226 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 01227 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 01228 01229 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 01230 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 01231 01232 /*@} end of group CMSIS_MPU */ 01233 #endif 01234 01235 01236 /** 01237 \ingroup CMSIS_core_register 01238 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01239 \brief Type definitions for the Core Debug Registers 01240 @{ 01241 */ 01242 01243 /** 01244 \brief Structure type to access the Core Debug Register (CoreDebug). 01245 */ 01246 typedef struct 01247 { 01248 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01249 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01250 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01251 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01252 } CoreDebug_Type; 01253 01254 /* Debug Halting Control and Status Register Definitions */ 01255 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01256 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01257 01258 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01259 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01260 01261 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01262 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01263 01264 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01265 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01266 01267 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01268 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01269 01270 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01271 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01272 01273 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01274 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01275 01276 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01277 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01278 01279 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01280 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01281 01282 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01283 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01284 01285 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01286 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01287 01288 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01289 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01290 01291 /* Debug Core Register Selector Register Definitions */ 01292 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01293 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01294 01295 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01296 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01297 01298 /* Debug Exception and Monitor Control Register Definitions */ 01299 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 01300 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01301 01302 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 01303 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01304 01305 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 01306 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01307 01308 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 01309 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01310 01311 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 01312 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01313 01314 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01315 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01316 01317 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 01318 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01319 01320 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01321 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01322 01323 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 01324 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01325 01326 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01327 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01328 01329 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01330 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01331 01332 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 01333 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01334 01335 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01336 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01337 01338 /*@} end of group CMSIS_CoreDebug */ 01339 01340 01341 /** 01342 \ingroup CMSIS_core_register 01343 \defgroup CMSIS_core_bitfield Core register bit field macros 01344 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01345 @{ 01346 */ 01347 01348 /** 01349 \brief Mask and shift a bit field value for use in a register bit range. 01350 \param[in] field Name of the register bit field. 01351 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01352 \return Masked and shifted value. 01353 */ 01354 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01355 01356 /** 01357 \brief Mask and shift a register value to extract a bit filed value. 01358 \param[in] field Name of the register bit field. 01359 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01360 \return Masked and shifted bit field value. 01361 */ 01362 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01363 01364 /*@} end of group CMSIS_core_bitfield */ 01365 01366 01367 /** 01368 \ingroup CMSIS_core_register 01369 \defgroup CMSIS_core_base Core Definitions 01370 \brief Definitions for base addresses, unions, and structures. 01371 @{ 01372 */ 01373 01374 /* Memory mapping of Core Hardware */ 01375 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01376 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01377 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01378 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01379 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01380 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01381 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01382 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01383 01384 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01385 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01386 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01387 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01388 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01389 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01390 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01391 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 01392 01393 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01394 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01395 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01396 #endif 01397 01398 /*@} */ 01399 01400 01401 01402 /******************************************************************************* 01403 * Hardware Abstraction Layer 01404 Core Function Interface contains: 01405 - Core NVIC Functions 01406 - Core SysTick Functions 01407 - Core Debug Functions 01408 - Core Register Access Functions 01409 ******************************************************************************/ 01410 /** 01411 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01412 */ 01413 01414 01415 01416 /* ########################## NVIC functions #################################### */ 01417 /** 01418 \ingroup CMSIS_Core_FunctionInterface 01419 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01420 \brief Functions that manage interrupts and exceptions via the NVIC. 01421 @{ 01422 */ 01423 01424 #ifdef CMSIS_NVIC_VIRTUAL 01425 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 01426 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 01427 #endif 01428 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 01429 #else 01430 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 01431 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 01432 #define NVIC_EnableIRQ __NVIC_EnableIRQ 01433 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 01434 #define NVIC_DisableIRQ __NVIC_DisableIRQ 01435 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 01436 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 01437 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 01438 #define NVIC_GetActive __NVIC_GetActive 01439 #define NVIC_SetPriority __NVIC_SetPriority 01440 #define NVIC_GetPriority __NVIC_GetPriority 01441 #define NVIC_SystemReset __NVIC_SystemReset 01442 #endif /* CMSIS_NVIC_VIRTUAL */ 01443 01444 #ifdef CMSIS_VECTAB_VIRTUAL 01445 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01446 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 01447 #endif 01448 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01449 #else 01450 #define NVIC_SetVector __NVIC_SetVector 01451 #define NVIC_GetVector __NVIC_GetVector 01452 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 01453 01454 #define NVIC_USER_IRQ_OFFSET 16 01455 01456 01457 /* The following EXC_RETURN values are saved the LR on exception entry */ 01458 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 01459 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 01460 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 01461 01462 01463 /** 01464 \brief Set Priority Grouping 01465 \details Sets the priority grouping field using the required unlock sequence. 01466 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 01467 Only values from 0..7 are used. 01468 In case of a conflict between priority grouping and available 01469 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01470 \param [in] PriorityGroup Priority grouping field. 01471 */ 01472 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01473 { 01474 uint32_t reg_value; 01475 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01476 01477 reg_value = SCB->AIRCR; /* read old register configuration */ 01478 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 01479 reg_value = (reg_value | 01480 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01481 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 01482 SCB->AIRCR = reg_value; 01483 } 01484 01485 01486 /** 01487 \brief Get Priority Grouping 01488 \details Reads the priority grouping field from the NVIC Interrupt Controller. 01489 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 01490 */ 01491 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 01492 { 01493 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 01494 } 01495 01496 01497 /** 01498 \brief Enable Interrupt 01499 \details Enables a device specific interrupt in the NVIC interrupt controller. 01500 \param [in] IRQn Device specific interrupt number. 01501 \note IRQn must not be negative. 01502 */ 01503 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 01504 { 01505 if ((int32_t)(IRQn) >= 0) 01506 { 01507 __COMPILER_BARRIER(); 01508 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01509 __COMPILER_BARRIER(); 01510 } 01511 } 01512 01513 01514 /** 01515 \brief Get Interrupt Enable status 01516 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 01517 \param [in] IRQn Device specific interrupt number. 01518 \return 0 Interrupt is not enabled. 01519 \return 1 Interrupt is enabled. 01520 \note IRQn must not be negative. 01521 */ 01522 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 01523 { 01524 if ((int32_t)(IRQn) >= 0) 01525 { 01526 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01527 } 01528 else 01529 { 01530 return(0U); 01531 } 01532 } 01533 01534 01535 /** 01536 \brief Disable Interrupt 01537 \details Disables a device specific interrupt in the NVIC interrupt controller. 01538 \param [in] IRQn Device specific interrupt number. 01539 \note IRQn must not be negative. 01540 */ 01541 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 01542 { 01543 if ((int32_t)(IRQn) >= 0) 01544 { 01545 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01546 __DSB(); 01547 __ISB(); 01548 } 01549 } 01550 01551 01552 /** 01553 \brief Get Pending Interrupt 01554 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 01555 \param [in] IRQn Device specific interrupt number. 01556 \return 0 Interrupt status is not pending. 01557 \return 1 Interrupt status is pending. 01558 \note IRQn must not be negative. 01559 */ 01560 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 01561 { 01562 if ((int32_t)(IRQn) >= 0) 01563 { 01564 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01565 } 01566 else 01567 { 01568 return(0U); 01569 } 01570 } 01571 01572 01573 /** 01574 \brief Set Pending Interrupt 01575 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 01576 \param [in] IRQn Device specific interrupt number. 01577 \note IRQn must not be negative. 01578 */ 01579 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 01580 { 01581 if ((int32_t)(IRQn) >= 0) 01582 { 01583 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01584 } 01585 } 01586 01587 01588 /** 01589 \brief Clear Pending Interrupt 01590 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 01591 \param [in] IRQn Device specific interrupt number. 01592 \note IRQn must not be negative. 01593 */ 01594 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01595 { 01596 if ((int32_t)(IRQn) >= 0) 01597 { 01598 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01599 } 01600 } 01601 01602 01603 /** 01604 \brief Get Active Interrupt 01605 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 01606 \param [in] IRQn Device specific interrupt number. 01607 \return 0 Interrupt status is not active. 01608 \return 1 Interrupt status is active. 01609 \note IRQn must not be negative. 01610 */ 01611 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 01612 { 01613 if ((int32_t)(IRQn) >= 0) 01614 { 01615 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01616 } 01617 else 01618 { 01619 return(0U); 01620 } 01621 } 01622 01623 01624 /** 01625 \brief Set Interrupt Priority 01626 \details Sets the priority of a device specific interrupt or a processor exception. 01627 The interrupt number can be positive to specify a device specific interrupt, 01628 or negative to specify a processor exception. 01629 \param [in] IRQn Interrupt number. 01630 \param [in] priority Priority to set. 01631 \note The priority cannot be set for every processor exception. 01632 */ 01633 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01634 { 01635 if ((int32_t)(IRQn) >= 0) 01636 { 01637 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01638 } 01639 else 01640 { 01641 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01642 } 01643 } 01644 01645 01646 /** 01647 \brief Get Interrupt Priority 01648 \details Reads the priority of a device specific interrupt or a processor exception. 01649 The interrupt number can be positive to specify a device specific interrupt, 01650 or negative to specify a processor exception. 01651 \param [in] IRQn Interrupt number. 01652 \return Interrupt Priority. 01653 Value is aligned automatically to the implemented priority bits of the microcontroller. 01654 */ 01655 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 01656 { 01657 01658 if ((int32_t)(IRQn) >= 0) 01659 { 01660 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 01661 } 01662 else 01663 { 01664 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 01665 } 01666 } 01667 01668 01669 /** 01670 \brief Encode Priority 01671 \details Encodes the priority for an interrupt with the given priority group, 01672 preemptive priority value, and subpriority value. 01673 In case of a conflict between priority grouping and available 01674 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01675 \param [in] PriorityGroup Used priority group. 01676 \param [in] PreemptPriority Preemptive priority value (starting from 0). 01677 \param [in] SubPriority Subpriority value (starting from 0). 01678 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 01679 */ 01680 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01681 { 01682 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01683 uint32_t PreemptPriorityBits; 01684 uint32_t SubPriorityBits; 01685 01686 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01687 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01688 01689 return ( 01690 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 01691 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 01692 ); 01693 } 01694 01695 01696 /** 01697 \brief Decode Priority 01698 \details Decodes an interrupt priority value with a given priority group to 01699 preemptive priority value and subpriority value. 01700 In case of a conflict between priority grouping and available 01701 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 01702 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 01703 \param [in] PriorityGroup Used priority group. 01704 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 01705 \param [out] pSubPriority Subpriority value (starting from 0). 01706 */ 01707 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 01708 { 01709 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01710 uint32_t PreemptPriorityBits; 01711 uint32_t SubPriorityBits; 01712 01713 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01714 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01715 01716 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 01717 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 01718 } 01719 01720 01721 /** 01722 \brief Set Interrupt Vector 01723 \details Sets an interrupt vector in SRAM based interrupt vector table. 01724 The interrupt number can be positive to specify a device specific interrupt, 01725 or negative to specify a processor exception. 01726 VTOR must been relocated to SRAM before. 01727 \param [in] IRQn Interrupt number 01728 \param [in] vector Address of interrupt handler function 01729 */ 01730 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 01731 { 01732 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01733 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 01734 /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ 01735 } 01736 01737 01738 /** 01739 \brief Get Interrupt Vector 01740 \details Reads an interrupt vector from interrupt vector table. 01741 The interrupt number can be positive to specify a device specific interrupt, 01742 or negative to specify a processor exception. 01743 \param [in] IRQn Interrupt number. 01744 \return Address of interrupt handler function 01745 */ 01746 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 01747 { 01748 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01749 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 01750 } 01751 01752 01753 /** 01754 \brief System Reset 01755 \details Initiates a system reset request to reset the MCU. 01756 */ 01757 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 01758 { 01759 __DSB(); /* Ensure all outstanding memory accesses included 01760 buffered write are completed before reset */ 01761 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01762 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 01763 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 01764 __DSB(); /* Ensure completion of memory access */ 01765 01766 for(;;) /* wait until reset */ 01767 { 01768 __NOP(); 01769 } 01770 } 01771 01772 /*@} end of CMSIS_Core_NVICFunctions */ 01773 01774 01775 /* ########################## MPU functions #################################### */ 01776 01777 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01778 01779 #include "mpu_armv7.h" 01780 01781 #endif 01782 01783 01784 /* ########################## FPU functions #################################### */ 01785 /** 01786 \ingroup CMSIS_Core_FunctionInterface 01787 \defgroup CMSIS_Core_FpuFunctions FPU Functions 01788 \brief Function that provides FPU type. 01789 @{ 01790 */ 01791 01792 /** 01793 \brief get FPU type 01794 \details returns the FPU type 01795 \returns 01796 - \b 0: No FPU 01797 - \b 1: Single precision FPU 01798 - \b 2: Double + Single precision FPU 01799 */ 01800 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 01801 { 01802 return 0U; /* No FPU */ 01803 } 01804 01805 01806 /*@} end of CMSIS_Core_FpuFunctions */ 01807 01808 01809 01810 /* ################################## SysTick function ############################################ */ 01811 /** 01812 \ingroup CMSIS_Core_FunctionInterface 01813 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 01814 \brief Functions that configure the System. 01815 @{ 01816 */ 01817 01818 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 01819 01820 /** 01821 \brief System Tick Configuration 01822 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 01823 Counter is in free running mode to generate periodic interrupts. 01824 \param [in] ticks Number of ticks between two interrupts. 01825 \return 0 Function succeeded. 01826 \return 1 Function failed. 01827 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01828 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 01829 must contain a vendor-specific implementation of this function. 01830 */ 01831 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01832 { 01833 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 01834 { 01835 return (1UL); /* Reload value impossible */ 01836 } 01837 01838 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01839 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01840 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 01841 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01842 SysTick_CTRL_TICKINT_Msk | 01843 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01844 return (0UL); /* Function successful */ 01845 } 01846 01847 #endif 01848 01849 /*@} end of CMSIS_Core_SysTickFunctions */ 01850 01851 01852 01853 /* ##################################### Debug In/Output function ########################################### */ 01854 /** 01855 \ingroup CMSIS_Core_FunctionInterface 01856 \defgroup CMSIS_core_DebugFunctions ITM Functions 01857 \brief Functions that access the ITM debug interface. 01858 @{ 01859 */ 01860 01861 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 01862 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 01863 01864 01865 /** 01866 \brief ITM Send Character 01867 \details Transmits a character via the ITM channel 0, and 01868 \li Just returns when no debugger is connected that has booked the output. 01869 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 01870 \param [in] ch Character to transmit. 01871 \returns Character to transmit. 01872 */ 01873 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 01874 { 01875 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 01876 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 01877 { 01878 while (ITM->PORT[0U].u32 == 0UL) 01879 { 01880 __NOP(); 01881 } 01882 ITM->PORT[0U].u8 = (uint8_t)ch; 01883 } 01884 return (ch); 01885 } 01886 01887 01888 /** 01889 \brief ITM Receive Character 01890 \details Inputs a character via the external variable \ref ITM_RxBuffer. 01891 \return Received character. 01892 \return -1 No character pending. 01893 */ 01894 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 01895 { 01896 int32_t ch = -1; /* no character available */ 01897 01898 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 01899 { 01900 ch = ITM_RxBuffer; 01901 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 01902 } 01903 01904 return (ch); 01905 } 01906 01907 01908 /** 01909 \brief ITM Check Character 01910 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 01911 \return 0 No character available. 01912 \return 1 Character available. 01913 */ 01914 __STATIC_INLINE int32_t ITM_CheckChar (void) 01915 { 01916 01917 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 01918 { 01919 return (0); /* no character available */ 01920 } 01921 else 01922 { 01923 return (1); /* character available */ 01924 } 01925 } 01926 01927 /*@} end of CMSIS_core_DebugFunctions */ 01928 01929 01930 01931 01932 #ifdef __cplusplus 01933 } 01934 #endif 01935 01936 #endif /* __CORE_CM3_H_DEPENDANT */ 01937 01938 #endif /* __CMSIS_GENERIC */
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