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core_cm33.h
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00001 /**************************************************************************//** 00002 * @file core_cm33.h 00003 * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File 00004 * @version V5.1.0 00005 * @date 12. November 2018 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__clang__) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_CM33_H_GENERIC 00032 #define __CORE_CM33_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_M33 00060 @{ 00061 */ 00062 00063 #include "cmsis_version.h" 00064 00065 /* CMSIS CM33 definitions */ 00066 #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 00067 #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 00068 #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ 00069 __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 00070 00071 #define __CORTEX_M (33U) /*!< Cortex-M Core */ 00072 00073 /** __FPU_USED indicates whether an FPU is used or not. 00074 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 00075 */ 00076 #if defined ( __CC_ARM ) 00077 #if defined (__TARGET_FPU_VFP) 00078 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00079 #define __FPU_USED 1U 00080 #else 00081 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00082 #define __FPU_USED 0U 00083 #endif 00084 #else 00085 #define __FPU_USED 0U 00086 #endif 00087 00088 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) 00089 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) 00090 #define __DSP_USED 1U 00091 #else 00092 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 00093 #define __DSP_USED 0U 00094 #endif 00095 #else 00096 #define __DSP_USED 0U 00097 #endif 00098 00099 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00100 #if defined (__ARM_FP) 00101 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00102 #define __FPU_USED 1U 00103 #else 00104 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00105 #define __FPU_USED 0U 00106 #endif 00107 #else 00108 #define __FPU_USED 0U 00109 #endif 00110 00111 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) 00112 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) 00113 #define __DSP_USED 1U 00114 #else 00115 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 00116 #define __DSP_USED 0U 00117 #endif 00118 #else 00119 #define __DSP_USED 0U 00120 #endif 00121 00122 #elif defined ( __GNUC__ ) 00123 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00125 #define __FPU_USED 1U 00126 #else 00127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00128 #define __FPU_USED 0U 00129 #endif 00130 #else 00131 #define __FPU_USED 0U 00132 #endif 00133 00134 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) 00135 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) 00136 #define __DSP_USED 1U 00137 #else 00138 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 00139 #define __DSP_USED 0U 00140 #endif 00141 #else 00142 #define __DSP_USED 0U 00143 #endif 00144 00145 #elif defined ( __ICCARM__ ) 00146 #if defined (__ARMVFP__) 00147 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00148 #define __FPU_USED 1U 00149 #else 00150 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00151 #define __FPU_USED 0U 00152 #endif 00153 #else 00154 #define __FPU_USED 0U 00155 #endif 00156 00157 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) 00158 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) 00159 #define __DSP_USED 1U 00160 #else 00161 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 00162 #define __DSP_USED 0U 00163 #endif 00164 #else 00165 #define __DSP_USED 0U 00166 #endif 00167 00168 #elif defined ( __TI_ARM__ ) 00169 #if defined (__TI_VFP_SUPPORT__) 00170 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00171 #define __FPU_USED 1U 00172 #else 00173 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00174 #define __FPU_USED 0U 00175 #endif 00176 #else 00177 #define __FPU_USED 0U 00178 #endif 00179 00180 #elif defined ( __TASKING__ ) 00181 #if defined (__FPU_VFP__) 00182 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00183 #define __FPU_USED 1U 00184 #else 00185 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00186 #define __FPU_USED 0U 00187 #endif 00188 #else 00189 #define __FPU_USED 0U 00190 #endif 00191 00192 #elif defined ( __CSMC__ ) 00193 #if ( __CSMC__ & 0x400U) 00194 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00195 #define __FPU_USED 1U 00196 #else 00197 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00198 #define __FPU_USED 0U 00199 #endif 00200 #else 00201 #define __FPU_USED 0U 00202 #endif 00203 00204 #endif 00205 00206 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00207 00208 00209 #ifdef __cplusplus 00210 } 00211 #endif 00212 00213 #endif /* __CORE_CM33_H_GENERIC */ 00214 00215 #ifndef __CMSIS_GENERIC 00216 00217 #ifndef __CORE_CM33_H_DEPENDANT 00218 #define __CORE_CM33_H_DEPENDANT 00219 00220 #ifdef __cplusplus 00221 extern "C" { 00222 #endif 00223 00224 /* check device defines and use defaults */ 00225 #if defined __CHECK_DEVICE_DEFINES 00226 #ifndef __CM33_REV 00227 #define __CM33_REV 0x0000U 00228 #warning "__CM33_REV not defined in device header file; using default!" 00229 #endif 00230 00231 #ifndef __FPU_PRESENT 00232 #define __FPU_PRESENT 0U 00233 #warning "__FPU_PRESENT not defined in device header file; using default!" 00234 #endif 00235 00236 #ifndef __MPU_PRESENT 00237 #define __MPU_PRESENT 0U 00238 #warning "__MPU_PRESENT not defined in device header file; using default!" 00239 #endif 00240 00241 #ifndef __SAUREGION_PRESENT 00242 #define __SAUREGION_PRESENT 0U 00243 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 00244 #endif 00245 00246 #ifndef __DSP_PRESENT 00247 #define __DSP_PRESENT 0U 00248 #warning "__DSP_PRESENT not defined in device header file; using default!" 00249 #endif 00250 00251 #ifndef __NVIC_PRIO_BITS 00252 #define __NVIC_PRIO_BITS 3U 00253 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00254 #endif 00255 00256 #ifndef __Vendor_SysTickConfig 00257 #define __Vendor_SysTickConfig 0U 00258 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00259 #endif 00260 #endif 00261 00262 /* IO definitions (access restrictions to peripheral registers) */ 00263 /** 00264 \defgroup CMSIS_glob_defs CMSIS Global Defines 00265 00266 <strong>IO Type Qualifiers</strong> are used 00267 \li to specify the access to peripheral variables. 00268 \li for automatic generation of peripheral register debug information. 00269 */ 00270 #ifdef __cplusplus 00271 #define __I volatile /*!< Defines 'read only' permissions */ 00272 #else 00273 #define __I volatile const /*!< Defines 'read only' permissions */ 00274 #endif 00275 #define __O volatile /*!< Defines 'write only' permissions */ 00276 #define __IO volatile /*!< Defines 'read / write' permissions */ 00277 00278 /* following defines should be used for structure members */ 00279 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00280 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00281 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00282 00283 /*@} end of group Cortex_M33 */ 00284 00285 00286 00287 /******************************************************************************* 00288 * Register Abstraction 00289 Core Register contain: 00290 - Core Register 00291 - Core NVIC Register 00292 - Core SCB Register 00293 - Core SysTick Register 00294 - Core Debug Register 00295 - Core MPU Register 00296 - Core SAU Register 00297 - Core FPU Register 00298 ******************************************************************************/ 00299 /** 00300 \defgroup CMSIS_core_register Defines and Type Definitions 00301 \brief Type definitions and defines for Cortex-M processor based devices. 00302 */ 00303 00304 /** 00305 \ingroup CMSIS_core_register 00306 \defgroup CMSIS_CORE Status and Control Registers 00307 \brief Core Register type definitions. 00308 @{ 00309 */ 00310 00311 /** 00312 \brief Union type to access the Application Program Status Register (APSR). 00313 */ 00314 typedef union 00315 { 00316 struct 00317 { 00318 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00319 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00320 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00321 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00322 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00323 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00324 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00325 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00326 } b; /*!< Structure used for bit access */ 00327 uint32_t w; /*!< Type used for word access */ 00328 } APSR_Type; 00329 00330 /* APSR Register Definitions */ 00331 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00332 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00333 00334 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00335 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00336 00337 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00338 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00339 00340 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00341 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00342 00343 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 00344 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 00345 00346 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 00347 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 00348 00349 00350 /** 00351 \brief Union type to access the Interrupt Program Status Register (IPSR). 00352 */ 00353 typedef union 00354 { 00355 struct 00356 { 00357 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00358 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00359 } b; /*!< Structure used for bit access */ 00360 uint32_t w; /*!< Type used for word access */ 00361 } IPSR_Type; 00362 00363 /* IPSR Register Definitions */ 00364 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00365 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00366 00367 00368 /** 00369 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00370 */ 00371 typedef union 00372 { 00373 struct 00374 { 00375 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00376 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00377 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00378 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00379 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00380 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00381 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00382 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00383 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00384 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00385 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00386 } b; /*!< Structure used for bit access */ 00387 uint32_t w; /*!< Type used for word access */ 00388 } xPSR_Type; 00389 00390 /* xPSR Register Definitions */ 00391 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00392 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00393 00394 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00395 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00396 00397 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00398 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00399 00400 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00401 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00402 00403 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 00404 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 00405 00406 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ 00407 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ 00408 00409 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00410 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00411 00412 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 00413 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 00414 00415 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00416 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00417 00418 00419 /** 00420 \brief Union type to access the Control Registers (CONTROL). 00421 */ 00422 typedef union 00423 { 00424 struct 00425 { 00426 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00427 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ 00428 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ 00429 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ 00430 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ 00431 } b; /*!< Structure used for bit access */ 00432 uint32_t w; /*!< Type used for word access */ 00433 } CONTROL_Type; 00434 00435 /* CONTROL Register Definitions */ 00436 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ 00437 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ 00438 00439 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 00440 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 00441 00442 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00443 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00444 00445 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00446 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00447 00448 /*@} end of group CMSIS_CORE */ 00449 00450 00451 /** 00452 \ingroup CMSIS_core_register 00453 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00454 \brief Type definitions for the NVIC Registers 00455 @{ 00456 */ 00457 00458 /** 00459 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00460 */ 00461 typedef struct 00462 { 00463 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00464 uint32_t RESERVED0[16U]; 00465 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00466 uint32_t RSERVED1[16U]; 00467 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00468 uint32_t RESERVED2[16U]; 00469 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00470 uint32_t RESERVED3[16U]; 00471 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00472 uint32_t RESERVED4[16U]; 00473 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 00474 uint32_t RESERVED5[16U]; 00475 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00476 uint32_t RESERVED6[580U]; 00477 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00478 } NVIC_Type; 00479 00480 /* Software Triggered Interrupt Register Definitions */ 00481 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 00482 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 00483 00484 /*@} end of group CMSIS_NVIC */ 00485 00486 00487 /** 00488 \ingroup CMSIS_core_register 00489 \defgroup CMSIS_SCB System Control Block (SCB) 00490 \brief Type definitions for the System Control Block Registers 00491 @{ 00492 */ 00493 00494 /** 00495 \brief Structure type to access the System Control Block (SCB). 00496 */ 00497 typedef struct 00498 { 00499 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00500 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00501 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00502 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00503 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00504 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00505 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00506 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00507 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00508 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00509 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00510 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00511 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00512 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00513 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00514 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00515 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00516 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00517 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00518 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 00519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 00520 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 00521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 00522 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00523 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ 00524 uint32_t RESERVED3[92U]; 00525 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 00526 uint32_t RESERVED4[15U]; 00527 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ 00528 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ 00529 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ 00530 uint32_t RESERVED5[1U]; 00531 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 00532 uint32_t RESERVED6[1U]; 00533 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 00534 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 00535 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 00536 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 00537 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 00538 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 00539 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ 00540 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ 00541 } SCB_Type; 00542 00543 /* SCB CPUID Register Definitions */ 00544 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00545 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00546 00547 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00548 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00549 00550 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00551 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00552 00553 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00554 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00555 00556 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00557 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00558 00559 /* SCB Interrupt Control State Register Definitions */ 00560 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 00561 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 00562 00563 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ 00564 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ 00565 00566 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 00567 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 00568 00569 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00570 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00571 00572 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00573 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00574 00575 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00576 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00577 00578 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00579 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00580 00581 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 00582 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 00583 00584 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00585 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00586 00587 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00588 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00589 00590 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00591 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00592 00593 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00594 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00595 00596 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00597 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00598 00599 /* SCB Vector Table Offset Register Definitions */ 00600 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00601 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00602 00603 /* SCB Application Interrupt and Reset Control Register Definitions */ 00604 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00605 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00606 00607 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00608 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00609 00610 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00611 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00612 00613 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 00614 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 00615 00616 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 00617 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 00618 00619 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 00620 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00621 00622 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 00623 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 00624 00625 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00626 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00627 00628 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00629 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00630 00631 /* SCB System Control Register Definitions */ 00632 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00633 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00634 00635 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 00636 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 00637 00638 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00639 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00640 00641 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00642 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00643 00644 /* SCB Configuration Control Register Definitions */ 00645 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 00646 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 00647 00648 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 00649 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 00650 00651 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 00652 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 00653 00654 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 00655 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 00656 00657 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00658 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00659 00660 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00661 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00662 00663 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00664 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00665 00666 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00667 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00668 00669 /* SCB System Handler Control and State Register Definitions */ 00670 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 00671 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 00672 00673 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ 00674 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ 00675 00676 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ 00677 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ 00678 00679 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 00680 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00681 00682 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 00683 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00684 00685 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 00686 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00687 00688 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00689 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00690 00691 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00692 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00693 00694 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00695 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00696 00697 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 00698 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00699 00700 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00701 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00702 00703 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00704 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00705 00706 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 00707 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00708 00709 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00710 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00711 00712 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 00713 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 00714 00715 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ 00716 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ 00717 00718 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 00719 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00720 00721 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 00722 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 00723 00724 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 00725 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00726 00727 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 00728 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00729 00730 /* SCB Configurable Fault Status Register Definitions */ 00731 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 00732 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00733 00734 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 00735 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00736 00737 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00738 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00739 00740 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 00741 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 00742 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 00743 00744 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ 00745 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ 00746 00747 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 00748 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 00749 00750 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 00751 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 00752 00753 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 00754 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 00755 00756 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 00757 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 00758 00759 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 00760 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 00761 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 00762 00763 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ 00764 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ 00765 00766 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 00767 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 00768 00769 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 00770 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 00771 00772 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 00773 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 00774 00775 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 00776 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 00777 00778 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 00779 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 00780 00781 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 00782 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 00783 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 00784 00785 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 00786 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 00787 00788 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ 00789 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ 00790 00791 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 00792 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 00793 00794 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 00795 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 00796 00797 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 00798 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 00799 00800 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 00801 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 00802 00803 /* SCB Hard Fault Status Register Definitions */ 00804 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 00805 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00806 00807 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 00808 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00809 00810 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 00811 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00812 00813 /* SCB Debug Fault Status Register Definitions */ 00814 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 00815 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00816 00817 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 00818 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00819 00820 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 00821 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00822 00823 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 00824 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00825 00826 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 00827 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 00828 00829 /* SCB Non-Secure Access Control Register Definitions */ 00830 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ 00831 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ 00832 00833 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ 00834 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ 00835 00836 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ 00837 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ 00838 00839 /* SCB Cache Level ID Register Definitions */ 00840 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ 00841 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ 00842 00843 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ 00844 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ 00845 00846 /* SCB Cache Type Register Definitions */ 00847 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ 00848 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ 00849 00850 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ 00851 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ 00852 00853 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ 00854 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ 00855 00856 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ 00857 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ 00858 00859 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ 00860 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ 00861 00862 /* SCB Cache Size ID Register Definitions */ 00863 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 00864 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 00865 00866 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 00867 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 00868 00869 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 00870 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 00871 00872 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 00873 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 00874 00875 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ 00876 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ 00877 00878 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ 00879 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ 00880 00881 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ 00882 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ 00883 00884 /* SCB Cache Size Selection Register Definitions */ 00885 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ 00886 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ 00887 00888 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ 00889 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ 00890 00891 /* SCB Software Triggered Interrupt Register Definitions */ 00892 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ 00893 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ 00894 00895 /* SCB D-Cache Invalidate by Set-way Register Definitions */ 00896 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ 00897 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ 00898 00899 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ 00900 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ 00901 00902 /* SCB D-Cache Clean by Set-way Register Definitions */ 00903 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ 00904 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ 00905 00906 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ 00907 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ 00908 00909 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ 00910 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ 00911 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ 00912 00913 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ 00914 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ 00915 00916 /*@} end of group CMSIS_SCB */ 00917 00918 00919 /** 00920 \ingroup CMSIS_core_register 00921 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00922 \brief Type definitions for the System Control and ID Register not in the SCB 00923 @{ 00924 */ 00925 00926 /** 00927 \brief Structure type to access the System Control and ID Register not in the SCB. 00928 */ 00929 typedef struct 00930 { 00931 uint32_t RESERVED0[1U]; 00932 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00933 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00934 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ 00935 } SCnSCB_Type; 00936 00937 /* Interrupt Controller Type Register Definitions */ 00938 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 00939 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 00940 00941 /*@} end of group CMSIS_SCnotSCB */ 00942 00943 00944 /** 00945 \ingroup CMSIS_core_register 00946 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00947 \brief Type definitions for the System Timer Registers. 00948 @{ 00949 */ 00950 00951 /** 00952 \brief Structure type to access the System Timer (SysTick). 00953 */ 00954 typedef struct 00955 { 00956 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00957 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00958 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00959 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00960 } SysTick_Type; 00961 00962 /* SysTick Control / Status Register Definitions */ 00963 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00964 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00965 00966 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00967 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00968 00969 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00970 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00971 00972 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00973 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00974 00975 /* SysTick Reload Register Definitions */ 00976 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00977 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00978 00979 /* SysTick Current Register Definitions */ 00980 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00981 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00982 00983 /* SysTick Calibration Register Definitions */ 00984 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00985 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00986 00987 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00988 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00989 00990 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00991 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00992 00993 /*@} end of group CMSIS_SysTick */ 00994 00995 00996 /** 00997 \ingroup CMSIS_core_register 00998 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 00999 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 01000 @{ 01001 */ 01002 01003 /** 01004 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 01005 */ 01006 typedef struct 01007 { 01008 __OM union 01009 { 01010 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 01011 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 01012 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 01013 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 01014 uint32_t RESERVED0[864U]; 01015 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 01016 uint32_t RESERVED1[15U]; 01017 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 01018 uint32_t RESERVED2[15U]; 01019 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 01020 uint32_t RESERVED3[32U]; 01021 uint32_t RESERVED4[43U]; 01022 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 01023 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 01024 uint32_t RESERVED5[1U]; 01025 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ 01026 uint32_t RESERVED6[4U]; 01027 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 01028 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 01029 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 01030 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 01031 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 01032 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 01033 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 01034 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 01035 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 01036 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 01037 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 01038 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 01039 } ITM_Type; 01040 01041 /* ITM Stimulus Port Register Definitions */ 01042 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ 01043 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ 01044 01045 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ 01046 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ 01047 01048 /* ITM Trace Privilege Register Definitions */ 01049 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 01050 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 01051 01052 /* ITM Trace Control Register Definitions */ 01053 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 01054 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 01055 01056 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ 01057 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ 01058 01059 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 01060 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 01061 01062 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ 01063 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ 01064 01065 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ 01066 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ 01067 01068 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 01069 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 01070 01071 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 01072 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 01073 01074 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 01075 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 01076 01077 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 01078 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 01079 01080 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 01081 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 01082 01083 /* ITM Lock Status Register Definitions */ 01084 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 01085 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 01086 01087 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 01088 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 01089 01090 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 01091 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 01092 01093 /*@}*/ /* end of group CMSIS_ITM */ 01094 01095 01096 /** 01097 \ingroup CMSIS_core_register 01098 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 01099 \brief Type definitions for the Data Watchpoint and Trace (DWT) 01100 @{ 01101 */ 01102 01103 /** 01104 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 01105 */ 01106 typedef struct 01107 { 01108 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 01109 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 01110 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 01111 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 01112 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 01113 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 01114 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 01115 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 01116 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 01117 uint32_t RESERVED1[1U]; 01118 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 01119 uint32_t RESERVED2[1U]; 01120 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 01121 uint32_t RESERVED3[1U]; 01122 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 01123 uint32_t RESERVED4[1U]; 01124 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 01125 uint32_t RESERVED5[1U]; 01126 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 01127 uint32_t RESERVED6[1U]; 01128 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 01129 uint32_t RESERVED7[1U]; 01130 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 01131 uint32_t RESERVED8[1U]; 01132 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 01133 uint32_t RESERVED9[1U]; 01134 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 01135 uint32_t RESERVED10[1U]; 01136 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 01137 uint32_t RESERVED11[1U]; 01138 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 01139 uint32_t RESERVED12[1U]; 01140 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 01141 uint32_t RESERVED13[1U]; 01142 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 01143 uint32_t RESERVED14[1U]; 01144 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 01145 uint32_t RESERVED15[1U]; 01146 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 01147 uint32_t RESERVED16[1U]; 01148 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 01149 uint32_t RESERVED17[1U]; 01150 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 01151 uint32_t RESERVED18[1U]; 01152 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 01153 uint32_t RESERVED19[1U]; 01154 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 01155 uint32_t RESERVED20[1U]; 01156 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 01157 uint32_t RESERVED21[1U]; 01158 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 01159 uint32_t RESERVED22[1U]; 01160 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 01161 uint32_t RESERVED23[1U]; 01162 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 01163 uint32_t RESERVED24[1U]; 01164 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 01165 uint32_t RESERVED25[1U]; 01166 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 01167 uint32_t RESERVED26[1U]; 01168 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 01169 uint32_t RESERVED27[1U]; 01170 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 01171 uint32_t RESERVED28[1U]; 01172 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 01173 uint32_t RESERVED29[1U]; 01174 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 01175 uint32_t RESERVED30[1U]; 01176 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 01177 uint32_t RESERVED31[1U]; 01178 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 01179 uint32_t RESERVED32[934U]; 01180 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 01181 uint32_t RESERVED33[1U]; 01182 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ 01183 } DWT_Type; 01184 01185 /* DWT Control Register Definitions */ 01186 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 01187 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 01188 01189 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 01190 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 01191 01192 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 01193 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 01194 01195 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 01196 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 01197 01198 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 01199 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 01200 01201 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ 01202 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ 01203 01204 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 01205 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 01206 01207 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 01208 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 01209 01210 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 01211 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 01212 01213 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 01214 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 01215 01216 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 01217 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 01218 01219 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 01220 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 01221 01222 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 01223 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 01224 01225 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 01226 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 01227 01228 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 01229 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 01230 01231 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 01232 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 01233 01234 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 01235 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 01236 01237 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 01238 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 01239 01240 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 01241 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 01242 01243 /* DWT CPI Count Register Definitions */ 01244 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 01245 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 01246 01247 /* DWT Exception Overhead Count Register Definitions */ 01248 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 01249 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 01250 01251 /* DWT Sleep Count Register Definitions */ 01252 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 01253 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 01254 01255 /* DWT LSU Count Register Definitions */ 01256 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 01257 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 01258 01259 /* DWT Folded-instruction Count Register Definitions */ 01260 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 01261 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 01262 01263 /* DWT Comparator Function Register Definitions */ 01264 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 01265 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 01266 01267 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 01268 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 01269 01270 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 01271 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 01272 01273 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 01274 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 01275 01276 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 01277 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 01278 01279 /*@}*/ /* end of group CMSIS_DWT */ 01280 01281 01282 /** 01283 \ingroup CMSIS_core_register 01284 \defgroup CMSIS_TPI Trace Port Interface (TPI) 01285 \brief Type definitions for the Trace Port Interface (TPI) 01286 @{ 01287 */ 01288 01289 /** 01290 \brief Structure type to access the Trace Port Interface Register (TPI). 01291 */ 01292 typedef struct 01293 { 01294 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 01295 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 01296 uint32_t RESERVED0[2U]; 01297 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 01298 uint32_t RESERVED1[55U]; 01299 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 01300 uint32_t RESERVED2[131U]; 01301 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 01302 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 01303 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ 01304 uint32_t RESERVED3[759U]; 01305 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 01306 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ 01307 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ 01308 uint32_t RESERVED4[1U]; 01309 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ 01310 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ 01311 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 01312 uint32_t RESERVED5[39U]; 01313 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 01314 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 01315 uint32_t RESERVED7[8U]; 01316 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ 01317 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ 01318 } TPI_Type; 01319 01320 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01321 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 01322 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 01323 01324 /* TPI Selected Pin Protocol Register Definitions */ 01325 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 01326 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 01327 01328 /* TPI Formatter and Flush Status Register Definitions */ 01329 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 01330 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01331 01332 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 01333 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01334 01335 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 01336 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01337 01338 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 01339 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 01340 01341 /* TPI Formatter and Flush Control Register Definitions */ 01342 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 01343 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01344 01345 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ 01346 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ 01347 01348 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 01349 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 01350 01351 /* TPI TRIGGER Register Definitions */ 01352 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 01353 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 01354 01355 /* TPI Integration Test FIFO Test Data 0 Register Definitions */ 01356 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ 01357 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ 01358 01359 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ 01360 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ 01361 01362 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ 01363 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ 01364 01365 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ 01366 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ 01367 01368 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ 01369 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ 01370 01371 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ 01372 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ 01373 01374 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ 01375 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ 01376 01377 /* TPI Integration Test ATB Control Register 2 Register Definitions */ 01378 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ 01379 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ 01380 01381 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ 01382 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ 01383 01384 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ 01385 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ 01386 01387 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ 01388 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ 01389 01390 /* TPI Integration Test FIFO Test Data 1 Register Definitions */ 01391 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ 01392 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ 01393 01394 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ 01395 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ 01396 01397 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ 01398 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ 01399 01400 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ 01401 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ 01402 01403 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ 01404 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ 01405 01406 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ 01407 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ 01408 01409 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ 01410 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ 01411 01412 /* TPI Integration Test ATB Control Register 0 Definitions */ 01413 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ 01414 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ 01415 01416 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ 01417 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ 01418 01419 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ 01420 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ 01421 01422 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ 01423 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ 01424 01425 /* TPI Integration Mode Control Register Definitions */ 01426 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 01427 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 01428 01429 /* TPI DEVID Register Definitions */ 01430 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 01431 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01432 01433 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 01434 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01435 01436 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 01437 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01438 01439 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ 01440 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ 01441 01442 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 01443 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 01444 01445 /* TPI DEVTYPE Register Definitions */ 01446 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 01447 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 01448 01449 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 01450 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01451 01452 /*@}*/ /* end of group CMSIS_TPI */ 01453 01454 01455 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01456 /** 01457 \ingroup CMSIS_core_register 01458 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01459 \brief Type definitions for the Memory Protection Unit (MPU) 01460 @{ 01461 */ 01462 01463 /** 01464 \brief Structure type to access the Memory Protection Unit (MPU). 01465 */ 01466 typedef struct 01467 { 01468 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01469 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01470 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 01471 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01472 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 01473 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ 01474 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ 01475 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ 01476 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ 01477 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ 01478 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ 01479 uint32_t RESERVED0[1]; 01480 union { 01481 __IOM uint32_t MAIR[2]; 01482 struct { 01483 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 01484 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 01485 }; 01486 }; 01487 } MPU_Type; 01488 01489 #define MPU_TYPE_RALIASES 4U 01490 01491 /* MPU Type Register Definitions */ 01492 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 01493 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01494 01495 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 01496 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01497 01498 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 01499 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 01500 01501 /* MPU Control Register Definitions */ 01502 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 01503 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01504 01505 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 01506 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01507 01508 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 01509 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 01510 01511 /* MPU Region Number Register Definitions */ 01512 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 01513 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 01514 01515 /* MPU Region Base Address Register Definitions */ 01516 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 01517 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 01518 01519 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 01520 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 01521 01522 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 01523 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 01524 01525 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 01526 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 01527 01528 /* MPU Region Limit Address Register Definitions */ 01529 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 01530 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 01531 01532 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 01533 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 01534 01535 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ 01536 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ 01537 01538 /* MPU Memory Attribute Indirection Register 0 Definitions */ 01539 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 01540 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 01541 01542 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 01543 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 01544 01545 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 01546 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 01547 01548 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 01549 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 01550 01551 /* MPU Memory Attribute Indirection Register 1 Definitions */ 01552 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 01553 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 01554 01555 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 01556 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 01557 01558 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 01559 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 01560 01561 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 01562 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 01563 01564 /*@} end of group CMSIS_MPU */ 01565 #endif 01566 01567 01568 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01569 /** 01570 \ingroup CMSIS_core_register 01571 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 01572 \brief Type definitions for the Security Attribution Unit (SAU) 01573 @{ 01574 */ 01575 01576 /** 01577 \brief Structure type to access the Security Attribution Unit (SAU). 01578 */ 01579 typedef struct 01580 { 01581 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 01582 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 01583 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 01584 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 01585 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 01586 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 01587 #else 01588 uint32_t RESERVED0[3]; 01589 #endif 01590 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ 01591 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ 01592 } SAU_Type; 01593 01594 /* SAU Control Register Definitions */ 01595 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 01596 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 01597 01598 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 01599 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 01600 01601 /* SAU Type Register Definitions */ 01602 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 01603 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 01604 01605 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 01606 /* SAU Region Number Register Definitions */ 01607 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 01608 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 01609 01610 /* SAU Region Base Address Register Definitions */ 01611 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 01612 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 01613 01614 /* SAU Region Limit Address Register Definitions */ 01615 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 01616 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 01617 01618 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 01619 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 01620 01621 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 01622 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 01623 01624 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 01625 01626 /* Secure Fault Status Register Definitions */ 01627 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ 01628 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ 01629 01630 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ 01631 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ 01632 01633 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ 01634 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ 01635 01636 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ 01637 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ 01638 01639 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ 01640 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ 01641 01642 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ 01643 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ 01644 01645 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ 01646 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ 01647 01648 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ 01649 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ 01650 01651 /*@} end of group CMSIS_SAU */ 01652 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01653 01654 01655 /** 01656 \ingroup CMSIS_core_register 01657 \defgroup CMSIS_FPU Floating Point Unit (FPU) 01658 \brief Type definitions for the Floating Point Unit (FPU) 01659 @{ 01660 */ 01661 01662 /** 01663 \brief Structure type to access the Floating Point Unit (FPU). 01664 */ 01665 typedef struct 01666 { 01667 uint32_t RESERVED0[1U]; 01668 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 01669 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 01670 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 01671 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 01672 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 01673 } FPU_Type; 01674 01675 /* Floating-Point Context Control Register Definitions */ 01676 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 01677 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 01678 01679 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 01680 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 01681 01682 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ 01683 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ 01684 01685 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ 01686 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ 01687 01688 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ 01689 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ 01690 01691 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ 01692 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ 01693 01694 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ 01695 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ 01696 01697 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ 01698 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ 01699 01700 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 01701 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 01702 01703 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ 01704 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ 01705 01706 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 01707 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 01708 01709 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 01710 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 01711 01712 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 01713 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 01714 01715 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 01716 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 01717 01718 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ 01719 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ 01720 01721 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 01722 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 01723 01724 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 01725 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 01726 01727 /* Floating-Point Context Address Register Definitions */ 01728 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 01729 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 01730 01731 /* Floating-Point Default Status Control Register Definitions */ 01732 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 01733 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 01734 01735 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 01736 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 01737 01738 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 01739 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 01740 01741 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 01742 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 01743 01744 /* Media and FP Feature Register 0 Definitions */ 01745 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ 01746 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 01747 01748 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ 01749 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 01750 01751 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ 01752 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 01753 01754 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ 01755 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 01756 01757 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ 01758 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 01759 01760 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ 01761 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 01762 01763 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ 01764 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 01765 01766 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ 01767 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 01768 01769 /* Media and FP Feature Register 1 Definitions */ 01770 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ 01771 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 01772 01773 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 01774 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 01775 01776 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 01777 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 01778 01779 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 01780 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 01781 01782 /*@} end of group CMSIS_FPU */ 01783 01784 01785 /** 01786 \ingroup CMSIS_core_register 01787 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01788 \brief Type definitions for the Core Debug Registers 01789 @{ 01790 */ 01791 01792 /** 01793 \brief Structure type to access the Core Debug Register (CoreDebug). 01794 */ 01795 typedef struct 01796 { 01797 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01798 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01799 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01800 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01801 uint32_t RESERVED4[1U]; 01802 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 01803 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 01804 } CoreDebug_Type; 01805 01806 /* Debug Halting Control and Status Register Definitions */ 01807 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01808 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01809 01810 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ 01811 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ 01812 01813 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01814 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01815 01816 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01817 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01818 01819 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01820 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01821 01822 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01823 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01824 01825 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01826 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01827 01828 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01829 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01830 01831 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01832 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01833 01834 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01835 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01836 01837 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01838 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01839 01840 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01841 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01842 01843 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01844 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01845 01846 /* Debug Core Register Selector Register Definitions */ 01847 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01848 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01849 01850 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01851 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01852 01853 /* Debug Exception and Monitor Control Register Definitions */ 01854 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 01855 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01856 01857 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 01858 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01859 01860 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 01861 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01862 01863 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 01864 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01865 01866 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 01867 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01868 01869 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01870 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01871 01872 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 01873 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01874 01875 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01876 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01877 01878 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 01879 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01880 01881 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01882 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01883 01884 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01885 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01886 01887 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 01888 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01889 01890 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01891 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01892 01893 /* Debug Authentication Control Register Definitions */ 01894 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 01895 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 01896 01897 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 01898 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 01899 01900 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ 01901 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 01902 01903 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ 01904 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 01905 01906 /* Debug Security Control and Status Register Definitions */ 01907 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ 01908 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ 01909 01910 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ 01911 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ 01912 01913 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ 01914 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ 01915 01916 /*@} end of group CMSIS_CoreDebug */ 01917 01918 01919 /** 01920 \ingroup CMSIS_core_register 01921 \defgroup CMSIS_core_bitfield Core register bit field macros 01922 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01923 @{ 01924 */ 01925 01926 /** 01927 \brief Mask and shift a bit field value for use in a register bit range. 01928 \param[in] field Name of the register bit field. 01929 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01930 \return Masked and shifted value. 01931 */ 01932 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01933 01934 /** 01935 \brief Mask and shift a register value to extract a bit filed value. 01936 \param[in] field Name of the register bit field. 01937 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01938 \return Masked and shifted bit field value. 01939 */ 01940 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01941 01942 /*@} end of group CMSIS_core_bitfield */ 01943 01944 01945 /** 01946 \ingroup CMSIS_core_register 01947 \defgroup CMSIS_core_base Core Definitions 01948 \brief Definitions for base addresses, unions, and structures. 01949 @{ 01950 */ 01951 01952 /* Memory mapping of Core Hardware */ 01953 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01954 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01955 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01956 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01957 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01958 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01959 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01960 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01961 01962 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01963 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01964 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01965 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01966 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01967 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01968 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01969 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ 01970 01971 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01972 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01973 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01974 #endif 01975 01976 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01977 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 01978 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 01979 #endif 01980 01981 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 01982 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 01983 01984 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01985 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 01986 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ 01987 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 01988 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 01989 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 01990 01991 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ 01992 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 01993 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 01994 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 01995 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ 01996 01997 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01998 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 01999 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 02000 #endif 02001 02002 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ 02003 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ 02004 02005 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02006 /*@} */ 02007 02008 02009 02010 /******************************************************************************* 02011 * Hardware Abstraction Layer 02012 Core Function Interface contains: 02013 - Core NVIC Functions 02014 - Core SysTick Functions 02015 - Core Debug Functions 02016 - Core Register Access Functions 02017 ******************************************************************************/ 02018 /** 02019 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 02020 */ 02021 02022 02023 02024 /* ########################## NVIC functions #################################### */ 02025 /** 02026 \ingroup CMSIS_Core_FunctionInterface 02027 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 02028 \brief Functions that manage interrupts and exceptions via the NVIC. 02029 @{ 02030 */ 02031 02032 #ifdef CMSIS_NVIC_VIRTUAL 02033 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 02034 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 02035 #endif 02036 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 02037 #else 02038 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 02039 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 02040 #define NVIC_EnableIRQ __NVIC_EnableIRQ 02041 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 02042 #define NVIC_DisableIRQ __NVIC_DisableIRQ 02043 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 02044 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 02045 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 02046 #define NVIC_GetActive __NVIC_GetActive 02047 #define NVIC_SetPriority __NVIC_SetPriority 02048 #define NVIC_GetPriority __NVIC_GetPriority 02049 #define NVIC_SystemReset __NVIC_SystemReset 02050 #endif /* CMSIS_NVIC_VIRTUAL */ 02051 02052 #ifdef CMSIS_VECTAB_VIRTUAL 02053 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 02054 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 02055 #endif 02056 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 02057 #else 02058 #define NVIC_SetVector __NVIC_SetVector 02059 #define NVIC_GetVector __NVIC_GetVector 02060 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 02061 02062 #define NVIC_USER_IRQ_OFFSET 16 02063 02064 02065 /* Special LR values for Secure/Non-Secure call handling and exception handling */ 02066 02067 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ 02068 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ 02069 02070 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ 02071 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ 02072 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ 02073 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ 02074 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ 02075 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ 02076 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ 02077 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ 02078 02079 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ 02080 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ 02081 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ 02082 #else 02083 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ 02084 #endif 02085 02086 02087 /** 02088 \brief Set Priority Grouping 02089 \details Sets the priority grouping field using the required unlock sequence. 02090 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 02091 Only values from 0..7 are used. 02092 In case of a conflict between priority grouping and available 02093 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 02094 \param [in] PriorityGroup Priority grouping field. 02095 */ 02096 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 02097 { 02098 uint32_t reg_value; 02099 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02100 02101 reg_value = SCB->AIRCR; /* read old register configuration */ 02102 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 02103 reg_value = (reg_value | 02104 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 02105 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 02106 SCB->AIRCR = reg_value; 02107 } 02108 02109 02110 /** 02111 \brief Get Priority Grouping 02112 \details Reads the priority grouping field from the NVIC Interrupt Controller. 02113 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 02114 */ 02115 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 02116 { 02117 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 02118 } 02119 02120 02121 /** 02122 \brief Enable Interrupt 02123 \details Enables a device specific interrupt in the NVIC interrupt controller. 02124 \param [in] IRQn Device specific interrupt number. 02125 \note IRQn must not be negative. 02126 */ 02127 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 02128 { 02129 if ((int32_t)(IRQn) >= 0) 02130 { 02131 __COMPILER_BARRIER(); 02132 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02133 __COMPILER_BARRIER(); 02134 } 02135 } 02136 02137 02138 /** 02139 \brief Get Interrupt Enable status 02140 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 02141 \param [in] IRQn Device specific interrupt number. 02142 \return 0 Interrupt is not enabled. 02143 \return 1 Interrupt is enabled. 02144 \note IRQn must not be negative. 02145 */ 02146 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 02147 { 02148 if ((int32_t)(IRQn) >= 0) 02149 { 02150 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02151 } 02152 else 02153 { 02154 return(0U); 02155 } 02156 } 02157 02158 02159 /** 02160 \brief Disable Interrupt 02161 \details Disables a device specific interrupt in the NVIC interrupt controller. 02162 \param [in] IRQn Device specific interrupt number. 02163 \note IRQn must not be negative. 02164 */ 02165 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 02166 { 02167 if ((int32_t)(IRQn) >= 0) 02168 { 02169 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02170 __DSB(); 02171 __ISB(); 02172 } 02173 } 02174 02175 02176 /** 02177 \brief Get Pending Interrupt 02178 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 02179 \param [in] IRQn Device specific interrupt number. 02180 \return 0 Interrupt status is not pending. 02181 \return 1 Interrupt status is pending. 02182 \note IRQn must not be negative. 02183 */ 02184 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 02185 { 02186 if ((int32_t)(IRQn) >= 0) 02187 { 02188 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02189 } 02190 else 02191 { 02192 return(0U); 02193 } 02194 } 02195 02196 02197 /** 02198 \brief Set Pending Interrupt 02199 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 02200 \param [in] IRQn Device specific interrupt number. 02201 \note IRQn must not be negative. 02202 */ 02203 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 02204 { 02205 if ((int32_t)(IRQn) >= 0) 02206 { 02207 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02208 } 02209 } 02210 02211 02212 /** 02213 \brief Clear Pending Interrupt 02214 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 02215 \param [in] IRQn Device specific interrupt number. 02216 \note IRQn must not be negative. 02217 */ 02218 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 02219 { 02220 if ((int32_t)(IRQn) >= 0) 02221 { 02222 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02223 } 02224 } 02225 02226 02227 /** 02228 \brief Get Active Interrupt 02229 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 02230 \param [in] IRQn Device specific interrupt number. 02231 \return 0 Interrupt status is not active. 02232 \return 1 Interrupt status is active. 02233 \note IRQn must not be negative. 02234 */ 02235 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 02236 { 02237 if ((int32_t)(IRQn) >= 0) 02238 { 02239 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02240 } 02241 else 02242 { 02243 return(0U); 02244 } 02245 } 02246 02247 02248 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02249 /** 02250 \brief Get Interrupt Target State 02251 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 02252 \param [in] IRQn Device specific interrupt number. 02253 \return 0 if interrupt is assigned to Secure 02254 \return 1 if interrupt is assigned to Non Secure 02255 \note IRQn must not be negative. 02256 */ 02257 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 02258 { 02259 if ((int32_t)(IRQn) >= 0) 02260 { 02261 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02262 } 02263 else 02264 { 02265 return(0U); 02266 } 02267 } 02268 02269 02270 /** 02271 \brief Set Interrupt Target State 02272 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 02273 \param [in] IRQn Device specific interrupt number. 02274 \return 0 if interrupt is assigned to Secure 02275 1 if interrupt is assigned to Non Secure 02276 \note IRQn must not be negative. 02277 */ 02278 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 02279 { 02280 if ((int32_t)(IRQn) >= 0) 02281 { 02282 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 02283 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02284 } 02285 else 02286 { 02287 return(0U); 02288 } 02289 } 02290 02291 02292 /** 02293 \brief Clear Interrupt Target State 02294 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 02295 \param [in] IRQn Device specific interrupt number. 02296 \return 0 if interrupt is assigned to Secure 02297 1 if interrupt is assigned to Non Secure 02298 \note IRQn must not be negative. 02299 */ 02300 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 02301 { 02302 if ((int32_t)(IRQn) >= 0) 02303 { 02304 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 02305 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02306 } 02307 else 02308 { 02309 return(0U); 02310 } 02311 } 02312 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02313 02314 02315 /** 02316 \brief Set Interrupt Priority 02317 \details Sets the priority of a device specific interrupt or a processor exception. 02318 The interrupt number can be positive to specify a device specific interrupt, 02319 or negative to specify a processor exception. 02320 \param [in] IRQn Interrupt number. 02321 \param [in] priority Priority to set. 02322 \note The priority cannot be set for every processor exception. 02323 */ 02324 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 02325 { 02326 if ((int32_t)(IRQn) >= 0) 02327 { 02328 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02329 } 02330 else 02331 { 02332 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02333 } 02334 } 02335 02336 02337 /** 02338 \brief Get Interrupt Priority 02339 \details Reads the priority of a device specific interrupt or a processor exception. 02340 The interrupt number can be positive to specify a device specific interrupt, 02341 or negative to specify a processor exception. 02342 \param [in] IRQn Interrupt number. 02343 \return Interrupt Priority. 02344 Value is aligned automatically to the implemented priority bits of the microcontroller. 02345 */ 02346 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 02347 { 02348 02349 if ((int32_t)(IRQn) >= 0) 02350 { 02351 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 02352 } 02353 else 02354 { 02355 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 02356 } 02357 } 02358 02359 02360 /** 02361 \brief Encode Priority 02362 \details Encodes the priority for an interrupt with the given priority group, 02363 preemptive priority value, and subpriority value. 02364 In case of a conflict between priority grouping and available 02365 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 02366 \param [in] PriorityGroup Used priority group. 02367 \param [in] PreemptPriority Preemptive priority value (starting from 0). 02368 \param [in] SubPriority Subpriority value (starting from 0). 02369 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 02370 */ 02371 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 02372 { 02373 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02374 uint32_t PreemptPriorityBits; 02375 uint32_t SubPriorityBits; 02376 02377 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 02378 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 02379 02380 return ( 02381 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 02382 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 02383 ); 02384 } 02385 02386 02387 /** 02388 \brief Decode Priority 02389 \details Decodes an interrupt priority value with a given priority group to 02390 preemptive priority value and subpriority value. 02391 In case of a conflict between priority grouping and available 02392 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 02393 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 02394 \param [in] PriorityGroup Used priority group. 02395 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 02396 \param [out] pSubPriority Subpriority value (starting from 0). 02397 */ 02398 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 02399 { 02400 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02401 uint32_t PreemptPriorityBits; 02402 uint32_t SubPriorityBits; 02403 02404 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 02405 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 02406 02407 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 02408 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 02409 } 02410 02411 02412 /** 02413 \brief Set Interrupt Vector 02414 \details Sets an interrupt vector in SRAM based interrupt vector table. 02415 The interrupt number can be positive to specify a device specific interrupt, 02416 or negative to specify a processor exception. 02417 VTOR must been relocated to SRAM before. 02418 \param [in] IRQn Interrupt number 02419 \param [in] vector Address of interrupt handler function 02420 */ 02421 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 02422 { 02423 uint32_t *vectors = (uint32_t *)SCB->VTOR; 02424 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 02425 __DSB(); 02426 } 02427 02428 02429 /** 02430 \brief Get Interrupt Vector 02431 \details Reads an interrupt vector from interrupt vector table. 02432 The interrupt number can be positive to specify a device specific interrupt, 02433 or negative to specify a processor exception. 02434 \param [in] IRQn Interrupt number. 02435 \return Address of interrupt handler function 02436 */ 02437 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 02438 { 02439 uint32_t *vectors = (uint32_t *)SCB->VTOR; 02440 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 02441 } 02442 02443 02444 /** 02445 \brief System Reset 02446 \details Initiates a system reset request to reset the MCU. 02447 */ 02448 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 02449 { 02450 __DSB(); /* Ensure all outstanding memory accesses included 02451 buffered write are completed before reset */ 02452 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 02453 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 02454 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 02455 __DSB(); /* Ensure completion of memory access */ 02456 02457 for(;;) /* wait until reset */ 02458 { 02459 __NOP(); 02460 } 02461 } 02462 02463 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02464 /** 02465 \brief Set Priority Grouping (non-secure) 02466 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. 02467 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 02468 Only values from 0..7 are used. 02469 In case of a conflict between priority grouping and available 02470 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 02471 \param [in] PriorityGroup Priority grouping field. 02472 */ 02473 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) 02474 { 02475 uint32_t reg_value; 02476 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02477 02478 reg_value = SCB_NS->AIRCR; /* read old register configuration */ 02479 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 02480 reg_value = (reg_value | 02481 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 02482 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 02483 SCB_NS->AIRCR = reg_value; 02484 } 02485 02486 02487 /** 02488 \brief Get Priority Grouping (non-secure) 02489 \details Reads the priority grouping field from the non-secure NVIC when in secure state. 02490 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 02491 */ 02492 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) 02493 { 02494 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 02495 } 02496 02497 02498 /** 02499 \brief Enable Interrupt (non-secure) 02500 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 02501 \param [in] IRQn Device specific interrupt number. 02502 \note IRQn must not be negative. 02503 */ 02504 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 02505 { 02506 if ((int32_t)(IRQn) >= 0) 02507 { 02508 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02509 } 02510 } 02511 02512 02513 /** 02514 \brief Get Interrupt Enable status (non-secure) 02515 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 02516 \param [in] IRQn Device specific interrupt number. 02517 \return 0 Interrupt is not enabled. 02518 \return 1 Interrupt is enabled. 02519 \note IRQn must not be negative. 02520 */ 02521 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 02522 { 02523 if ((int32_t)(IRQn) >= 0) 02524 { 02525 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02526 } 02527 else 02528 { 02529 return(0U); 02530 } 02531 } 02532 02533 02534 /** 02535 \brief Disable Interrupt (non-secure) 02536 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 02537 \param [in] IRQn Device specific interrupt number. 02538 \note IRQn must not be negative. 02539 */ 02540 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 02541 { 02542 if ((int32_t)(IRQn) >= 0) 02543 { 02544 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02545 } 02546 } 02547 02548 02549 /** 02550 \brief Get Pending Interrupt (non-secure) 02551 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 02552 \param [in] IRQn Device specific interrupt number. 02553 \return 0 Interrupt status is not pending. 02554 \return 1 Interrupt status is pending. 02555 \note IRQn must not be negative. 02556 */ 02557 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 02558 { 02559 if ((int32_t)(IRQn) >= 0) 02560 { 02561 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02562 } 02563 else 02564 { 02565 return(0U); 02566 } 02567 } 02568 02569 02570 /** 02571 \brief Set Pending Interrupt (non-secure) 02572 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 02573 \param [in] IRQn Device specific interrupt number. 02574 \note IRQn must not be negative. 02575 */ 02576 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 02577 { 02578 if ((int32_t)(IRQn) >= 0) 02579 { 02580 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02581 } 02582 } 02583 02584 02585 /** 02586 \brief Clear Pending Interrupt (non-secure) 02587 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 02588 \param [in] IRQn Device specific interrupt number. 02589 \note IRQn must not be negative. 02590 */ 02591 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 02592 { 02593 if ((int32_t)(IRQn) >= 0) 02594 { 02595 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02596 } 02597 } 02598 02599 02600 /** 02601 \brief Get Active Interrupt (non-secure) 02602 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 02603 \param [in] IRQn Device specific interrupt number. 02604 \return 0 Interrupt status is not active. 02605 \return 1 Interrupt status is active. 02606 \note IRQn must not be negative. 02607 */ 02608 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 02609 { 02610 if ((int32_t)(IRQn) >= 0) 02611 { 02612 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02613 } 02614 else 02615 { 02616 return(0U); 02617 } 02618 } 02619 02620 02621 /** 02622 \brief Set Interrupt Priority (non-secure) 02623 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 02624 The interrupt number can be positive to specify a device specific interrupt, 02625 or negative to specify a processor exception. 02626 \param [in] IRQn Interrupt number. 02627 \param [in] priority Priority to set. 02628 \note The priority cannot be set for every non-secure processor exception. 02629 */ 02630 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 02631 { 02632 if ((int32_t)(IRQn) >= 0) 02633 { 02634 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02635 } 02636 else 02637 { 02638 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02639 } 02640 } 02641 02642 02643 /** 02644 \brief Get Interrupt Priority (non-secure) 02645 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 02646 The interrupt number can be positive to specify a device specific interrupt, 02647 or negative to specify a processor exception. 02648 \param [in] IRQn Interrupt number. 02649 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 02650 */ 02651 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 02652 { 02653 02654 if ((int32_t)(IRQn) >= 0) 02655 { 02656 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 02657 } 02658 else 02659 { 02660 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 02661 } 02662 } 02663 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 02664 02665 /*@} end of CMSIS_Core_NVICFunctions */ 02666 02667 /* ########################## MPU functions #################################### */ 02668 02669 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 02670 02671 #include "mpu_armv8.h" 02672 02673 #endif 02674 02675 /* ########################## FPU functions #################################### */ 02676 /** 02677 \ingroup CMSIS_Core_FunctionInterface 02678 \defgroup CMSIS_Core_FpuFunctions FPU Functions 02679 \brief Function that provides FPU type. 02680 @{ 02681 */ 02682 02683 /** 02684 \brief get FPU type 02685 \details returns the FPU type 02686 \returns 02687 - \b 0: No FPU 02688 - \b 1: Single precision FPU 02689 - \b 2: Double + Single precision FPU 02690 */ 02691 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 02692 { 02693 uint32_t mvfr0; 02694 02695 mvfr0 = FPU->MVFR0; 02696 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) 02697 { 02698 return 2U; /* Double + Single precision FPU */ 02699 } 02700 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) 02701 { 02702 return 1U; /* Single precision FPU */ 02703 } 02704 else 02705 { 02706 return 0U; /* No FPU */ 02707 } 02708 } 02709 02710 02711 /*@} end of CMSIS_Core_FpuFunctions */ 02712 02713 02714 02715 /* ########################## SAU functions #################################### */ 02716 /** 02717 \ingroup CMSIS_Core_FunctionInterface 02718 \defgroup CMSIS_Core_SAUFunctions SAU Functions 02719 \brief Functions that configure the SAU. 02720 @{ 02721 */ 02722 02723 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02724 02725 /** 02726 \brief Enable SAU 02727 \details Enables the Security Attribution Unit (SAU). 02728 */ 02729 __STATIC_INLINE void TZ_SAU_Enable(void) 02730 { 02731 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 02732 } 02733 02734 02735 02736 /** 02737 \brief Disable SAU 02738 \details Disables the Security Attribution Unit (SAU). 02739 */ 02740 __STATIC_INLINE void TZ_SAU_Disable(void) 02741 { 02742 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 02743 } 02744 02745 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02746 02747 /*@} end of CMSIS_Core_SAUFunctions */ 02748 02749 02750 02751 02752 /* ################################## SysTick function ############################################ */ 02753 /** 02754 \ingroup CMSIS_Core_FunctionInterface 02755 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 02756 \brief Functions that configure the System. 02757 @{ 02758 */ 02759 02760 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 02761 02762 /** 02763 \brief System Tick Configuration 02764 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 02765 Counter is in free running mode to generate periodic interrupts. 02766 \param [in] ticks Number of ticks between two interrupts. 02767 \return 0 Function succeeded. 02768 \return 1 Function failed. 02769 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 02770 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 02771 must contain a vendor-specific implementation of this function. 02772 */ 02773 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 02774 { 02775 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 02776 { 02777 return (1UL); /* Reload value impossible */ 02778 } 02779 02780 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 02781 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 02782 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 02783 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02784 SysTick_CTRL_TICKINT_Msk | 02785 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02786 return (0UL); /* Function successful */ 02787 } 02788 02789 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02790 /** 02791 \brief System Tick Configuration (non-secure) 02792 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 02793 Counter is in free running mode to generate periodic interrupts. 02794 \param [in] ticks Number of ticks between two interrupts. 02795 \return 0 Function succeeded. 02796 \return 1 Function failed. 02797 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 02798 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 02799 must contain a vendor-specific implementation of this function. 02800 02801 */ 02802 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 02803 { 02804 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 02805 { 02806 return (1UL); /* Reload value impossible */ 02807 } 02808 02809 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 02810 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 02811 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 02812 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02813 SysTick_CTRL_TICKINT_Msk | 02814 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02815 return (0UL); /* Function successful */ 02816 } 02817 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02818 02819 #endif 02820 02821 /*@} end of CMSIS_Core_SysTickFunctions */ 02822 02823 02824 02825 /* ##################################### Debug In/Output function ########################################### */ 02826 /** 02827 \ingroup CMSIS_Core_FunctionInterface 02828 \defgroup CMSIS_core_DebugFunctions ITM Functions 02829 \brief Functions that access the ITM debug interface. 02830 @{ 02831 */ 02832 02833 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 02834 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 02835 02836 02837 /** 02838 \brief ITM Send Character 02839 \details Transmits a character via the ITM channel 0, and 02840 \li Just returns when no debugger is connected that has booked the output. 02841 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 02842 \param [in] ch Character to transmit. 02843 \returns Character to transmit. 02844 */ 02845 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 02846 { 02847 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 02848 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 02849 { 02850 while (ITM->PORT[0U].u32 == 0UL) 02851 { 02852 __NOP(); 02853 } 02854 ITM->PORT[0U].u8 = (uint8_t)ch; 02855 } 02856 return (ch); 02857 } 02858 02859 02860 /** 02861 \brief ITM Receive Character 02862 \details Inputs a character via the external variable \ref ITM_RxBuffer. 02863 \return Received character. 02864 \return -1 No character pending. 02865 */ 02866 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 02867 { 02868 int32_t ch = -1; /* no character available */ 02869 02870 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 02871 { 02872 ch = ITM_RxBuffer; 02873 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 02874 } 02875 02876 return (ch); 02877 } 02878 02879 02880 /** 02881 \brief ITM Check Character 02882 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 02883 \return 0 No character available. 02884 \return 1 Character available. 02885 */ 02886 __STATIC_INLINE int32_t ITM_CheckChar (void) 02887 { 02888 02889 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 02890 { 02891 return (0); /* no character available */ 02892 } 02893 else 02894 { 02895 return (1); /* character available */ 02896 } 02897 } 02898 02899 /*@} end of CMSIS_core_DebugFunctions */ 02900 02901 02902 02903 02904 #ifdef __cplusplus 02905 } 02906 #endif 02907 02908 #endif /* __CORE_CM33_H_DEPENDANT */ 02909 02910 #endif /* __CMSIS_GENERIC */
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