Arrow
/
DAPLink Reset
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Embed:
(wiki syntax)
Show/hide line numbers
core_cm23.h
Go to the documentation of this file.
00001 /**************************************************************************//** 00002 * @file core_cm23.h 00003 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File 00004 * @version V5.0.8 00005 * @date 12. November 2018 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__clang__) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_CM23_H_GENERIC 00032 #define __CORE_CM23_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_M23 00060 @{ 00061 */ 00062 00063 #include "cmsis_version.h" 00064 00065 /* CMSIS definitions */ 00066 #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 00067 #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 00068 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ 00069 __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 00070 00071 #define __CORTEX_M (23U) /*!< Cortex-M Core */ 00072 00073 /** __FPU_USED indicates whether an FPU is used or not. 00074 This core does not support an FPU at all 00075 */ 00076 #define __FPU_USED 0U 00077 00078 #if defined ( __CC_ARM ) 00079 #if defined __TARGET_FPU_VFP 00080 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00081 #endif 00082 00083 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00084 #if defined __ARM_FP 00085 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00086 #endif 00087 00088 #elif defined ( __GNUC__ ) 00089 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00090 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00091 #endif 00092 00093 #elif defined ( __ICCARM__ ) 00094 #if defined __ARMVFP__ 00095 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00096 #endif 00097 00098 #elif defined ( __TI_ARM__ ) 00099 #if defined __TI_VFP_SUPPORT__ 00100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00101 #endif 00102 00103 #elif defined ( __TASKING__ ) 00104 #if defined __FPU_VFP__ 00105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00106 #endif 00107 00108 #elif defined ( __CSMC__ ) 00109 #if ( __CSMC__ & 0x400U) 00110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00111 #endif 00112 00113 #endif 00114 00115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00116 00117 00118 #ifdef __cplusplus 00119 } 00120 #endif 00121 00122 #endif /* __CORE_CM23_H_GENERIC */ 00123 00124 #ifndef __CMSIS_GENERIC 00125 00126 #ifndef __CORE_CM23_H_DEPENDANT 00127 #define __CORE_CM23_H_DEPENDANT 00128 00129 #ifdef __cplusplus 00130 extern "C" { 00131 #endif 00132 00133 /* check device defines and use defaults */ 00134 #if defined __CHECK_DEVICE_DEFINES 00135 #ifndef __CM23_REV 00136 #define __CM23_REV 0x0000U 00137 #warning "__CM23_REV not defined in device header file; using default!" 00138 #endif 00139 00140 #ifndef __FPU_PRESENT 00141 #define __FPU_PRESENT 0U 00142 #warning "__FPU_PRESENT not defined in device header file; using default!" 00143 #endif 00144 00145 #ifndef __MPU_PRESENT 00146 #define __MPU_PRESENT 0U 00147 #warning "__MPU_PRESENT not defined in device header file; using default!" 00148 #endif 00149 00150 #ifndef __SAUREGION_PRESENT 00151 #define __SAUREGION_PRESENT 0U 00152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 00153 #endif 00154 00155 #ifndef __VTOR_PRESENT 00156 #define __VTOR_PRESENT 0U 00157 #warning "__VTOR_PRESENT not defined in device header file; using default!" 00158 #endif 00159 00160 #ifndef __NVIC_PRIO_BITS 00161 #define __NVIC_PRIO_BITS 2U 00162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00163 #endif 00164 00165 #ifndef __Vendor_SysTickConfig 00166 #define __Vendor_SysTickConfig 0U 00167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00168 #endif 00169 00170 #ifndef __ETM_PRESENT 00171 #define __ETM_PRESENT 0U 00172 #warning "__ETM_PRESENT not defined in device header file; using default!" 00173 #endif 00174 00175 #ifndef __MTB_PRESENT 00176 #define __MTB_PRESENT 0U 00177 #warning "__MTB_PRESENT not defined in device header file; using default!" 00178 #endif 00179 00180 #endif 00181 00182 /* IO definitions (access restrictions to peripheral registers) */ 00183 /** 00184 \defgroup CMSIS_glob_defs CMSIS Global Defines 00185 00186 <strong>IO Type Qualifiers</strong> are used 00187 \li to specify the access to peripheral variables. 00188 \li for automatic generation of peripheral register debug information. 00189 */ 00190 #ifdef __cplusplus 00191 #define __I volatile /*!< Defines 'read only' permissions */ 00192 #else 00193 #define __I volatile const /*!< Defines 'read only' permissions */ 00194 #endif 00195 #define __O volatile /*!< Defines 'write only' permissions */ 00196 #define __IO volatile /*!< Defines 'read / write' permissions */ 00197 00198 /* following defines should be used for structure members */ 00199 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00200 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00202 00203 /*@} end of group Cortex_M23 */ 00204 00205 00206 00207 /******************************************************************************* 00208 * Register Abstraction 00209 Core Register contain: 00210 - Core Register 00211 - Core NVIC Register 00212 - Core SCB Register 00213 - Core SysTick Register 00214 - Core Debug Register 00215 - Core MPU Register 00216 - Core SAU Register 00217 ******************************************************************************/ 00218 /** 00219 \defgroup CMSIS_core_register Defines and Type Definitions 00220 \brief Type definitions and defines for Cortex-M processor based devices. 00221 */ 00222 00223 /** 00224 \ingroup CMSIS_core_register 00225 \defgroup CMSIS_CORE Status and Control Registers 00226 \brief Core Register type definitions. 00227 @{ 00228 */ 00229 00230 /** 00231 \brief Union type to access the Application Program Status Register (APSR). 00232 */ 00233 typedef union 00234 { 00235 struct 00236 { 00237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 00238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00242 } b; /*!< Structure used for bit access */ 00243 uint32_t w; /*!< Type used for word access */ 00244 } APSR_Type; 00245 00246 /* APSR Register Definitions */ 00247 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00249 00250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00252 00253 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00255 00256 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00258 00259 00260 /** 00261 \brief Union type to access the Interrupt Program Status Register (IPSR). 00262 */ 00263 typedef union 00264 { 00265 struct 00266 { 00267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00269 } b; /*!< Structure used for bit access */ 00270 uint32_t w; /*!< Type used for word access */ 00271 } IPSR_Type; 00272 00273 /* IPSR Register Definitions */ 00274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00276 00277 00278 /** 00279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00280 */ 00281 typedef union 00282 { 00283 struct 00284 { 00285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 00289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00293 } b; /*!< Structure used for bit access */ 00294 uint32_t w; /*!< Type used for word access */ 00295 } xPSR_Type; 00296 00297 /* xPSR Register Definitions */ 00298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00300 00301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00303 00304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00306 00307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00309 00310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00312 00313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00315 00316 00317 /** 00318 \brief Union type to access the Control Registers (CONTROL). 00319 */ 00320 typedef union 00321 { 00322 struct 00323 { 00324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ 00326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00327 } b; /*!< Structure used for bit access */ 00328 uint32_t w; /*!< Type used for word access */ 00329 } CONTROL_Type; 00330 00331 /* CONTROL Register Definitions */ 00332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00334 00335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00337 00338 /*@} end of group CMSIS_CORE */ 00339 00340 00341 /** 00342 \ingroup CMSIS_core_register 00343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00344 \brief Type definitions for the NVIC Registers 00345 @{ 00346 */ 00347 00348 /** 00349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00350 */ 00351 typedef struct 00352 { 00353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00354 uint32_t RESERVED0[16U]; 00355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00356 uint32_t RSERVED1[16U]; 00357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00358 uint32_t RESERVED2[16U]; 00359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00360 uint32_t RESERVED3[16U]; 00361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00362 uint32_t RESERVED4[16U]; 00363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 00364 uint32_t RESERVED5[16U]; 00365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00366 } NVIC_Type; 00367 00368 /*@} end of group CMSIS_NVIC */ 00369 00370 00371 /** 00372 \ingroup CMSIS_core_register 00373 \defgroup CMSIS_SCB System Control Block (SCB) 00374 \brief Type definitions for the System Control Block Registers 00375 @{ 00376 */ 00377 00378 /** 00379 \brief Structure type to access the System Control Block (SCB). 00380 */ 00381 typedef struct 00382 { 00383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00387 #else 00388 uint32_t RESERVED0; 00389 #endif 00390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00393 uint32_t RESERVED1; 00394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00396 } SCB_Type; 00397 00398 /* SCB CPUID Register Definitions */ 00399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00401 00402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00404 00405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00407 00408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00410 00411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00413 00414 /* SCB Interrupt Control State Register Definitions */ 00415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 00416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 00417 00418 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ 00419 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ 00420 00421 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 00422 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 00423 00424 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00425 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00426 00427 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00428 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00429 00430 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00431 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00432 00433 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00434 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00435 00436 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 00437 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 00438 00439 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00440 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00441 00442 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00443 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00444 00445 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00446 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00447 00448 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00449 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00450 00451 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00453 00454 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00455 /* SCB Vector Table Offset Register Definitions */ 00456 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00457 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00458 #endif 00459 00460 /* SCB Application Interrupt and Reset Control Register Definitions */ 00461 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00462 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00463 00464 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00465 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00466 00467 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00468 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00469 00470 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 00471 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 00472 00473 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 00474 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 00475 00476 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 00477 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 00478 00479 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00480 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00481 00482 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00483 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00484 00485 /* SCB System Control Register Definitions */ 00486 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00487 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00488 00489 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 00490 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 00491 00492 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00493 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00494 00495 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00496 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00497 00498 /* SCB Configuration Control Register Definitions */ 00499 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 00500 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 00501 00502 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 00503 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 00504 00505 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 00506 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 00507 00508 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 00509 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 00510 00511 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00512 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00513 00514 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00515 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00516 00517 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00518 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00519 00520 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00521 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00522 00523 /* SCB System Handler Control and State Register Definitions */ 00524 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 00525 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 00526 00527 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00528 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00529 00530 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00531 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00532 00533 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00534 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00535 00536 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00537 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00538 00539 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 00540 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 00541 00542 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 00543 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 00544 00545 /*@} end of group CMSIS_SCB */ 00546 00547 00548 /** 00549 \ingroup CMSIS_core_register 00550 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00551 \brief Type definitions for the System Timer Registers. 00552 @{ 00553 */ 00554 00555 /** 00556 \brief Structure type to access the System Timer (SysTick). 00557 */ 00558 typedef struct 00559 { 00560 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00561 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00562 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00563 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00564 } SysTick_Type; 00565 00566 /* SysTick Control / Status Register Definitions */ 00567 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00568 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00569 00570 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00571 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00572 00573 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00574 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00575 00576 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00577 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00578 00579 /* SysTick Reload Register Definitions */ 00580 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00581 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00582 00583 /* SysTick Current Register Definitions */ 00584 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00585 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00586 00587 /* SysTick Calibration Register Definitions */ 00588 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00589 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00590 00591 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00592 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00593 00594 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00595 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00596 00597 /*@} end of group CMSIS_SysTick */ 00598 00599 00600 /** 00601 \ingroup CMSIS_core_register 00602 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00603 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00604 @{ 00605 */ 00606 00607 /** 00608 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00609 */ 00610 typedef struct 00611 { 00612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 00613 uint32_t RESERVED0[6U]; 00614 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00615 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00616 uint32_t RESERVED1[1U]; 00617 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00618 uint32_t RESERVED2[1U]; 00619 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00620 uint32_t RESERVED3[1U]; 00621 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00622 uint32_t RESERVED4[1U]; 00623 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 00624 uint32_t RESERVED5[1U]; 00625 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 00626 uint32_t RESERVED6[1U]; 00627 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 00628 uint32_t RESERVED7[1U]; 00629 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 00630 uint32_t RESERVED8[1U]; 00631 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 00632 uint32_t RESERVED9[1U]; 00633 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 00634 uint32_t RESERVED10[1U]; 00635 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 00636 uint32_t RESERVED11[1U]; 00637 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 00638 uint32_t RESERVED12[1U]; 00639 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 00640 uint32_t RESERVED13[1U]; 00641 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 00642 uint32_t RESERVED14[1U]; 00643 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 00644 uint32_t RESERVED15[1U]; 00645 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 00646 uint32_t RESERVED16[1U]; 00647 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 00648 uint32_t RESERVED17[1U]; 00649 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 00650 uint32_t RESERVED18[1U]; 00651 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 00652 uint32_t RESERVED19[1U]; 00653 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 00654 uint32_t RESERVED20[1U]; 00655 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 00656 uint32_t RESERVED21[1U]; 00657 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 00658 uint32_t RESERVED22[1U]; 00659 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 00660 uint32_t RESERVED23[1U]; 00661 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 00662 uint32_t RESERVED24[1U]; 00663 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 00664 uint32_t RESERVED25[1U]; 00665 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 00666 uint32_t RESERVED26[1U]; 00667 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 00668 uint32_t RESERVED27[1U]; 00669 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 00670 uint32_t RESERVED28[1U]; 00671 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 00672 uint32_t RESERVED29[1U]; 00673 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 00674 uint32_t RESERVED30[1U]; 00675 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 00676 uint32_t RESERVED31[1U]; 00677 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 00678 } DWT_Type; 00679 00680 /* DWT Control Register Definitions */ 00681 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 00682 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 00683 00684 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 00685 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 00686 00687 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 00688 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 00689 00690 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 00691 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 00692 00693 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 00694 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 00695 00696 /* DWT Comparator Function Register Definitions */ 00697 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 00698 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 00699 00700 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 00701 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 00702 00703 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 00704 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 00705 00706 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 00707 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 00708 00709 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 00710 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 00711 00712 /*@}*/ /* end of group CMSIS_DWT */ 00713 00714 00715 /** 00716 \ingroup CMSIS_core_register 00717 \defgroup CMSIS_TPI Trace Port Interface (TPI) 00718 \brief Type definitions for the Trace Port Interface (TPI) 00719 @{ 00720 */ 00721 00722 /** 00723 \brief Structure type to access the Trace Port Interface Register (TPI). 00724 */ 00725 typedef struct 00726 { 00727 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 00728 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 00729 uint32_t RESERVED0[2U]; 00730 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 00731 uint32_t RESERVED1[55U]; 00732 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 00733 uint32_t RESERVED2[131U]; 00734 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 00735 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 00736 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ 00737 uint32_t RESERVED3[759U]; 00738 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 00739 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ 00740 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ 00741 uint32_t RESERVED4[1U]; 00742 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ 00743 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ 00744 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 00745 uint32_t RESERVED5[39U]; 00746 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 00747 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 00748 uint32_t RESERVED7[8U]; 00749 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ 00750 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ 00751 } TPI_Type; 00752 00753 /* TPI Asynchronous Clock Prescaler Register Definitions */ 00754 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 00755 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 00756 00757 /* TPI Selected Pin Protocol Register Definitions */ 00758 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 00759 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 00760 00761 /* TPI Formatter and Flush Status Register Definitions */ 00762 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 00763 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 00764 00765 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 00766 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 00767 00768 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 00769 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 00770 00771 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 00772 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 00773 00774 /* TPI Formatter and Flush Control Register Definitions */ 00775 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 00776 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 00777 00778 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ 00779 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ 00780 00781 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 00782 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 00783 00784 /* TPI TRIGGER Register Definitions */ 00785 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 00786 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 00787 00788 /* TPI Integration Test FIFO Test Data 0 Register Definitions */ 00789 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ 00790 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ 00791 00792 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ 00793 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ 00794 00795 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ 00796 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ 00797 00798 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ 00799 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ 00800 00801 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ 00802 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ 00803 00804 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ 00805 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ 00806 00807 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ 00808 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ 00809 00810 /* TPI Integration Test ATB Control Register 2 Register Definitions */ 00811 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ 00812 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ 00813 00814 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ 00815 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ 00816 00817 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ 00818 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ 00819 00820 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ 00821 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ 00822 00823 /* TPI Integration Test FIFO Test Data 1 Register Definitions */ 00824 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ 00825 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ 00826 00827 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ 00828 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ 00829 00830 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ 00831 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ 00832 00833 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ 00834 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ 00835 00836 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ 00837 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ 00838 00839 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ 00840 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ 00841 00842 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ 00843 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ 00844 00845 /* TPI Integration Test ATB Control Register 0 Definitions */ 00846 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ 00847 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ 00848 00849 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ 00850 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ 00851 00852 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ 00853 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ 00854 00855 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ 00856 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ 00857 00858 /* TPI Integration Mode Control Register Definitions */ 00859 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 00860 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 00861 00862 /* TPI DEVID Register Definitions */ 00863 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 00864 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 00865 00866 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 00867 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 00868 00869 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 00870 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 00871 00872 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ 00873 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ 00874 00875 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 00876 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 00877 00878 /* TPI DEVTYPE Register Definitions */ 00879 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 00880 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 00881 00882 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 00883 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 00884 00885 /*@}*/ /* end of group CMSIS_TPI */ 00886 00887 00888 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 00889 /** 00890 \ingroup CMSIS_core_register 00891 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00892 \brief Type definitions for the Memory Protection Unit (MPU) 00893 @{ 00894 */ 00895 00896 /** 00897 \brief Structure type to access the Memory Protection Unit (MPU). 00898 */ 00899 typedef struct 00900 { 00901 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00902 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00903 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 00904 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00905 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 00906 uint32_t RESERVED0[7U]; 00907 union { 00908 __IOM uint32_t MAIR[2]; 00909 struct { 00910 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 00911 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 00912 }; 00913 }; 00914 } MPU_Type; 00915 00916 #define MPU_TYPE_RALIASES 1U 00917 00918 /* MPU Type Register Definitions */ 00919 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 00920 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00921 00922 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 00923 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00924 00925 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 00926 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 00927 00928 /* MPU Control Register Definitions */ 00929 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 00930 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00931 00932 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 00933 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00934 00935 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 00936 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 00937 00938 /* MPU Region Number Register Definitions */ 00939 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 00940 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 00941 00942 /* MPU Region Base Address Register Definitions */ 00943 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 00944 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 00945 00946 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 00947 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 00948 00949 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 00950 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 00951 00952 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 00953 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 00954 00955 /* MPU Region Limit Address Register Definitions */ 00956 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 00957 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 00958 00959 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 00960 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 00961 00962 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ 00963 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ 00964 00965 /* MPU Memory Attribute Indirection Register 0 Definitions */ 00966 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 00967 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 00968 00969 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 00970 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 00971 00972 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 00973 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 00974 00975 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 00976 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 00977 00978 /* MPU Memory Attribute Indirection Register 1 Definitions */ 00979 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 00980 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 00981 00982 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 00983 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 00984 00985 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 00986 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 00987 00988 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 00989 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 00990 00991 /*@} end of group CMSIS_MPU */ 00992 #endif 00993 00994 00995 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 00996 /** 00997 \ingroup CMSIS_core_register 00998 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 00999 \brief Type definitions for the Security Attribution Unit (SAU) 01000 @{ 01001 */ 01002 01003 /** 01004 \brief Structure type to access the Security Attribution Unit (SAU). 01005 */ 01006 typedef struct 01007 { 01008 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 01009 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 01010 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 01011 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 01012 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 01013 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 01014 #endif 01015 } SAU_Type; 01016 01017 /* SAU Control Register Definitions */ 01018 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 01019 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 01020 01021 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 01022 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 01023 01024 /* SAU Type Register Definitions */ 01025 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 01026 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 01027 01028 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 01029 /* SAU Region Number Register Definitions */ 01030 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 01031 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 01032 01033 /* SAU Region Base Address Register Definitions */ 01034 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 01035 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 01036 01037 /* SAU Region Limit Address Register Definitions */ 01038 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 01039 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 01040 01041 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 01042 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 01043 01044 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 01045 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 01046 01047 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 01048 01049 /*@} end of group CMSIS_SAU */ 01050 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01051 01052 01053 /** 01054 \ingroup CMSIS_core_register 01055 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01056 \brief Type definitions for the Core Debug Registers 01057 @{ 01058 */ 01059 01060 /** 01061 \brief Structure type to access the Core Debug Register (CoreDebug). 01062 */ 01063 typedef struct 01064 { 01065 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01066 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01067 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01068 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01069 uint32_t RESERVED4[1U]; 01070 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 01071 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 01072 } CoreDebug_Type; 01073 01074 /* Debug Halting Control and Status Register Definitions */ 01075 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01076 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01077 01078 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ 01079 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ 01080 01081 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01082 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01083 01084 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01085 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01086 01087 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01088 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01089 01090 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01091 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01092 01093 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01094 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01095 01096 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01097 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01098 01099 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01100 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01101 01102 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01103 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01104 01105 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01106 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01107 01108 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01109 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01110 01111 /* Debug Core Register Selector Register Definitions */ 01112 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01113 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01114 01115 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01116 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01117 01118 /* Debug Exception and Monitor Control Register */ 01119 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ 01120 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ 01121 01122 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01123 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01124 01125 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01126 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01127 01128 /* Debug Authentication Control Register Definitions */ 01129 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 01130 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 01131 01132 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 01133 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 01134 01135 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ 01136 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 01137 01138 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ 01139 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 01140 01141 /* Debug Security Control and Status Register Definitions */ 01142 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ 01143 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ 01144 01145 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ 01146 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ 01147 01148 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ 01149 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ 01150 01151 /*@} end of group CMSIS_CoreDebug */ 01152 01153 01154 /** 01155 \ingroup CMSIS_core_register 01156 \defgroup CMSIS_core_bitfield Core register bit field macros 01157 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01158 @{ 01159 */ 01160 01161 /** 01162 \brief Mask and shift a bit field value for use in a register bit range. 01163 \param[in] field Name of the register bit field. 01164 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01165 \return Masked and shifted value. 01166 */ 01167 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01168 01169 /** 01170 \brief Mask and shift a register value to extract a bit filed value. 01171 \param[in] field Name of the register bit field. 01172 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01173 \return Masked and shifted bit field value. 01174 */ 01175 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01176 01177 /*@} end of group CMSIS_core_bitfield */ 01178 01179 01180 /** 01181 \ingroup CMSIS_core_register 01182 \defgroup CMSIS_core_base Core Definitions 01183 \brief Definitions for base addresses, unions, and structures. 01184 @{ 01185 */ 01186 01187 /* Memory mapping of Core Hardware */ 01188 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01189 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01190 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01191 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01192 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01193 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01194 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01195 01196 01197 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01198 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01199 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01200 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01201 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01202 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ 01203 01204 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01205 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01206 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01207 #endif 01208 01209 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01210 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 01211 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 01212 #endif 01213 01214 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01215 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 01216 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ 01217 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 01218 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 01219 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 01220 01221 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 01222 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 01223 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 01224 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ 01225 01226 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01227 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 01228 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 01229 #endif 01230 01231 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01232 /*@} */ 01233 01234 01235 01236 /******************************************************************************* 01237 * Hardware Abstraction Layer 01238 Core Function Interface contains: 01239 - Core NVIC Functions 01240 - Core SysTick Functions 01241 - Core Register Access Functions 01242 ******************************************************************************/ 01243 /** 01244 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01245 */ 01246 01247 01248 01249 /* ########################## NVIC functions #################################### */ 01250 /** 01251 \ingroup CMSIS_Core_FunctionInterface 01252 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01253 \brief Functions that manage interrupts and exceptions via the NVIC. 01254 @{ 01255 */ 01256 01257 #ifdef CMSIS_NVIC_VIRTUAL 01258 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 01259 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 01260 #endif 01261 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 01262 #else 01263 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ 01264 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ 01265 #define NVIC_EnableIRQ __NVIC_EnableIRQ 01266 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 01267 #define NVIC_DisableIRQ __NVIC_DisableIRQ 01268 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 01269 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 01270 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 01271 #define NVIC_GetActive __NVIC_GetActive 01272 #define NVIC_SetPriority __NVIC_SetPriority 01273 #define NVIC_GetPriority __NVIC_GetPriority 01274 #define NVIC_SystemReset __NVIC_SystemReset 01275 #endif /* CMSIS_NVIC_VIRTUAL */ 01276 01277 #ifdef CMSIS_VECTAB_VIRTUAL 01278 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01279 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 01280 #endif 01281 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01282 #else 01283 #define NVIC_SetVector __NVIC_SetVector 01284 #define NVIC_GetVector __NVIC_GetVector 01285 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 01286 01287 #define NVIC_USER_IRQ_OFFSET 16 01288 01289 01290 /* Special LR values for Secure/Non-Secure call handling and exception handling */ 01291 01292 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ 01293 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ 01294 01295 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ 01296 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ 01297 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ 01298 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ 01299 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ 01300 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ 01301 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ 01302 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ 01303 01304 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ 01305 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ 01306 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ 01307 #else 01308 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ 01309 #endif 01310 01311 01312 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 01313 /* The following MACROS handle generation of the register offset and byte masks */ 01314 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 01315 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 01316 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 01317 01318 #define __NVIC_SetPriorityGrouping(X) (void)(X) 01319 #define __NVIC_GetPriorityGrouping() (0U) 01320 01321 /** 01322 \brief Enable Interrupt 01323 \details Enables a device specific interrupt in the NVIC interrupt controller. 01324 \param [in] IRQn Device specific interrupt number. 01325 \note IRQn must not be negative. 01326 */ 01327 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 01328 { 01329 if ((int32_t)(IRQn) >= 0) 01330 { 01331 __COMPILER_BARRIER(); 01332 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01333 __COMPILER_BARRIER(); 01334 } 01335 } 01336 01337 01338 /** 01339 \brief Get Interrupt Enable status 01340 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 01341 \param [in] IRQn Device specific interrupt number. 01342 \return 0 Interrupt is not enabled. 01343 \return 1 Interrupt is enabled. 01344 \note IRQn must not be negative. 01345 */ 01346 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 01347 { 01348 if ((int32_t)(IRQn) >= 0) 01349 { 01350 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01351 } 01352 else 01353 { 01354 return(0U); 01355 } 01356 } 01357 01358 01359 /** 01360 \brief Disable Interrupt 01361 \details Disables a device specific interrupt in the NVIC interrupt controller. 01362 \param [in] IRQn Device specific interrupt number. 01363 \note IRQn must not be negative. 01364 */ 01365 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 01366 { 01367 if ((int32_t)(IRQn) >= 0) 01368 { 01369 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01370 __DSB(); 01371 __ISB(); 01372 } 01373 } 01374 01375 01376 /** 01377 \brief Get Pending Interrupt 01378 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 01379 \param [in] IRQn Device specific interrupt number. 01380 \return 0 Interrupt status is not pending. 01381 \return 1 Interrupt status is pending. 01382 \note IRQn must not be negative. 01383 */ 01384 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 01385 { 01386 if ((int32_t)(IRQn) >= 0) 01387 { 01388 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01389 } 01390 else 01391 { 01392 return(0U); 01393 } 01394 } 01395 01396 01397 /** 01398 \brief Set Pending Interrupt 01399 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 01400 \param [in] IRQn Device specific interrupt number. 01401 \note IRQn must not be negative. 01402 */ 01403 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 01404 { 01405 if ((int32_t)(IRQn) >= 0) 01406 { 01407 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01408 } 01409 } 01410 01411 01412 /** 01413 \brief Clear Pending Interrupt 01414 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 01415 \param [in] IRQn Device specific interrupt number. 01416 \note IRQn must not be negative. 01417 */ 01418 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01419 { 01420 if ((int32_t)(IRQn) >= 0) 01421 { 01422 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01423 } 01424 } 01425 01426 01427 /** 01428 \brief Get Active Interrupt 01429 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 01430 \param [in] IRQn Device specific interrupt number. 01431 \return 0 Interrupt status is not active. 01432 \return 1 Interrupt status is active. 01433 \note IRQn must not be negative. 01434 */ 01435 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 01436 { 01437 if ((int32_t)(IRQn) >= 0) 01438 { 01439 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01440 } 01441 else 01442 { 01443 return(0U); 01444 } 01445 } 01446 01447 01448 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01449 /** 01450 \brief Get Interrupt Target State 01451 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01452 \param [in] IRQn Device specific interrupt number. 01453 \return 0 if interrupt is assigned to Secure 01454 \return 1 if interrupt is assigned to Non Secure 01455 \note IRQn must not be negative. 01456 */ 01457 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 01458 { 01459 if ((int32_t)(IRQn) >= 0) 01460 { 01461 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01462 } 01463 else 01464 { 01465 return(0U); 01466 } 01467 } 01468 01469 01470 /** 01471 \brief Set Interrupt Target State 01472 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01473 \param [in] IRQn Device specific interrupt number. 01474 \return 0 if interrupt is assigned to Secure 01475 1 if interrupt is assigned to Non Secure 01476 \note IRQn must not be negative. 01477 */ 01478 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 01479 { 01480 if ((int32_t)(IRQn) >= 0) 01481 { 01482 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 01483 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01484 } 01485 else 01486 { 01487 return(0U); 01488 } 01489 } 01490 01491 01492 /** 01493 \brief Clear Interrupt Target State 01494 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01495 \param [in] IRQn Device specific interrupt number. 01496 \return 0 if interrupt is assigned to Secure 01497 1 if interrupt is assigned to Non Secure 01498 \note IRQn must not be negative. 01499 */ 01500 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 01501 { 01502 if ((int32_t)(IRQn) >= 0) 01503 { 01504 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 01505 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01506 } 01507 else 01508 { 01509 return(0U); 01510 } 01511 } 01512 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01513 01514 01515 /** 01516 \brief Set Interrupt Priority 01517 \details Sets the priority of a device specific interrupt or a processor exception. 01518 The interrupt number can be positive to specify a device specific interrupt, 01519 or negative to specify a processor exception. 01520 \param [in] IRQn Interrupt number. 01521 \param [in] priority Priority to set. 01522 \note The priority cannot be set for every processor exception. 01523 */ 01524 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01525 { 01526 if ((int32_t)(IRQn) >= 0) 01527 { 01528 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01529 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01530 } 01531 else 01532 { 01533 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01534 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01535 } 01536 } 01537 01538 01539 /** 01540 \brief Get Interrupt Priority 01541 \details Reads the priority of a device specific interrupt or a processor exception. 01542 The interrupt number can be positive to specify a device specific interrupt, 01543 or negative to specify a processor exception. 01544 \param [in] IRQn Interrupt number. 01545 \return Interrupt Priority. 01546 Value is aligned automatically to the implemented priority bits of the microcontroller. 01547 */ 01548 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 01549 { 01550 01551 if ((int32_t)(IRQn) >= 0) 01552 { 01553 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01554 } 01555 else 01556 { 01557 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01558 } 01559 } 01560 01561 01562 /** 01563 \brief Encode Priority 01564 \details Encodes the priority for an interrupt with the given priority group, 01565 preemptive priority value, and subpriority value. 01566 In case of a conflict between priority grouping and available 01567 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01568 \param [in] PriorityGroup Used priority group. 01569 \param [in] PreemptPriority Preemptive priority value (starting from 0). 01570 \param [in] SubPriority Subpriority value (starting from 0). 01571 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 01572 */ 01573 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01574 { 01575 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01576 uint32_t PreemptPriorityBits; 01577 uint32_t SubPriorityBits; 01578 01579 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01580 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01581 01582 return ( 01583 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 01584 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 01585 ); 01586 } 01587 01588 01589 /** 01590 \brief Decode Priority 01591 \details Decodes an interrupt priority value with a given priority group to 01592 preemptive priority value and subpriority value. 01593 In case of a conflict between priority grouping and available 01594 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 01595 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 01596 \param [in] PriorityGroup Used priority group. 01597 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 01598 \param [out] pSubPriority Subpriority value (starting from 0). 01599 */ 01600 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 01601 { 01602 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01603 uint32_t PreemptPriorityBits; 01604 uint32_t SubPriorityBits; 01605 01606 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01607 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01608 01609 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 01610 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 01611 } 01612 01613 01614 /** 01615 \brief Set Interrupt Vector 01616 \details Sets an interrupt vector in SRAM based interrupt vector table. 01617 The interrupt number can be positive to specify a device specific interrupt, 01618 or negative to specify a processor exception. 01619 VTOR must been relocated to SRAM before. 01620 If VTOR is not present address 0 must be mapped to SRAM. 01621 \param [in] IRQn Interrupt number 01622 \param [in] vector Address of interrupt handler function 01623 */ 01624 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 01625 { 01626 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 01627 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01628 #else 01629 uint32_t *vectors = (uint32_t *)0x0U; 01630 #endif 01631 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 01632 __DSB(); 01633 } 01634 01635 01636 /** 01637 \brief Get Interrupt Vector 01638 \details Reads an interrupt vector from interrupt vector table. 01639 The interrupt number can be positive to specify a device specific interrupt, 01640 or negative to specify a processor exception. 01641 \param [in] IRQn Interrupt number. 01642 \return Address of interrupt handler function 01643 */ 01644 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 01645 { 01646 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 01647 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01648 #else 01649 uint32_t *vectors = (uint32_t *)0x0U; 01650 #endif 01651 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 01652 } 01653 01654 01655 /** 01656 \brief System Reset 01657 \details Initiates a system reset request to reset the MCU. 01658 */ 01659 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 01660 { 01661 __DSB(); /* Ensure all outstanding memory accesses included 01662 buffered write are completed before reset */ 01663 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01664 SCB_AIRCR_SYSRESETREQ_Msk); 01665 __DSB(); /* Ensure completion of memory access */ 01666 01667 for(;;) /* wait until reset */ 01668 { 01669 __NOP(); 01670 } 01671 } 01672 01673 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01674 /** 01675 \brief Enable Interrupt (non-secure) 01676 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 01677 \param [in] IRQn Device specific interrupt number. 01678 \note IRQn must not be negative. 01679 */ 01680 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 01681 { 01682 if ((int32_t)(IRQn) >= 0) 01683 { 01684 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01685 } 01686 } 01687 01688 01689 /** 01690 \brief Get Interrupt Enable status (non-secure) 01691 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 01692 \param [in] IRQn Device specific interrupt number. 01693 \return 0 Interrupt is not enabled. 01694 \return 1 Interrupt is enabled. 01695 \note IRQn must not be negative. 01696 */ 01697 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 01698 { 01699 if ((int32_t)(IRQn) >= 0) 01700 { 01701 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01702 } 01703 else 01704 { 01705 return(0U); 01706 } 01707 } 01708 01709 01710 /** 01711 \brief Disable Interrupt (non-secure) 01712 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 01713 \param [in] IRQn Device specific interrupt number. 01714 \note IRQn must not be negative. 01715 */ 01716 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 01717 { 01718 if ((int32_t)(IRQn) >= 0) 01719 { 01720 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01721 } 01722 } 01723 01724 01725 /** 01726 \brief Get Pending Interrupt (non-secure) 01727 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 01728 \param [in] IRQn Device specific interrupt number. 01729 \return 0 Interrupt status is not pending. 01730 \return 1 Interrupt status is pending. 01731 \note IRQn must not be negative. 01732 */ 01733 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 01734 { 01735 if ((int32_t)(IRQn) >= 0) 01736 { 01737 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01738 } 01739 else 01740 { 01741 return(0U); 01742 } 01743 } 01744 01745 01746 /** 01747 \brief Set Pending Interrupt (non-secure) 01748 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 01749 \param [in] IRQn Device specific interrupt number. 01750 \note IRQn must not be negative. 01751 */ 01752 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 01753 { 01754 if ((int32_t)(IRQn) >= 0) 01755 { 01756 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01757 } 01758 } 01759 01760 01761 /** 01762 \brief Clear Pending Interrupt (non-secure) 01763 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 01764 \param [in] IRQn Device specific interrupt number. 01765 \note IRQn must not be negative. 01766 */ 01767 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 01768 { 01769 if ((int32_t)(IRQn) >= 0) 01770 { 01771 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01772 } 01773 } 01774 01775 01776 /** 01777 \brief Get Active Interrupt (non-secure) 01778 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 01779 \param [in] IRQn Device specific interrupt number. 01780 \return 0 Interrupt status is not active. 01781 \return 1 Interrupt status is active. 01782 \note IRQn must not be negative. 01783 */ 01784 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 01785 { 01786 if ((int32_t)(IRQn) >= 0) 01787 { 01788 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01789 } 01790 else 01791 { 01792 return(0U); 01793 } 01794 } 01795 01796 01797 /** 01798 \brief Set Interrupt Priority (non-secure) 01799 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 01800 The interrupt number can be positive to specify a device specific interrupt, 01801 or negative to specify a processor exception. 01802 \param [in] IRQn Interrupt number. 01803 \param [in] priority Priority to set. 01804 \note The priority cannot be set for every non-secure processor exception. 01805 */ 01806 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 01807 { 01808 if ((int32_t)(IRQn) >= 0) 01809 { 01810 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01811 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01812 } 01813 else 01814 { 01815 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01816 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01817 } 01818 } 01819 01820 01821 /** 01822 \brief Get Interrupt Priority (non-secure) 01823 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 01824 The interrupt number can be positive to specify a device specific interrupt, 01825 or negative to specify a processor exception. 01826 \param [in] IRQn Interrupt number. 01827 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 01828 */ 01829 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 01830 { 01831 01832 if ((int32_t)(IRQn) >= 0) 01833 { 01834 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01835 } 01836 else 01837 { 01838 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01839 } 01840 } 01841 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 01842 01843 /*@} end of CMSIS_Core_NVICFunctions */ 01844 01845 /* ########################## MPU functions #################################### */ 01846 01847 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01848 01849 #include "mpu_armv8.h" 01850 01851 #endif 01852 01853 /* ########################## FPU functions #################################### */ 01854 /** 01855 \ingroup CMSIS_Core_FunctionInterface 01856 \defgroup CMSIS_Core_FpuFunctions FPU Functions 01857 \brief Function that provides FPU type. 01858 @{ 01859 */ 01860 01861 /** 01862 \brief get FPU type 01863 \details returns the FPU type 01864 \returns 01865 - \b 0: No FPU 01866 - \b 1: Single precision FPU 01867 - \b 2: Double + Single precision FPU 01868 */ 01869 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 01870 { 01871 return 0U; /* No FPU */ 01872 } 01873 01874 01875 /*@} end of CMSIS_Core_FpuFunctions */ 01876 01877 01878 01879 /* ########################## SAU functions #################################### */ 01880 /** 01881 \ingroup CMSIS_Core_FunctionInterface 01882 \defgroup CMSIS_Core_SAUFunctions SAU Functions 01883 \brief Functions that configure the SAU. 01884 @{ 01885 */ 01886 01887 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01888 01889 /** 01890 \brief Enable SAU 01891 \details Enables the Security Attribution Unit (SAU). 01892 */ 01893 __STATIC_INLINE void TZ_SAU_Enable(void) 01894 { 01895 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 01896 } 01897 01898 01899 01900 /** 01901 \brief Disable SAU 01902 \details Disables the Security Attribution Unit (SAU). 01903 */ 01904 __STATIC_INLINE void TZ_SAU_Disable(void) 01905 { 01906 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 01907 } 01908 01909 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01910 01911 /*@} end of CMSIS_Core_SAUFunctions */ 01912 01913 01914 01915 01916 /* ################################## SysTick function ############################################ */ 01917 /** 01918 \ingroup CMSIS_Core_FunctionInterface 01919 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 01920 \brief Functions that configure the System. 01921 @{ 01922 */ 01923 01924 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 01925 01926 /** 01927 \brief System Tick Configuration 01928 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 01929 Counter is in free running mode to generate periodic interrupts. 01930 \param [in] ticks Number of ticks between two interrupts. 01931 \return 0 Function succeeded. 01932 \return 1 Function failed. 01933 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01934 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 01935 must contain a vendor-specific implementation of this function. 01936 */ 01937 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01938 { 01939 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 01940 { 01941 return (1UL); /* Reload value impossible */ 01942 } 01943 01944 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01945 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01946 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 01947 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01948 SysTick_CTRL_TICKINT_Msk | 01949 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01950 return (0UL); /* Function successful */ 01951 } 01952 01953 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01954 /** 01955 \brief System Tick Configuration (non-secure) 01956 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 01957 Counter is in free running mode to generate periodic interrupts. 01958 \param [in] ticks Number of ticks between two interrupts. 01959 \return 0 Function succeeded. 01960 \return 1 Function failed. 01961 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01962 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 01963 must contain a vendor-specific implementation of this function. 01964 01965 */ 01966 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 01967 { 01968 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 01969 { 01970 return (1UL); /* Reload value impossible */ 01971 } 01972 01973 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01974 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01975 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 01976 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01977 SysTick_CTRL_TICKINT_Msk | 01978 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01979 return (0UL); /* Function successful */ 01980 } 01981 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01982 01983 #endif 01984 01985 /*@} end of CMSIS_Core_SysTickFunctions */ 01986 01987 01988 01989 01990 #ifdef __cplusplus 01991 } 01992 #endif 01993 01994 #endif /* __CORE_CM23_H_DEPENDANT */ 01995 01996 #endif /* __CMSIS_GENERIC */
Generated on Tue Jul 12 2022 15:37:14 by
1.7.2