Arrow
/
DAPLink Reset
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Embed:
(wiki syntax)
Show/hide line numbers
core_armv8mbl.h
Go to the documentation of this file.
00001 /**************************************************************************//** 00002 * @file core_armv8mbl.h 00003 * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File 00004 * @version V5.0.8 00005 * @date 12. November 2018 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__clang__) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_ARMV8MBL_H_GENERIC 00032 #define __CORE_ARMV8MBL_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_ARMv8MBL 00060 @{ 00061 */ 00062 00063 #include "cmsis_version.h" 00064 00065 /* CMSIS definitions */ 00066 #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 00067 #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 00068 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ 00069 __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 00070 00071 #define __CORTEX_M ( 2U) /*!< Cortex-M Core */ 00072 00073 /** __FPU_USED indicates whether an FPU is used or not. 00074 This core does not support an FPU at all 00075 */ 00076 #define __FPU_USED 0U 00077 00078 #if defined ( __CC_ARM ) 00079 #if defined __TARGET_FPU_VFP 00080 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00081 #endif 00082 00083 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00084 #if defined __ARM_FP 00085 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00086 #endif 00087 00088 #elif defined ( __GNUC__ ) 00089 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00090 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00091 #endif 00092 00093 #elif defined ( __ICCARM__ ) 00094 #if defined __ARMVFP__ 00095 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00096 #endif 00097 00098 #elif defined ( __TI_ARM__ ) 00099 #if defined __TI_VFP_SUPPORT__ 00100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00101 #endif 00102 00103 #elif defined ( __TASKING__ ) 00104 #if defined __FPU_VFP__ 00105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00106 #endif 00107 00108 #elif defined ( __CSMC__ ) 00109 #if ( __CSMC__ & 0x400U) 00110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00111 #endif 00112 00113 #endif 00114 00115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00116 00117 00118 #ifdef __cplusplus 00119 } 00120 #endif 00121 00122 #endif /* __CORE_ARMV8MBL_H_GENERIC */ 00123 00124 #ifndef __CMSIS_GENERIC 00125 00126 #ifndef __CORE_ARMV8MBL_H_DEPENDANT 00127 #define __CORE_ARMV8MBL_H_DEPENDANT 00128 00129 #ifdef __cplusplus 00130 extern "C" { 00131 #endif 00132 00133 /* check device defines and use defaults */ 00134 #if defined __CHECK_DEVICE_DEFINES 00135 #ifndef __ARMv8MBL_REV 00136 #define __ARMv8MBL_REV 0x0000U 00137 #warning "__ARMv8MBL_REV not defined in device header file; using default!" 00138 #endif 00139 00140 #ifndef __FPU_PRESENT 00141 #define __FPU_PRESENT 0U 00142 #warning "__FPU_PRESENT not defined in device header file; using default!" 00143 #endif 00144 00145 #ifndef __MPU_PRESENT 00146 #define __MPU_PRESENT 0U 00147 #warning "__MPU_PRESENT not defined in device header file; using default!" 00148 #endif 00149 00150 #ifndef __SAUREGION_PRESENT 00151 #define __SAUREGION_PRESENT 0U 00152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 00153 #endif 00154 00155 #ifndef __VTOR_PRESENT 00156 #define __VTOR_PRESENT 0U 00157 #warning "__VTOR_PRESENT not defined in device header file; using default!" 00158 #endif 00159 00160 #ifndef __NVIC_PRIO_BITS 00161 #define __NVIC_PRIO_BITS 2U 00162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00163 #endif 00164 00165 #ifndef __Vendor_SysTickConfig 00166 #define __Vendor_SysTickConfig 0U 00167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00168 #endif 00169 00170 #ifndef __ETM_PRESENT 00171 #define __ETM_PRESENT 0U 00172 #warning "__ETM_PRESENT not defined in device header file; using default!" 00173 #endif 00174 00175 #ifndef __MTB_PRESENT 00176 #define __MTB_PRESENT 0U 00177 #warning "__MTB_PRESENT not defined in device header file; using default!" 00178 #endif 00179 00180 #endif 00181 00182 /* IO definitions (access restrictions to peripheral registers) */ 00183 /** 00184 \defgroup CMSIS_glob_defs CMSIS Global Defines 00185 00186 <strong>IO Type Qualifiers</strong> are used 00187 \li to specify the access to peripheral variables. 00188 \li for automatic generation of peripheral register debug information. 00189 */ 00190 #ifdef __cplusplus 00191 #define __I volatile /*!< Defines 'read only' permissions */ 00192 #else 00193 #define __I volatile const /*!< Defines 'read only' permissions */ 00194 #endif 00195 #define __O volatile /*!< Defines 'write only' permissions */ 00196 #define __IO volatile /*!< Defines 'read / write' permissions */ 00197 00198 /* following defines should be used for structure members */ 00199 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00200 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00202 00203 /*@} end of group ARMv8MBL */ 00204 00205 00206 00207 /******************************************************************************* 00208 * Register Abstraction 00209 Core Register contain: 00210 - Core Register 00211 - Core NVIC Register 00212 - Core SCB Register 00213 - Core SysTick Register 00214 - Core Debug Register 00215 - Core MPU Register 00216 - Core SAU Register 00217 ******************************************************************************/ 00218 /** 00219 \defgroup CMSIS_core_register Defines and Type Definitions 00220 \brief Type definitions and defines for Cortex-M processor based devices. 00221 */ 00222 00223 /** 00224 \ingroup CMSIS_core_register 00225 \defgroup CMSIS_CORE Status and Control Registers 00226 \brief Core Register type definitions. 00227 @{ 00228 */ 00229 00230 /** 00231 \brief Union type to access the Application Program Status Register (APSR). 00232 */ 00233 typedef union 00234 { 00235 struct 00236 { 00237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 00238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00242 } b; /*!< Structure used for bit access */ 00243 uint32_t w; /*!< Type used for word access */ 00244 } APSR_Type; 00245 00246 /* APSR Register Definitions */ 00247 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00249 00250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00252 00253 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00255 00256 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00258 00259 00260 /** 00261 \brief Union type to access the Interrupt Program Status Register (IPSR). 00262 */ 00263 typedef union 00264 { 00265 struct 00266 { 00267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00269 } b; /*!< Structure used for bit access */ 00270 uint32_t w; /*!< Type used for word access */ 00271 } IPSR_Type; 00272 00273 /* IPSR Register Definitions */ 00274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00276 00277 00278 /** 00279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00280 */ 00281 typedef union 00282 { 00283 struct 00284 { 00285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 00289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00293 } b; /*!< Structure used for bit access */ 00294 uint32_t w; /*!< Type used for word access */ 00295 } xPSR_Type; 00296 00297 /* xPSR Register Definitions */ 00298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00300 00301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00303 00304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00306 00307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00309 00310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00312 00313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00315 00316 00317 /** 00318 \brief Union type to access the Control Registers (CONTROL). 00319 */ 00320 typedef union 00321 { 00322 struct 00323 { 00324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ 00326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00327 } b; /*!< Structure used for bit access */ 00328 uint32_t w; /*!< Type used for word access */ 00329 } CONTROL_Type; 00330 00331 /* CONTROL Register Definitions */ 00332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00334 00335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00337 00338 /*@} end of group CMSIS_CORE */ 00339 00340 00341 /** 00342 \ingroup CMSIS_core_register 00343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00344 \brief Type definitions for the NVIC Registers 00345 @{ 00346 */ 00347 00348 /** 00349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00350 */ 00351 typedef struct 00352 { 00353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00354 uint32_t RESERVED0[16U]; 00355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00356 uint32_t RSERVED1[16U]; 00357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00358 uint32_t RESERVED2[16U]; 00359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00360 uint32_t RESERVED3[16U]; 00361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00362 uint32_t RESERVED4[16U]; 00363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 00364 uint32_t RESERVED5[16U]; 00365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00366 } NVIC_Type; 00367 00368 /*@} end of group CMSIS_NVIC */ 00369 00370 00371 /** 00372 \ingroup CMSIS_core_register 00373 \defgroup CMSIS_SCB System Control Block (SCB) 00374 \brief Type definitions for the System Control Block Registers 00375 @{ 00376 */ 00377 00378 /** 00379 \brief Structure type to access the System Control Block (SCB). 00380 */ 00381 typedef struct 00382 { 00383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00387 #else 00388 uint32_t RESERVED0; 00389 #endif 00390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00393 uint32_t RESERVED1; 00394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00396 } SCB_Type; 00397 00398 /* SCB CPUID Register Definitions */ 00399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00401 00402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00404 00405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00407 00408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00410 00411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00413 00414 /* SCB Interrupt Control State Register Definitions */ 00415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 00416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 00417 00418 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ 00419 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ 00420 00421 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 00422 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 00423 00424 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00425 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00426 00427 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00428 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00429 00430 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00431 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00432 00433 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00434 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00435 00436 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 00437 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 00438 00439 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00440 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00441 00442 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00443 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00444 00445 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00446 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00447 00448 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00449 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00450 00451 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00453 00454 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00455 /* SCB Vector Table Offset Register Definitions */ 00456 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00457 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00458 #endif 00459 00460 /* SCB Application Interrupt and Reset Control Register Definitions */ 00461 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00462 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00463 00464 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00465 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00466 00467 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00468 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00469 00470 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 00471 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 00472 00473 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 00474 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 00475 00476 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 00477 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 00478 00479 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00480 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00481 00482 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00483 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00484 00485 /* SCB System Control Register Definitions */ 00486 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00487 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00488 00489 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 00490 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 00491 00492 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00493 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00494 00495 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00496 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00497 00498 /* SCB Configuration Control Register Definitions */ 00499 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 00500 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 00501 00502 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 00503 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 00504 00505 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 00506 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 00507 00508 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 00509 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 00510 00511 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00512 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00513 00514 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00515 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00516 00517 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00518 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00519 00520 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00521 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00522 00523 /* SCB System Handler Control and State Register Definitions */ 00524 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 00525 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 00526 00527 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00528 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00529 00530 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00531 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00532 00533 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00534 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00535 00536 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00537 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00538 00539 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 00540 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 00541 00542 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 00543 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 00544 00545 /*@} end of group CMSIS_SCB */ 00546 00547 00548 /** 00549 \ingroup CMSIS_core_register 00550 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00551 \brief Type definitions for the System Timer Registers. 00552 @{ 00553 */ 00554 00555 /** 00556 \brief Structure type to access the System Timer (SysTick). 00557 */ 00558 typedef struct 00559 { 00560 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00561 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00562 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00563 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00564 } SysTick_Type; 00565 00566 /* SysTick Control / Status Register Definitions */ 00567 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00568 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00569 00570 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00571 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00572 00573 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00574 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00575 00576 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00577 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00578 00579 /* SysTick Reload Register Definitions */ 00580 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00581 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00582 00583 /* SysTick Current Register Definitions */ 00584 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00585 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00586 00587 /* SysTick Calibration Register Definitions */ 00588 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00589 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00590 00591 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00592 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00593 00594 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00595 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00596 00597 /*@} end of group CMSIS_SysTick */ 00598 00599 00600 /** 00601 \ingroup CMSIS_core_register 00602 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00603 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00604 @{ 00605 */ 00606 00607 /** 00608 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00609 */ 00610 typedef struct 00611 { 00612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 00613 uint32_t RESERVED0[6U]; 00614 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00615 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00616 uint32_t RESERVED1[1U]; 00617 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00618 uint32_t RESERVED2[1U]; 00619 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00620 uint32_t RESERVED3[1U]; 00621 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00622 uint32_t RESERVED4[1U]; 00623 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 00624 uint32_t RESERVED5[1U]; 00625 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 00626 uint32_t RESERVED6[1U]; 00627 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 00628 uint32_t RESERVED7[1U]; 00629 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 00630 uint32_t RESERVED8[1U]; 00631 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 00632 uint32_t RESERVED9[1U]; 00633 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 00634 uint32_t RESERVED10[1U]; 00635 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 00636 uint32_t RESERVED11[1U]; 00637 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 00638 uint32_t RESERVED12[1U]; 00639 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 00640 uint32_t RESERVED13[1U]; 00641 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 00642 uint32_t RESERVED14[1U]; 00643 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 00644 uint32_t RESERVED15[1U]; 00645 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 00646 uint32_t RESERVED16[1U]; 00647 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 00648 uint32_t RESERVED17[1U]; 00649 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 00650 uint32_t RESERVED18[1U]; 00651 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 00652 uint32_t RESERVED19[1U]; 00653 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 00654 uint32_t RESERVED20[1U]; 00655 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 00656 uint32_t RESERVED21[1U]; 00657 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 00658 uint32_t RESERVED22[1U]; 00659 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 00660 uint32_t RESERVED23[1U]; 00661 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 00662 uint32_t RESERVED24[1U]; 00663 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 00664 uint32_t RESERVED25[1U]; 00665 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 00666 uint32_t RESERVED26[1U]; 00667 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 00668 uint32_t RESERVED27[1U]; 00669 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 00670 uint32_t RESERVED28[1U]; 00671 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 00672 uint32_t RESERVED29[1U]; 00673 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 00674 uint32_t RESERVED30[1U]; 00675 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 00676 uint32_t RESERVED31[1U]; 00677 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 00678 } DWT_Type; 00679 00680 /* DWT Control Register Definitions */ 00681 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 00682 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 00683 00684 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 00685 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 00686 00687 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 00688 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 00689 00690 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 00691 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 00692 00693 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 00694 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 00695 00696 /* DWT Comparator Function Register Definitions */ 00697 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 00698 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 00699 00700 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 00701 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 00702 00703 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 00704 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 00705 00706 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 00707 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 00708 00709 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 00710 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 00711 00712 /*@}*/ /* end of group CMSIS_DWT */ 00713 00714 00715 /** 00716 \ingroup CMSIS_core_register 00717 \defgroup CMSIS_TPI Trace Port Interface (TPI) 00718 \brief Type definitions for the Trace Port Interface (TPI) 00719 @{ 00720 */ 00721 00722 /** 00723 \brief Structure type to access the Trace Port Interface Register (TPI). 00724 */ 00725 typedef struct 00726 { 00727 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ 00728 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ 00729 uint32_t RESERVED0[2U]; 00730 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 00731 uint32_t RESERVED1[55U]; 00732 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 00733 uint32_t RESERVED2[131U]; 00734 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 00735 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 00736 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ 00737 uint32_t RESERVED3[809U]; 00738 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ 00739 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ 00740 uint32_t RESERVED4[4U]; 00741 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ 00742 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ 00743 } TPI_Type; 00744 00745 /* TPI Asynchronous Clock Prescaler Register Definitions */ 00746 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ 00747 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ 00748 00749 /* TPI Selected Pin Protocol Register Definitions */ 00750 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 00751 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 00752 00753 /* TPI Formatter and Flush Status Register Definitions */ 00754 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 00755 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 00756 00757 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 00758 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 00759 00760 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 00761 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 00762 00763 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 00764 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 00765 00766 /* TPI Formatter and Flush Control Register Definitions */ 00767 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 00768 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 00769 00770 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ 00771 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ 00772 00773 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 00774 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 00775 00776 /* TPI Periodic Synchronization Control Register Definitions */ 00777 #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ 00778 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ 00779 00780 /* TPI Software Lock Status Register Definitions */ 00781 #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ 00782 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ 00783 00784 #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ 00785 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ 00786 00787 #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ 00788 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ 00789 00790 /* TPI DEVID Register Definitions */ 00791 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 00792 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 00793 00794 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 00795 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 00796 00797 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 00798 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 00799 00800 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ 00801 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ 00802 00803 /* TPI DEVTYPE Register Definitions */ 00804 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 00805 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 00806 00807 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 00808 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 00809 00810 /*@}*/ /* end of group CMSIS_TPI */ 00811 00812 00813 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 00814 /** 00815 \ingroup CMSIS_core_register 00816 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00817 \brief Type definitions for the Memory Protection Unit (MPU) 00818 @{ 00819 */ 00820 00821 /** 00822 \brief Structure type to access the Memory Protection Unit (MPU). 00823 */ 00824 typedef struct 00825 { 00826 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00827 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00828 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 00829 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00830 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 00831 uint32_t RESERVED0[7U]; 00832 union { 00833 __IOM uint32_t MAIR[2]; 00834 struct { 00835 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 00836 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 00837 }; 00838 }; 00839 } MPU_Type; 00840 00841 #define MPU_TYPE_RALIASES 1U 00842 00843 /* MPU Type Register Definitions */ 00844 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 00845 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00846 00847 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 00848 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00849 00850 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 00851 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 00852 00853 /* MPU Control Register Definitions */ 00854 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 00855 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00856 00857 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 00858 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00859 00860 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 00861 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 00862 00863 /* MPU Region Number Register Definitions */ 00864 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 00865 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 00866 00867 /* MPU Region Base Address Register Definitions */ 00868 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 00869 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 00870 00871 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 00872 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 00873 00874 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 00875 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 00876 00877 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 00878 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 00879 00880 /* MPU Region Limit Address Register Definitions */ 00881 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 00882 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 00883 00884 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 00885 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 00886 00887 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ 00888 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ 00889 00890 /* MPU Memory Attribute Indirection Register 0 Definitions */ 00891 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 00892 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 00893 00894 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 00895 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 00896 00897 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 00898 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 00899 00900 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 00901 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 00902 00903 /* MPU Memory Attribute Indirection Register 1 Definitions */ 00904 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 00905 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 00906 00907 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 00908 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 00909 00910 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 00911 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 00912 00913 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 00914 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 00915 00916 /*@} end of group CMSIS_MPU */ 00917 #endif 00918 00919 00920 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 00921 /** 00922 \ingroup CMSIS_core_register 00923 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 00924 \brief Type definitions for the Security Attribution Unit (SAU) 00925 @{ 00926 */ 00927 00928 /** 00929 \brief Structure type to access the Security Attribution Unit (SAU). 00930 */ 00931 typedef struct 00932 { 00933 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 00934 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 00935 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 00936 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 00937 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 00938 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 00939 #endif 00940 } SAU_Type; 00941 00942 /* SAU Control Register Definitions */ 00943 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 00944 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 00945 00946 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 00947 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 00948 00949 /* SAU Type Register Definitions */ 00950 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 00951 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 00952 00953 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 00954 /* SAU Region Number Register Definitions */ 00955 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 00956 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 00957 00958 /* SAU Region Base Address Register Definitions */ 00959 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 00960 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 00961 00962 /* SAU Region Limit Address Register Definitions */ 00963 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 00964 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 00965 00966 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 00967 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 00968 00969 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 00970 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 00971 00972 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 00973 00974 /*@} end of group CMSIS_SAU */ 00975 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 00976 00977 00978 /** 00979 \ingroup CMSIS_core_register 00980 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00981 \brief Type definitions for the Core Debug Registers 00982 @{ 00983 */ 00984 00985 /** 00986 \brief Structure type to access the Core Debug Register (CoreDebug). 00987 */ 00988 typedef struct 00989 { 00990 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 00991 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 00992 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 00993 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 00994 uint32_t RESERVED4[1U]; 00995 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 00996 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 00997 } CoreDebug_Type; 00998 00999 /* Debug Halting Control and Status Register Definitions */ 01000 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01001 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01002 01003 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ 01004 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ 01005 01006 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01007 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01008 01009 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01010 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01011 01012 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01013 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01014 01015 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01016 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01017 01018 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01019 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01020 01021 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01022 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01023 01024 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01025 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01026 01027 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01028 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01029 01030 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01031 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01032 01033 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01034 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01035 01036 /* Debug Core Register Selector Register Definitions */ 01037 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01038 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01039 01040 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01041 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01042 01043 /* Debug Exception and Monitor Control Register */ 01044 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ 01045 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ 01046 01047 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01048 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01049 01050 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01051 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01052 01053 /* Debug Authentication Control Register Definitions */ 01054 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 01055 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 01056 01057 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 01058 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 01059 01060 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ 01061 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 01062 01063 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ 01064 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 01065 01066 /* Debug Security Control and Status Register Definitions */ 01067 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ 01068 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ 01069 01070 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ 01071 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ 01072 01073 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ 01074 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ 01075 01076 /*@} end of group CMSIS_CoreDebug */ 01077 01078 01079 /** 01080 \ingroup CMSIS_core_register 01081 \defgroup CMSIS_core_bitfield Core register bit field macros 01082 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01083 @{ 01084 */ 01085 01086 /** 01087 \brief Mask and shift a bit field value for use in a register bit range. 01088 \param[in] field Name of the register bit field. 01089 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01090 \return Masked and shifted value. 01091 */ 01092 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01093 01094 /** 01095 \brief Mask and shift a register value to extract a bit filed value. 01096 \param[in] field Name of the register bit field. 01097 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01098 \return Masked and shifted bit field value. 01099 */ 01100 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01101 01102 /*@} end of group CMSIS_core_bitfield */ 01103 01104 01105 /** 01106 \ingroup CMSIS_core_register 01107 \defgroup CMSIS_core_base Core Definitions 01108 \brief Definitions for base addresses, unions, and structures. 01109 @{ 01110 */ 01111 01112 /* Memory mapping of Core Hardware */ 01113 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01114 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01115 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01116 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01117 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01118 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01119 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01120 01121 01122 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01123 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01124 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01125 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01126 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01127 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ 01128 01129 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01130 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01131 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01132 #endif 01133 01134 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01135 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 01136 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 01137 #endif 01138 01139 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01140 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 01141 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ 01142 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 01143 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 01144 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 01145 01146 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 01147 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 01148 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 01149 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ 01150 01151 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01152 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 01153 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 01154 #endif 01155 01156 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01157 /*@} */ 01158 01159 01160 01161 /******************************************************************************* 01162 * Hardware Abstraction Layer 01163 Core Function Interface contains: 01164 - Core NVIC Functions 01165 - Core SysTick Functions 01166 - Core Register Access Functions 01167 ******************************************************************************/ 01168 /** 01169 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01170 */ 01171 01172 01173 01174 /* ########################## NVIC functions #################################### */ 01175 /** 01176 \ingroup CMSIS_Core_FunctionInterface 01177 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01178 \brief Functions that manage interrupts and exceptions via the NVIC. 01179 @{ 01180 */ 01181 01182 #ifdef CMSIS_NVIC_VIRTUAL 01183 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 01184 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 01185 #endif 01186 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 01187 #else 01188 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 01189 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 01190 #define NVIC_EnableIRQ __NVIC_EnableIRQ 01191 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 01192 #define NVIC_DisableIRQ __NVIC_DisableIRQ 01193 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 01194 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 01195 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 01196 #define NVIC_GetActive __NVIC_GetActive 01197 #define NVIC_SetPriority __NVIC_SetPriority 01198 #define NVIC_GetPriority __NVIC_GetPriority 01199 #define NVIC_SystemReset __NVIC_SystemReset 01200 #endif /* CMSIS_NVIC_VIRTUAL */ 01201 01202 #ifdef CMSIS_VECTAB_VIRTUAL 01203 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01204 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 01205 #endif 01206 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01207 #else 01208 #define NVIC_SetVector __NVIC_SetVector 01209 #define NVIC_GetVector __NVIC_GetVector 01210 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 01211 01212 #define NVIC_USER_IRQ_OFFSET 16 01213 01214 01215 /* Special LR values for Secure/Non-Secure call handling and exception handling */ 01216 01217 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ 01218 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ 01219 01220 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ 01221 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ 01222 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ 01223 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ 01224 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ 01225 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ 01226 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ 01227 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ 01228 01229 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ 01230 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ 01231 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ 01232 #else 01233 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ 01234 #endif 01235 01236 01237 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 01238 /* The following MACROS handle generation of the register offset and byte masks */ 01239 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 01240 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 01241 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 01242 01243 #define __NVIC_SetPriorityGrouping(X) (void)(X) 01244 #define __NVIC_GetPriorityGrouping() (0U) 01245 01246 /** 01247 \brief Enable Interrupt 01248 \details Enables a device specific interrupt in the NVIC interrupt controller. 01249 \param [in] IRQn Device specific interrupt number. 01250 \note IRQn must not be negative. 01251 */ 01252 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 01253 { 01254 if ((int32_t)(IRQn) >= 0) 01255 { 01256 __COMPILER_BARRIER(); 01257 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01258 __COMPILER_BARRIER(); 01259 } 01260 } 01261 01262 01263 /** 01264 \brief Get Interrupt Enable status 01265 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 01266 \param [in] IRQn Device specific interrupt number. 01267 \return 0 Interrupt is not enabled. 01268 \return 1 Interrupt is enabled. 01269 \note IRQn must not be negative. 01270 */ 01271 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 01272 { 01273 if ((int32_t)(IRQn) >= 0) 01274 { 01275 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01276 } 01277 else 01278 { 01279 return(0U); 01280 } 01281 } 01282 01283 01284 /** 01285 \brief Disable Interrupt 01286 \details Disables a device specific interrupt in the NVIC interrupt controller. 01287 \param [in] IRQn Device specific interrupt number. 01288 \note IRQn must not be negative. 01289 */ 01290 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 01291 { 01292 if ((int32_t)(IRQn) >= 0) 01293 { 01294 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01295 __DSB(); 01296 __ISB(); 01297 } 01298 } 01299 01300 01301 /** 01302 \brief Get Pending Interrupt 01303 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 01304 \param [in] IRQn Device specific interrupt number. 01305 \return 0 Interrupt status is not pending. 01306 \return 1 Interrupt status is pending. 01307 \note IRQn must not be negative. 01308 */ 01309 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 01310 { 01311 if ((int32_t)(IRQn) >= 0) 01312 { 01313 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01314 } 01315 else 01316 { 01317 return(0U); 01318 } 01319 } 01320 01321 01322 /** 01323 \brief Set Pending Interrupt 01324 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 01325 \param [in] IRQn Device specific interrupt number. 01326 \note IRQn must not be negative. 01327 */ 01328 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 01329 { 01330 if ((int32_t)(IRQn) >= 0) 01331 { 01332 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01333 } 01334 } 01335 01336 01337 /** 01338 \brief Clear Pending Interrupt 01339 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 01340 \param [in] IRQn Device specific interrupt number. 01341 \note IRQn must not be negative. 01342 */ 01343 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01344 { 01345 if ((int32_t)(IRQn) >= 0) 01346 { 01347 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01348 } 01349 } 01350 01351 01352 /** 01353 \brief Get Active Interrupt 01354 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 01355 \param [in] IRQn Device specific interrupt number. 01356 \return 0 Interrupt status is not active. 01357 \return 1 Interrupt status is active. 01358 \note IRQn must not be negative. 01359 */ 01360 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 01361 { 01362 if ((int32_t)(IRQn) >= 0) 01363 { 01364 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01365 } 01366 else 01367 { 01368 return(0U); 01369 } 01370 } 01371 01372 01373 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01374 /** 01375 \brief Get Interrupt Target State 01376 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01377 \param [in] IRQn Device specific interrupt number. 01378 \return 0 if interrupt is assigned to Secure 01379 \return 1 if interrupt is assigned to Non Secure 01380 \note IRQn must not be negative. 01381 */ 01382 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 01383 { 01384 if ((int32_t)(IRQn) >= 0) 01385 { 01386 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01387 } 01388 else 01389 { 01390 return(0U); 01391 } 01392 } 01393 01394 01395 /** 01396 \brief Set Interrupt Target State 01397 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01398 \param [in] IRQn Device specific interrupt number. 01399 \return 0 if interrupt is assigned to Secure 01400 1 if interrupt is assigned to Non Secure 01401 \note IRQn must not be negative. 01402 */ 01403 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 01404 { 01405 if ((int32_t)(IRQn) >= 0) 01406 { 01407 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 01408 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01409 } 01410 else 01411 { 01412 return(0U); 01413 } 01414 } 01415 01416 01417 /** 01418 \brief Clear Interrupt Target State 01419 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01420 \param [in] IRQn Device specific interrupt number. 01421 \return 0 if interrupt is assigned to Secure 01422 1 if interrupt is assigned to Non Secure 01423 \note IRQn must not be negative. 01424 */ 01425 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 01426 { 01427 if ((int32_t)(IRQn) >= 0) 01428 { 01429 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 01430 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01431 } 01432 else 01433 { 01434 return(0U); 01435 } 01436 } 01437 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01438 01439 01440 /** 01441 \brief Set Interrupt Priority 01442 \details Sets the priority of a device specific interrupt or a processor exception. 01443 The interrupt number can be positive to specify a device specific interrupt, 01444 or negative to specify a processor exception. 01445 \param [in] IRQn Interrupt number. 01446 \param [in] priority Priority to set. 01447 \note The priority cannot be set for every processor exception. 01448 */ 01449 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01450 { 01451 if ((int32_t)(IRQn) >= 0) 01452 { 01453 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01454 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01455 } 01456 else 01457 { 01458 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01459 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01460 } 01461 } 01462 01463 01464 /** 01465 \brief Get Interrupt Priority 01466 \details Reads the priority of a device specific interrupt or a processor exception. 01467 The interrupt number can be positive to specify a device specific interrupt, 01468 or negative to specify a processor exception. 01469 \param [in] IRQn Interrupt number. 01470 \return Interrupt Priority. 01471 Value is aligned automatically to the implemented priority bits of the microcontroller. 01472 */ 01473 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 01474 { 01475 01476 if ((int32_t)(IRQn) >= 0) 01477 { 01478 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01479 } 01480 else 01481 { 01482 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01483 } 01484 } 01485 01486 01487 /** 01488 \brief Encode Priority 01489 \details Encodes the priority for an interrupt with the given priority group, 01490 preemptive priority value, and subpriority value. 01491 In case of a conflict between priority grouping and available 01492 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01493 \param [in] PriorityGroup Used priority group. 01494 \param [in] PreemptPriority Preemptive priority value (starting from 0). 01495 \param [in] SubPriority Subpriority value (starting from 0). 01496 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 01497 */ 01498 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01499 { 01500 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01501 uint32_t PreemptPriorityBits; 01502 uint32_t SubPriorityBits; 01503 01504 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01505 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01506 01507 return ( 01508 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 01509 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 01510 ); 01511 } 01512 01513 01514 /** 01515 \brief Decode Priority 01516 \details Decodes an interrupt priority value with a given priority group to 01517 preemptive priority value and subpriority value. 01518 In case of a conflict between priority grouping and available 01519 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 01520 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 01521 \param [in] PriorityGroup Used priority group. 01522 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 01523 \param [out] pSubPriority Subpriority value (starting from 0). 01524 */ 01525 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 01526 { 01527 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01528 uint32_t PreemptPriorityBits; 01529 uint32_t SubPriorityBits; 01530 01531 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01532 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01533 01534 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 01535 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 01536 } 01537 01538 01539 /** 01540 \brief Set Interrupt Vector 01541 \details Sets an interrupt vector in SRAM based interrupt vector table. 01542 The interrupt number can be positive to specify a device specific interrupt, 01543 or negative to specify a processor exception. 01544 VTOR must been relocated to SRAM before. 01545 If VTOR is not present address 0 must be mapped to SRAM. 01546 \param [in] IRQn Interrupt number 01547 \param [in] vector Address of interrupt handler function 01548 */ 01549 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 01550 { 01551 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 01552 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01553 #else 01554 uint32_t *vectors = (uint32_t *)0x0U; 01555 #endif 01556 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 01557 __DSB(); 01558 } 01559 01560 01561 /** 01562 \brief Get Interrupt Vector 01563 \details Reads an interrupt vector from interrupt vector table. 01564 The interrupt number can be positive to specify a device specific interrupt, 01565 or negative to specify a processor exception. 01566 \param [in] IRQn Interrupt number. 01567 \return Address of interrupt handler function 01568 */ 01569 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 01570 { 01571 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 01572 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01573 #else 01574 uint32_t *vectors = (uint32_t *)0x0U; 01575 #endif 01576 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 01577 } 01578 01579 01580 /** 01581 \brief System Reset 01582 \details Initiates a system reset request to reset the MCU. 01583 */ 01584 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 01585 { 01586 __DSB(); /* Ensure all outstanding memory accesses included 01587 buffered write are completed before reset */ 01588 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01589 SCB_AIRCR_SYSRESETREQ_Msk); 01590 __DSB(); /* Ensure completion of memory access */ 01591 01592 for(;;) /* wait until reset */ 01593 { 01594 __NOP(); 01595 } 01596 } 01597 01598 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01599 /** 01600 \brief Enable Interrupt (non-secure) 01601 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 01602 \param [in] IRQn Device specific interrupt number. 01603 \note IRQn must not be negative. 01604 */ 01605 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 01606 { 01607 if ((int32_t)(IRQn) >= 0) 01608 { 01609 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01610 } 01611 } 01612 01613 01614 /** 01615 \brief Get Interrupt Enable status (non-secure) 01616 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 01617 \param [in] IRQn Device specific interrupt number. 01618 \return 0 Interrupt is not enabled. 01619 \return 1 Interrupt is enabled. 01620 \note IRQn must not be negative. 01621 */ 01622 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 01623 { 01624 if ((int32_t)(IRQn) >= 0) 01625 { 01626 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01627 } 01628 else 01629 { 01630 return(0U); 01631 } 01632 } 01633 01634 01635 /** 01636 \brief Disable Interrupt (non-secure) 01637 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 01638 \param [in] IRQn Device specific interrupt number. 01639 \note IRQn must not be negative. 01640 */ 01641 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 01642 { 01643 if ((int32_t)(IRQn) >= 0) 01644 { 01645 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01646 } 01647 } 01648 01649 01650 /** 01651 \brief Get Pending Interrupt (non-secure) 01652 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 01653 \param [in] IRQn Device specific interrupt number. 01654 \return 0 Interrupt status is not pending. 01655 \return 1 Interrupt status is pending. 01656 \note IRQn must not be negative. 01657 */ 01658 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 01659 { 01660 if ((int32_t)(IRQn) >= 0) 01661 { 01662 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01663 } 01664 else 01665 { 01666 return(0U); 01667 } 01668 } 01669 01670 01671 /** 01672 \brief Set Pending Interrupt (non-secure) 01673 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 01674 \param [in] IRQn Device specific interrupt number. 01675 \note IRQn must not be negative. 01676 */ 01677 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 01678 { 01679 if ((int32_t)(IRQn) >= 0) 01680 { 01681 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01682 } 01683 } 01684 01685 01686 /** 01687 \brief Clear Pending Interrupt (non-secure) 01688 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 01689 \param [in] IRQn Device specific interrupt number. 01690 \note IRQn must not be negative. 01691 */ 01692 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 01693 { 01694 if ((int32_t)(IRQn) >= 0) 01695 { 01696 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01697 } 01698 } 01699 01700 01701 /** 01702 \brief Get Active Interrupt (non-secure) 01703 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 01704 \param [in] IRQn Device specific interrupt number. 01705 \return 0 Interrupt status is not active. 01706 \return 1 Interrupt status is active. 01707 \note IRQn must not be negative. 01708 */ 01709 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 01710 { 01711 if ((int32_t)(IRQn) >= 0) 01712 { 01713 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01714 } 01715 else 01716 { 01717 return(0U); 01718 } 01719 } 01720 01721 01722 /** 01723 \brief Set Interrupt Priority (non-secure) 01724 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 01725 The interrupt number can be positive to specify a device specific interrupt, 01726 or negative to specify a processor exception. 01727 \param [in] IRQn Interrupt number. 01728 \param [in] priority Priority to set. 01729 \note The priority cannot be set for every non-secure processor exception. 01730 */ 01731 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 01732 { 01733 if ((int32_t)(IRQn) >= 0) 01734 { 01735 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01736 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01737 } 01738 else 01739 { 01740 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01741 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01742 } 01743 } 01744 01745 01746 /** 01747 \brief Get Interrupt Priority (non-secure) 01748 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 01749 The interrupt number can be positive to specify a device specific interrupt, 01750 or negative to specify a processor exception. 01751 \param [in] IRQn Interrupt number. 01752 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 01753 */ 01754 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 01755 { 01756 01757 if ((int32_t)(IRQn) >= 0) 01758 { 01759 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01760 } 01761 else 01762 { 01763 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01764 } 01765 } 01766 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 01767 01768 /*@} end of CMSIS_Core_NVICFunctions */ 01769 01770 /* ########################## MPU functions #################################### */ 01771 01772 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01773 01774 #include "mpu_armv8.h" 01775 01776 #endif 01777 01778 /* ########################## FPU functions #################################### */ 01779 /** 01780 \ingroup CMSIS_Core_FunctionInterface 01781 \defgroup CMSIS_Core_FpuFunctions FPU Functions 01782 \brief Function that provides FPU type. 01783 @{ 01784 */ 01785 01786 /** 01787 \brief get FPU type 01788 \details returns the FPU type 01789 \returns 01790 - \b 0: No FPU 01791 - \b 1: Single precision FPU 01792 - \b 2: Double + Single precision FPU 01793 */ 01794 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 01795 { 01796 return 0U; /* No FPU */ 01797 } 01798 01799 01800 /*@} end of CMSIS_Core_FpuFunctions */ 01801 01802 01803 01804 /* ########################## SAU functions #################################### */ 01805 /** 01806 \ingroup CMSIS_Core_FunctionInterface 01807 \defgroup CMSIS_Core_SAUFunctions SAU Functions 01808 \brief Functions that configure the SAU. 01809 @{ 01810 */ 01811 01812 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01813 01814 /** 01815 \brief Enable SAU 01816 \details Enables the Security Attribution Unit (SAU). 01817 */ 01818 __STATIC_INLINE void TZ_SAU_Enable(void) 01819 { 01820 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 01821 } 01822 01823 01824 01825 /** 01826 \brief Disable SAU 01827 \details Disables the Security Attribution Unit (SAU). 01828 */ 01829 __STATIC_INLINE void TZ_SAU_Disable(void) 01830 { 01831 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 01832 } 01833 01834 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01835 01836 /*@} end of CMSIS_Core_SAUFunctions */ 01837 01838 01839 01840 01841 /* ################################## SysTick function ############################################ */ 01842 /** 01843 \ingroup CMSIS_Core_FunctionInterface 01844 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 01845 \brief Functions that configure the System. 01846 @{ 01847 */ 01848 01849 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 01850 01851 /** 01852 \brief System Tick Configuration 01853 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 01854 Counter is in free running mode to generate periodic interrupts. 01855 \param [in] ticks Number of ticks between two interrupts. 01856 \return 0 Function succeeded. 01857 \return 1 Function failed. 01858 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01859 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 01860 must contain a vendor-specific implementation of this function. 01861 */ 01862 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01863 { 01864 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 01865 { 01866 return (1UL); /* Reload value impossible */ 01867 } 01868 01869 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01870 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01871 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 01872 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01873 SysTick_CTRL_TICKINT_Msk | 01874 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01875 return (0UL); /* Function successful */ 01876 } 01877 01878 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01879 /** 01880 \brief System Tick Configuration (non-secure) 01881 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 01882 Counter is in free running mode to generate periodic interrupts. 01883 \param [in] ticks Number of ticks between two interrupts. 01884 \return 0 Function succeeded. 01885 \return 1 Function failed. 01886 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01887 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 01888 must contain a vendor-specific implementation of this function. 01889 01890 */ 01891 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 01892 { 01893 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 01894 { 01895 return (1UL); /* Reload value impossible */ 01896 } 01897 01898 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01899 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01900 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 01901 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01902 SysTick_CTRL_TICKINT_Msk | 01903 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01904 return (0UL); /* Function successful */ 01905 } 01906 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01907 01908 #endif 01909 01910 /*@} end of CMSIS_Core_SysTickFunctions */ 01911 01912 01913 01914 01915 #ifdef __cplusplus 01916 } 01917 #endif 01918 01919 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */ 01920 01921 #endif /* __CMSIS_GENERIC */
Generated on Tue Jul 12 2022 15:37:14 by
1.7.2