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core_armv81mml.h
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00001 /**************************************************************************//** 00002 * @file core_armv81mml.h 00003 * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File 00004 * @version V1.2.0 00005 * @date 21. October 2019 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2018-2019 Arm Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__clang__) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_ARMV81MML_H_GENERIC 00032 #define __CORE_ARMV81MML_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_ARMV81MML 00060 @{ 00061 */ 00062 00063 #include "cmsis_version.h" 00064 00065 #define __ARM_ARCH_8M_MAIN__ 1 // patching for now 00066 /* CMSIS ARMV81MML definitions */ 00067 #define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 00068 #define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 00069 #define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ 00070 __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 00071 00072 #define __CORTEX_M (81U) /*!< Cortex-M Core */ 00073 00074 #if defined ( __CC_ARM ) 00075 #error Legacy Arm Compiler does not support Armv8.1-M target architecture. 00076 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00077 #if defined __ARM_FP 00078 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00079 #define __FPU_USED 1U 00080 #else 00081 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00082 #define __FPU_USED 0U 00083 #endif 00084 #else 00085 #define __FPU_USED 0U 00086 #endif 00087 00088 #if defined(__ARM_FEATURE_DSP) 00089 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) 00090 #define __DSP_USED 1U 00091 #else 00092 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 00093 #define __DSP_USED 0U 00094 #endif 00095 #else 00096 #define __DSP_USED 0U 00097 #endif 00098 00099 #if defined(__ARM_FEATURE_MVE) 00100 #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U) 00101 #define __MVE_USED 1U 00102 #else 00103 #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)" 00104 #define __MVE_USED 0U 00105 #endif 00106 #else 00107 #define __MVE_USED 0U 00108 #endif 00109 00110 #elif defined ( __GNUC__ ) 00111 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00112 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00113 #define __FPU_USED 1U 00114 #else 00115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00116 #define __FPU_USED 0U 00117 #endif 00118 #else 00119 #define __FPU_USED 0U 00120 #endif 00121 00122 #if defined(__ARM_FEATURE_DSP) 00123 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) 00124 #define __DSP_USED 1U 00125 #else 00126 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 00127 #define __DSP_USED 0U 00128 #endif 00129 #else 00130 #define __DSP_USED 0U 00131 #endif 00132 00133 #if defined(__ARM_FEATURE_MVE) 00134 #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U) 00135 #define __MVE_USED 1U 00136 #else 00137 #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)" 00138 #define __MVE_USED 0U 00139 #endif 00140 #else 00141 #define __MVE_USED 0U 00142 #endif 00143 00144 #elif defined ( __ICCARM__ ) 00145 #if defined __ARMVFP__ 00146 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00147 #define __FPU_USED 1U 00148 #else 00149 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00150 #define __FPU_USED 0U 00151 #endif 00152 #else 00153 #define __FPU_USED 0U 00154 #endif 00155 00156 #if defined(__ARM_FEATURE_DSP) 00157 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) 00158 #define __DSP_USED 1U 00159 #else 00160 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 00161 #define __DSP_USED 0U 00162 #endif 00163 #else 00164 #define __DSP_USED 0U 00165 #endif 00166 00167 #if defined(__ARM_FEATURE_MVE) 00168 #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U) 00169 #define __MVE_USED 1U 00170 #else 00171 #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)" 00172 #define __MVE_USED 0U 00173 #endif 00174 #else 00175 #define __MVE_USED 0U 00176 #endif 00177 00178 #elif defined ( __TI_ARM__ ) 00179 #if defined __TI_VFP_SUPPORT__ 00180 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00181 #define __FPU_USED 1U 00182 #else 00183 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00184 #define __FPU_USED 0U 00185 #endif 00186 #else 00187 #define __FPU_USED 0U 00188 #endif 00189 00190 #elif defined ( __TASKING__ ) 00191 #if defined __FPU_VFP__ 00192 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00193 #define __FPU_USED 1U 00194 #else 00195 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00196 #define __FPU_USED 0U 00197 #endif 00198 #else 00199 #define __FPU_USED 0U 00200 #endif 00201 00202 #elif defined ( __CSMC__ ) 00203 #if ( __CSMC__ & 0x400U) 00204 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00205 #define __FPU_USED 1U 00206 #else 00207 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00208 #define __FPU_USED 0U 00209 #endif 00210 #else 00211 #define __FPU_USED 0U 00212 #endif 00213 00214 #endif 00215 00216 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00217 00218 00219 #ifdef __cplusplus 00220 } 00221 #endif 00222 00223 #endif /* __CORE_ARMV81MML_H_GENERIC */ 00224 00225 #ifndef __CMSIS_GENERIC 00226 00227 #ifndef __CORE_ARMV81MML_H_DEPENDANT 00228 #define __CORE_ARMV81MML_H_DEPENDANT 00229 00230 #ifdef __cplusplus 00231 extern "C" { 00232 #endif 00233 00234 /* check device defines and use defaults */ 00235 #if defined __CHECK_DEVICE_DEFINES 00236 #ifndef __ARMv81MML_REV 00237 #define __ARMv81MML_REV 0x0000U 00238 #warning "__ARMv81MML_REV not defined in device header file; using default!" 00239 #endif 00240 00241 #ifndef __FPU_PRESENT 00242 #define __FPU_PRESENT 0U 00243 #warning "__FPU_PRESENT not defined in device header file; using default!" 00244 #endif 00245 00246 #ifndef __MPU_PRESENT 00247 #define __MPU_PRESENT 0U 00248 #warning "__MPU_PRESENT not defined in device header file; using default!" 00249 #endif 00250 00251 #ifndef __SAUREGION_PRESENT 00252 #define __SAUREGION_PRESENT 0U 00253 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 00254 #endif 00255 00256 #ifndef __DSP_PRESENT 00257 #define __DSP_PRESENT 0U 00258 #warning "__DSP_PRESENT not defined in device header file; using default!" 00259 #endif 00260 00261 #ifndef __MVE_PRESENT 00262 #define __MVE_PRESENT 0U 00263 #warning "__MVE_PRESENT not defined in device header file; using default!" 00264 #endif 00265 00266 #ifndef __NVIC_PRIO_BITS 00267 #define __NVIC_PRIO_BITS 3U 00268 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00269 #endif 00270 00271 #ifndef __Vendor_SysTickConfig 00272 #define __Vendor_SysTickConfig 0U 00273 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00274 #endif 00275 #endif 00276 00277 /* IO definitions (access restrictions to peripheral registers) */ 00278 /** 00279 \defgroup CMSIS_glob_defs CMSIS Global Defines 00280 00281 <strong>IO Type Qualifiers</strong> are used 00282 \li to specify the access to peripheral variables. 00283 \li for automatic generation of peripheral register debug information. 00284 */ 00285 #ifdef __cplusplus 00286 #define __I volatile /*!< Defines 'read only' permissions */ 00287 #else 00288 #define __I volatile const /*!< Defines 'read only' permissions */ 00289 #endif 00290 #define __O volatile /*!< Defines 'write only' permissions */ 00291 #define __IO volatile /*!< Defines 'read / write' permissions */ 00292 00293 /* following defines should be used for structure members */ 00294 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00295 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00296 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00297 00298 /*@} end of group ARMv81MML */ 00299 00300 00301 00302 /******************************************************************************* 00303 * Register Abstraction 00304 Core Register contain: 00305 - Core Register 00306 - Core NVIC Register 00307 - Core SCB Register 00308 - Core SysTick Register 00309 - Core Debug Register 00310 - Core MPU Register 00311 - Core SAU Register 00312 - Core FPU Register 00313 ******************************************************************************/ 00314 /** 00315 \defgroup CMSIS_core_register Defines and Type Definitions 00316 \brief Type definitions and defines for Cortex-M processor based devices. 00317 */ 00318 00319 /** 00320 \ingroup CMSIS_core_register 00321 \defgroup CMSIS_CORE Status and Control Registers 00322 \brief Core Register type definitions. 00323 @{ 00324 */ 00325 00326 /** 00327 \brief Union type to access the Application Program Status Register (APSR). 00328 */ 00329 typedef union 00330 { 00331 struct 00332 { 00333 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00334 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00335 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00336 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00337 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00338 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00339 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00340 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00341 } b; /*!< Structure used for bit access */ 00342 uint32_t w; /*!< Type used for word access */ 00343 } APSR_Type; 00344 00345 /* APSR Register Definitions */ 00346 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00347 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00348 00349 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00350 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00351 00352 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00353 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00354 00355 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00356 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00357 00358 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 00359 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 00360 00361 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 00362 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 00363 00364 00365 /** 00366 \brief Union type to access the Interrupt Program Status Register (IPSR). 00367 */ 00368 typedef union 00369 { 00370 struct 00371 { 00372 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00373 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00374 } b; /*!< Structure used for bit access */ 00375 uint32_t w; /*!< Type used for word access */ 00376 } IPSR_Type; 00377 00378 /* IPSR Register Definitions */ 00379 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00380 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00381 00382 00383 /** 00384 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00385 */ 00386 typedef union 00387 { 00388 struct 00389 { 00390 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00391 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00392 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00393 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00394 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00395 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00396 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00397 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00398 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00399 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00400 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00401 } b; /*!< Structure used for bit access */ 00402 uint32_t w; /*!< Type used for word access */ 00403 } xPSR_Type; 00404 00405 /* xPSR Register Definitions */ 00406 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00407 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00408 00409 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00410 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00411 00412 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00413 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00414 00415 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00416 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00417 00418 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 00419 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 00420 00421 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ 00422 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ 00423 00424 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00425 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00426 00427 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 00428 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 00429 00430 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00431 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00432 00433 00434 /** 00435 \brief Union type to access the Control Registers (CONTROL). 00436 */ 00437 typedef union 00438 { 00439 struct 00440 { 00441 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00442 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ 00443 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ 00444 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ 00445 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ 00446 } b; /*!< Structure used for bit access */ 00447 uint32_t w; /*!< Type used for word access */ 00448 } CONTROL_Type; 00449 00450 /* CONTROL Register Definitions */ 00451 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ 00452 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ 00453 00454 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 00455 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 00456 00457 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00458 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00459 00460 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00461 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00462 00463 /*@} end of group CMSIS_CORE */ 00464 00465 00466 /** 00467 \ingroup CMSIS_core_register 00468 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00469 \brief Type definitions for the NVIC Registers 00470 @{ 00471 */ 00472 00473 /** 00474 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00475 */ 00476 typedef struct 00477 { 00478 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00479 uint32_t RESERVED0[16U]; 00480 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00481 uint32_t RSERVED1[16U]; 00482 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00483 uint32_t RESERVED2[16U]; 00484 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00485 uint32_t RESERVED3[16U]; 00486 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00487 uint32_t RESERVED4[16U]; 00488 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 00489 uint32_t RESERVED5[16U]; 00490 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00491 uint32_t RESERVED6[580U]; 00492 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00493 } NVIC_Type; 00494 00495 /* Software Triggered Interrupt Register Definitions */ 00496 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 00497 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 00498 00499 /*@} end of group CMSIS_NVIC */ 00500 00501 00502 /** 00503 \ingroup CMSIS_core_register 00504 \defgroup CMSIS_SCB System Control Block (SCB) 00505 \brief Type definitions for the System Control Block Registers 00506 @{ 00507 */ 00508 00509 /** 00510 \brief Structure type to access the System Control Block (SCB). 00511 */ 00512 typedef struct 00513 { 00514 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00515 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00516 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00517 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00518 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00519 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00520 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00521 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00522 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00523 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00524 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00525 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00526 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00527 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00528 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00529 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00530 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00531 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00532 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00533 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 00534 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 00535 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 00536 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 00537 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00538 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ 00539 uint32_t RESERVED3[92U]; 00540 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 00541 __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ 00542 uint32_t RESERVED4[14U]; 00543 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ 00544 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ 00545 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ 00546 uint32_t RESERVED5[1U]; 00547 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 00548 uint32_t RESERVED6[1U]; 00549 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 00550 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 00551 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 00552 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 00553 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 00554 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 00555 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ 00556 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ 00557 __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ 00558 } SCB_Type; 00559 00560 /* SCB CPUID Register Definitions */ 00561 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00562 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00563 00564 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00565 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00566 00567 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00568 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00569 00570 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00571 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00572 00573 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00574 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00575 00576 /* SCB Interrupt Control State Register Definitions */ 00577 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 00578 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 00579 00580 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ 00581 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ 00582 00583 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 00584 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 00585 00586 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00587 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00588 00589 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00590 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00591 00592 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00593 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00594 00595 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00596 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00597 00598 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 00599 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 00600 00601 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00602 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00603 00604 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00605 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00606 00607 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00608 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00609 00610 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00611 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00612 00613 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00614 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00615 00616 /* SCB Vector Table Offset Register Definitions */ 00617 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00618 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00619 00620 /* SCB Application Interrupt and Reset Control Register Definitions */ 00621 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00622 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00623 00624 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00625 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00626 00627 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00628 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00629 00630 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 00631 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 00632 00633 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 00634 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 00635 00636 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 00637 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00638 00639 #define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ 00640 #define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ 00641 00642 #define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ 00643 #define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ 00644 00645 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 00646 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 00647 00648 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00649 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00650 00651 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00652 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00653 00654 /* SCB System Control Register Definitions */ 00655 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00656 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00657 00658 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 00659 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 00660 00661 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00662 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00663 00664 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00665 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00666 00667 /* SCB Configuration Control Register Definitions */ 00668 #define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ 00669 #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ 00670 00671 #define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ 00672 #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ 00673 00674 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 00675 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 00676 00677 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 00678 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 00679 00680 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 00681 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 00682 00683 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 00684 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 00685 00686 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00687 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00688 00689 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00690 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00691 00692 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00693 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00694 00695 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00696 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00697 00698 /* SCB System Handler Control and State Register Definitions */ 00699 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 00700 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 00701 00702 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ 00703 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ 00704 00705 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ 00706 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ 00707 00708 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 00709 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00710 00711 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 00712 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00713 00714 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 00715 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00716 00717 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00718 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00719 00720 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00721 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00722 00723 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00724 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00725 00726 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 00727 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00728 00729 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00730 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00731 00732 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00733 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00734 00735 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 00736 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00737 00738 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00739 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00740 00741 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 00742 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 00743 00744 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ 00745 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ 00746 00747 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 00748 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00749 00750 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 00751 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 00752 00753 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 00754 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00755 00756 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 00757 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00758 00759 /* SCB Configurable Fault Status Register Definitions */ 00760 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 00761 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00762 00763 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 00764 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00765 00766 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00767 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00768 00769 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 00770 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 00771 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 00772 00773 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ 00774 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ 00775 00776 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 00777 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 00778 00779 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 00780 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 00781 00782 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 00783 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 00784 00785 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 00786 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 00787 00788 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 00789 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 00790 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 00791 00792 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ 00793 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ 00794 00795 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 00796 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 00797 00798 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 00799 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 00800 00801 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 00802 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 00803 00804 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 00805 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 00806 00807 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 00808 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 00809 00810 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 00811 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 00812 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 00813 00814 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 00815 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 00816 00817 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ 00818 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ 00819 00820 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 00821 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 00822 00823 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 00824 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 00825 00826 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 00827 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 00828 00829 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 00830 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 00831 00832 /* SCB Hard Fault Status Register Definitions */ 00833 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 00834 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00835 00836 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 00837 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00838 00839 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 00840 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00841 00842 /* SCB Debug Fault Status Register Definitions */ 00843 #define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ 00844 #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ 00845 00846 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 00847 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00848 00849 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 00850 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00851 00852 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 00853 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00854 00855 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 00856 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00857 00858 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 00859 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 00860 00861 /* SCB Non-Secure Access Control Register Definitions */ 00862 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ 00863 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ 00864 00865 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ 00866 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ 00867 00868 #define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ 00869 #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ 00870 00871 #define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ 00872 #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ 00873 00874 #define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ 00875 #define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ 00876 00877 #define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ 00878 #define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ 00879 00880 #define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ 00881 #define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ 00882 00883 #define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ 00884 #define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ 00885 00886 #define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ 00887 #define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ 00888 00889 #define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ 00890 #define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ 00891 00892 /* SCB Debug Feature Register 0 Definitions */ 00893 #define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ 00894 #define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ 00895 00896 #define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ 00897 #define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ 00898 00899 /* SCB Cache Level ID Register Definitions */ 00900 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ 00901 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ 00902 00903 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ 00904 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ 00905 00906 /* SCB Cache Type Register Definitions */ 00907 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ 00908 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ 00909 00910 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ 00911 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ 00912 00913 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ 00914 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ 00915 00916 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ 00917 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ 00918 00919 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ 00920 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ 00921 00922 /* SCB Cache Size ID Register Definitions */ 00923 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 00924 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 00925 00926 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 00927 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 00928 00929 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 00930 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 00931 00932 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 00933 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 00934 00935 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ 00936 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ 00937 00938 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ 00939 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ 00940 00941 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ 00942 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ 00943 00944 /* SCB Cache Size Selection Register Definitions */ 00945 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ 00946 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ 00947 00948 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ 00949 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ 00950 00951 /* SCB Software Triggered Interrupt Register Definitions */ 00952 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ 00953 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ 00954 00955 /* SCB RAS Fault Status Register Definitions */ 00956 #define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ 00957 #define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ 00958 00959 #define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ 00960 #define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ 00961 00962 #define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ 00963 #define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ 00964 00965 /* SCB D-Cache Invalidate by Set-way Register Definitions */ 00966 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ 00967 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ 00968 00969 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ 00970 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ 00971 00972 /* SCB D-Cache Clean by Set-way Register Definitions */ 00973 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ 00974 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ 00975 00976 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ 00977 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ 00978 00979 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ 00980 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ 00981 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ 00982 00983 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ 00984 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ 00985 00986 /*@} end of group CMSIS_SCB */ 00987 00988 00989 /** 00990 \ingroup CMSIS_core_register 00991 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00992 \brief Type definitions for the System Control and ID Register not in the SCB 00993 @{ 00994 */ 00995 00996 /** 00997 \brief Structure type to access the System Control and ID Register not in the SCB. 00998 */ 00999 typedef struct 01000 { 01001 uint32_t RESERVED0[1U]; 01002 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 01003 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 01004 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ 01005 } SCnSCB_Type; 01006 01007 /* Interrupt Controller Type Register Definitions */ 01008 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 01009 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 01010 01011 /*@} end of group CMSIS_SCnotSCB */ 01012 01013 01014 /** 01015 \ingroup CMSIS_core_register 01016 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 01017 \brief Type definitions for the System Timer Registers. 01018 @{ 01019 */ 01020 01021 /** 01022 \brief Structure type to access the System Timer (SysTick). 01023 */ 01024 typedef struct 01025 { 01026 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 01027 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 01028 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 01029 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 01030 } SysTick_Type; 01031 01032 /* SysTick Control / Status Register Definitions */ 01033 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 01034 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 01035 01036 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 01037 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 01038 01039 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 01040 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 01041 01042 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 01043 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 01044 01045 /* SysTick Reload Register Definitions */ 01046 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 01047 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 01048 01049 /* SysTick Current Register Definitions */ 01050 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 01051 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 01052 01053 /* SysTick Calibration Register Definitions */ 01054 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 01055 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 01056 01057 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 01058 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 01059 01060 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 01061 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 01062 01063 /*@} end of group CMSIS_SysTick */ 01064 01065 01066 /** 01067 \ingroup CMSIS_core_register 01068 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 01069 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 01070 @{ 01071 */ 01072 01073 /** 01074 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 01075 */ 01076 typedef struct 01077 { 01078 __OM union 01079 { 01080 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 01081 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 01082 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 01083 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 01084 uint32_t RESERVED0[864U]; 01085 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 01086 uint32_t RESERVED1[15U]; 01087 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 01088 uint32_t RESERVED2[15U]; 01089 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 01090 uint32_t RESERVED3[32U]; 01091 uint32_t RESERVED4[43U]; 01092 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 01093 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 01094 uint32_t RESERVED5[1U]; 01095 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ 01096 uint32_t RESERVED6[3U]; 01097 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ 01098 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 01099 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 01100 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 01101 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 01102 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 01103 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 01104 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 01105 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 01106 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 01107 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 01108 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 01109 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 01110 } ITM_Type; 01111 01112 /* ITM Stimulus Port Register Definitions */ 01113 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ 01114 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ 01115 01116 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ 01117 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ 01118 01119 /* ITM Trace Privilege Register Definitions */ 01120 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 01121 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 01122 01123 /* ITM Trace Control Register Definitions */ 01124 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 01125 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 01126 01127 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ 01128 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ 01129 01130 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 01131 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 01132 01133 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ 01134 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ 01135 01136 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ 01137 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ 01138 01139 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 01140 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 01141 01142 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 01143 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 01144 01145 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 01146 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 01147 01148 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 01149 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 01150 01151 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 01152 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 01153 01154 /* ITM Lock Status Register Definitions */ 01155 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 01156 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 01157 01158 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 01159 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 01160 01161 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 01162 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 01163 01164 /*@}*/ /* end of group CMSIS_ITM */ 01165 01166 01167 /** 01168 \ingroup CMSIS_core_register 01169 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 01170 \brief Type definitions for the Data Watchpoint and Trace (DWT) 01171 @{ 01172 */ 01173 01174 /** 01175 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 01176 */ 01177 typedef struct 01178 { 01179 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 01180 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 01181 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 01182 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 01183 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 01184 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 01185 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 01186 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 01187 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 01188 uint32_t RESERVED1[1U]; 01189 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 01190 uint32_t RESERVED2[1U]; 01191 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 01192 uint32_t RESERVED3[1U]; 01193 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 01194 uint32_t RESERVED4[1U]; 01195 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 01196 uint32_t RESERVED5[1U]; 01197 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 01198 uint32_t RESERVED6[1U]; 01199 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 01200 uint32_t RESERVED7[1U]; 01201 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 01202 uint32_t RESERVED8[1U]; 01203 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 01204 uint32_t RESERVED9[1U]; 01205 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 01206 uint32_t RESERVED10[1U]; 01207 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 01208 uint32_t RESERVED11[1U]; 01209 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 01210 uint32_t RESERVED12[1U]; 01211 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 01212 uint32_t RESERVED13[1U]; 01213 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 01214 uint32_t RESERVED14[1U]; 01215 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 01216 uint32_t RESERVED15[1U]; 01217 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 01218 uint32_t RESERVED16[1U]; 01219 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 01220 uint32_t RESERVED17[1U]; 01221 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 01222 uint32_t RESERVED18[1U]; 01223 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 01224 uint32_t RESERVED19[1U]; 01225 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 01226 uint32_t RESERVED20[1U]; 01227 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 01228 uint32_t RESERVED21[1U]; 01229 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 01230 uint32_t RESERVED22[1U]; 01231 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 01232 uint32_t RESERVED23[1U]; 01233 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 01234 uint32_t RESERVED24[1U]; 01235 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 01236 uint32_t RESERVED25[1U]; 01237 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 01238 uint32_t RESERVED26[1U]; 01239 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 01240 uint32_t RESERVED27[1U]; 01241 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 01242 uint32_t RESERVED28[1U]; 01243 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 01244 uint32_t RESERVED29[1U]; 01245 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 01246 uint32_t RESERVED30[1U]; 01247 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 01248 uint32_t RESERVED31[1U]; 01249 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 01250 uint32_t RESERVED32[934U]; 01251 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 01252 uint32_t RESERVED33[1U]; 01253 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ 01254 } DWT_Type; 01255 01256 /* DWT Control Register Definitions */ 01257 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 01258 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 01259 01260 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 01261 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 01262 01263 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 01264 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 01265 01266 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 01267 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 01268 01269 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 01270 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 01271 01272 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ 01273 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ 01274 01275 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 01276 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 01277 01278 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 01279 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 01280 01281 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 01282 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 01283 01284 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 01285 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 01286 01287 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 01288 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 01289 01290 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 01291 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 01292 01293 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 01294 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 01295 01296 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 01297 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 01298 01299 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 01300 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 01301 01302 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 01303 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 01304 01305 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 01306 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 01307 01308 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 01309 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 01310 01311 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 01312 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 01313 01314 /* DWT CPI Count Register Definitions */ 01315 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 01316 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 01317 01318 /* DWT Exception Overhead Count Register Definitions */ 01319 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 01320 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 01321 01322 /* DWT Sleep Count Register Definitions */ 01323 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 01324 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 01325 01326 /* DWT LSU Count Register Definitions */ 01327 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 01328 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 01329 01330 /* DWT Folded-instruction Count Register Definitions */ 01331 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 01332 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 01333 01334 /* DWT Comparator Function Register Definitions */ 01335 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 01336 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 01337 01338 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 01339 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 01340 01341 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 01342 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 01343 01344 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 01345 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 01346 01347 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 01348 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 01349 01350 /*@}*/ /* end of group CMSIS_DWT */ 01351 01352 01353 /** 01354 \ingroup CMSIS_core_register 01355 \defgroup CMSIS_TPI Trace Port Interface (TPI) 01356 \brief Type definitions for the Trace Port Interface (TPI) 01357 @{ 01358 */ 01359 01360 /** 01361 \brief Structure type to access the Trace Port Interface Register (TPI). 01362 */ 01363 typedef struct 01364 { 01365 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ 01366 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ 01367 uint32_t RESERVED0[2U]; 01368 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 01369 uint32_t RESERVED1[55U]; 01370 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 01371 uint32_t RESERVED2[131U]; 01372 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 01373 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 01374 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ 01375 uint32_t RESERVED3[809U]; 01376 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ 01377 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ 01378 uint32_t RESERVED4[4U]; 01379 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ 01380 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ 01381 } TPI_Type; 01382 01383 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01384 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ 01385 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ 01386 01387 /* TPI Selected Pin Protocol Register Definitions */ 01388 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 01389 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 01390 01391 /* TPI Formatter and Flush Status Register Definitions */ 01392 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 01393 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01394 01395 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 01396 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01397 01398 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 01399 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01400 01401 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 01402 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 01403 01404 /* TPI Formatter and Flush Control Register Definitions */ 01405 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 01406 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01407 01408 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ 01409 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ 01410 01411 #define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ 01412 #define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ 01413 01414 /* TPI Periodic Synchronization Control Register Definitions */ 01415 #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ 01416 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ 01417 01418 /* TPI Software Lock Status Register Definitions */ 01419 #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ 01420 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ 01421 01422 #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ 01423 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ 01424 01425 #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ 01426 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ 01427 01428 /* TPI DEVID Register Definitions */ 01429 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 01430 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01431 01432 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 01433 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01434 01435 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 01436 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01437 01438 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ 01439 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ 01440 01441 /* TPI DEVTYPE Register Definitions */ 01442 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 01443 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 01444 01445 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 01446 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01447 01448 /*@}*/ /* end of group CMSIS_TPI */ 01449 01450 01451 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01452 /** 01453 \ingroup CMSIS_core_register 01454 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01455 \brief Type definitions for the Memory Protection Unit (MPU) 01456 @{ 01457 */ 01458 01459 /** 01460 \brief Structure type to access the Memory Protection Unit (MPU). 01461 */ 01462 typedef struct 01463 { 01464 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01465 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01466 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 01467 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01468 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 01469 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ 01470 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ 01471 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ 01472 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ 01473 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ 01474 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ 01475 uint32_t RESERVED0[1]; 01476 union { 01477 __IOM uint32_t MAIR[2]; 01478 struct { 01479 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 01480 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 01481 }; 01482 }; 01483 } MPU_Type; 01484 01485 #define MPU_TYPE_RALIASES 4U 01486 01487 /* MPU Type Register Definitions */ 01488 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 01489 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01490 01491 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 01492 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01493 01494 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 01495 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 01496 01497 /* MPU Control Register Definitions */ 01498 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 01499 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01500 01501 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 01502 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01503 01504 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 01505 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 01506 01507 /* MPU Region Number Register Definitions */ 01508 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 01509 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 01510 01511 /* MPU Region Base Address Register Definitions */ 01512 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 01513 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 01514 01515 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 01516 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 01517 01518 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 01519 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 01520 01521 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 01522 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 01523 01524 /* MPU Region Limit Address Register Definitions */ 01525 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 01526 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 01527 01528 #define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ 01529 #define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ 01530 01531 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 01532 #define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 01533 01534 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ 01535 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ 01536 01537 /* MPU Memory Attribute Indirection Register 0 Definitions */ 01538 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 01539 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 01540 01541 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 01542 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 01543 01544 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 01545 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 01546 01547 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 01548 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 01549 01550 /* MPU Memory Attribute Indirection Register 1 Definitions */ 01551 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 01552 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 01553 01554 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 01555 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 01556 01557 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 01558 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 01559 01560 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 01561 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 01562 01563 /*@} end of group CMSIS_MPU */ 01564 #endif 01565 01566 01567 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01568 /** 01569 \ingroup CMSIS_core_register 01570 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 01571 \brief Type definitions for the Security Attribution Unit (SAU) 01572 @{ 01573 */ 01574 01575 /** 01576 \brief Structure type to access the Security Attribution Unit (SAU). 01577 */ 01578 typedef struct 01579 { 01580 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 01581 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 01582 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 01583 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 01584 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 01585 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 01586 #else 01587 uint32_t RESERVED0[3]; 01588 #endif 01589 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ 01590 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ 01591 } SAU_Type; 01592 01593 /* SAU Control Register Definitions */ 01594 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 01595 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 01596 01597 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 01598 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 01599 01600 /* SAU Type Register Definitions */ 01601 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 01602 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 01603 01604 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 01605 /* SAU Region Number Register Definitions */ 01606 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 01607 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 01608 01609 /* SAU Region Base Address Register Definitions */ 01610 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 01611 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 01612 01613 /* SAU Region Limit Address Register Definitions */ 01614 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 01615 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 01616 01617 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 01618 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 01619 01620 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 01621 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 01622 01623 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 01624 01625 /* Secure Fault Status Register Definitions */ 01626 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ 01627 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ 01628 01629 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ 01630 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ 01631 01632 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ 01633 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ 01634 01635 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ 01636 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ 01637 01638 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ 01639 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ 01640 01641 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ 01642 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ 01643 01644 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ 01645 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ 01646 01647 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ 01648 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ 01649 01650 /*@} end of group CMSIS_SAU */ 01651 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01652 01653 01654 /** 01655 \ingroup CMSIS_core_register 01656 \defgroup CMSIS_FPU Floating Point Unit (FPU) 01657 \brief Type definitions for the Floating Point Unit (FPU) 01658 @{ 01659 */ 01660 01661 /** 01662 \brief Structure type to access the Floating Point Unit (FPU). 01663 */ 01664 typedef struct 01665 { 01666 uint32_t RESERVED0[1U]; 01667 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 01668 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 01669 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 01670 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 01671 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 01672 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ 01673 } FPU_Type; 01674 01675 /* Floating-Point Context Control Register Definitions */ 01676 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 01677 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 01678 01679 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 01680 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 01681 01682 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ 01683 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ 01684 01685 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ 01686 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ 01687 01688 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ 01689 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ 01690 01691 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ 01692 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ 01693 01694 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ 01695 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ 01696 01697 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ 01698 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ 01699 01700 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 01701 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 01702 01703 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ 01704 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ 01705 01706 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 01707 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 01708 01709 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 01710 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 01711 01712 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 01713 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 01714 01715 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 01716 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 01717 01718 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ 01719 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ 01720 01721 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 01722 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 01723 01724 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 01725 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 01726 01727 /* Floating-Point Context Address Register Definitions */ 01728 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 01729 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 01730 01731 /* Floating-Point Default Status Control Register Definitions */ 01732 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 01733 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 01734 01735 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 01736 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 01737 01738 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 01739 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 01740 01741 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 01742 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 01743 01744 #define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ 01745 #define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ 01746 01747 #define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ 01748 #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ 01749 01750 /* Media and FP Feature Register 0 Definitions */ 01751 #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ 01752 #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ 01753 01754 #define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ 01755 #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ 01756 01757 #define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ 01758 #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ 01759 01760 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ 01761 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ 01762 01763 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ 01764 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ 01765 01766 #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ 01767 #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ 01768 01769 /* Media and FP Feature Register 1 Definitions */ 01770 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ 01771 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ 01772 01773 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ 01774 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ 01775 01776 #define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ 01777 #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ 01778 01779 #define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ 01780 #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ 01781 01782 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ 01783 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ 01784 01785 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ 01786 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ 01787 01788 /* Media and FP Feature Register 2 Definitions */ 01789 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ 01790 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ 01791 01792 /*@} end of group CMSIS_FPU */ 01793 01794 01795 /** 01796 \ingroup CMSIS_core_register 01797 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01798 \brief Type definitions for the Core Debug Registers 01799 @{ 01800 */ 01801 01802 /** 01803 \brief Structure type to access the Core Debug Register (CoreDebug). 01804 */ 01805 typedef struct 01806 { 01807 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01808 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01809 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01810 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01811 __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ 01812 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 01813 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 01814 } CoreDebug_Type; 01815 01816 /* Debug Halting Control and Status Register Definitions */ 01817 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01818 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01819 01820 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ 01821 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ 01822 01823 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01824 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01825 01826 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01827 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01828 01829 #define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< CoreDebug DHCSR: S_FPD Position */ 01830 #define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< CoreDebug DHCSR: S_FPD Mask */ 01831 01832 #define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< CoreDebug DHCSR: S_SUIDE Position */ 01833 #define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< CoreDebug DHCSR: S_SUIDE Mask */ 01834 01835 #define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< CoreDebug DHCSR: S_NSUIDE Position */ 01836 #define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< CoreDebug DHCSR: S_NSUIDE Mask */ 01837 01838 #define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< CoreDebug DHCSR: S_SDE Position */ 01839 #define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< CoreDebug DHCSR: S_SDE Mask */ 01840 01841 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01842 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01843 01844 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01845 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01846 01847 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01848 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01849 01850 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01851 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01852 01853 #define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< CoreDebug DHCSR: C_PMOV Position */ 01854 #define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< CoreDebug DHCSR: C_PMOV Mask */ 01855 01856 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01857 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01858 01859 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01860 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01861 01862 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01863 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01864 01865 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01866 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01867 01868 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01869 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01870 01871 /* Debug Core Register Selector Register Definitions */ 01872 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01873 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01874 01875 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01876 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01877 01878 /* Debug Exception and Monitor Control Register Definitions */ 01879 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 01880 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01881 01882 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 01883 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01884 01885 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 01886 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01887 01888 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 01889 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01890 01891 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 01892 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01893 01894 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01895 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01896 01897 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 01898 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01899 01900 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01901 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01902 01903 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 01904 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01905 01906 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01907 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01908 01909 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01910 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01911 01912 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 01913 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01914 01915 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01916 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01917 01918 /* Debug Set Clear Exception and Monitor Control Register Definitions */ 01919 #define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< CoreDebug DSCEMCR: CLR_MON_REQ, Position */ 01920 #define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ 01921 01922 #define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< CoreDebug DSCEMCR: CLR_MON_PEND, Position */ 01923 #define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ 01924 01925 #define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< CoreDebug DSCEMCR: SET_MON_REQ, Position */ 01926 #define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< CoreDebug DSCEMCR: SET_MON_REQ, Mask */ 01927 01928 #define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< CoreDebug DSCEMCR: SET_MON_PEND, Position */ 01929 #define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< CoreDebug DSCEMCR: SET_MON_PEND, Mask */ 01930 01931 /* Debug Authentication Control Register Definitions */ 01932 #define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< CoreDebug DAUTHCTRL: UIDEN, Position */ 01933 #define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< CoreDebug DAUTHCTRL: UIDEN, Mask */ 01934 01935 #define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< CoreDebug DAUTHCTRL: UIDAPEN, Position */ 01936 #define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< CoreDebug DAUTHCTRL: UIDAPEN, Mask */ 01937 01938 #define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< CoreDebug DAUTHCTRL: FSDMA, Position */ 01939 #define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< CoreDebug DAUTHCTRL: FSDMA, Mask */ 01940 01941 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 01942 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 01943 01944 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 01945 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 01946 01947 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ 01948 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 01949 01950 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ 01951 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 01952 01953 /* Debug Security Control and Status Register Definitions */ 01954 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ 01955 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ 01956 01957 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ 01958 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ 01959 01960 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ 01961 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ 01962 01963 /*@} end of group CMSIS_CoreDebug */ 01964 01965 01966 /** 01967 \ingroup CMSIS_core_register 01968 \defgroup CMSIS_core_bitfield Core register bit field macros 01969 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01970 @{ 01971 */ 01972 01973 /** 01974 \brief Mask and shift a bit field value for use in a register bit range. 01975 \param[in] field Name of the register bit field. 01976 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01977 \return Masked and shifted value. 01978 */ 01979 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01980 01981 /** 01982 \brief Mask and shift a register value to extract a bit filed value. 01983 \param[in] field Name of the register bit field. 01984 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01985 \return Masked and shifted bit field value. 01986 */ 01987 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01988 01989 /*@} end of group CMSIS_core_bitfield */ 01990 01991 01992 /** 01993 \ingroup CMSIS_core_register 01994 \defgroup CMSIS_core_base Core Definitions 01995 \brief Definitions for base addresses, unions, and structures. 01996 @{ 01997 */ 01998 01999 /* Memory mapping of Core Hardware */ 02000 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 02001 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 02002 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 02003 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 02004 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 02005 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 02006 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 02007 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 02008 02009 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 02010 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 02011 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 02012 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 02013 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 02014 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 02015 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 02016 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ 02017 02018 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 02019 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 02020 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 02021 #endif 02022 02023 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02024 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 02025 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 02026 #endif 02027 02028 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 02029 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 02030 02031 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02032 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 02033 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ 02034 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 02035 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 02036 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 02037 02038 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ 02039 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 02040 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 02041 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 02042 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ 02043 02044 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 02045 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 02046 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 02047 #endif 02048 02049 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ 02050 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ 02051 02052 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02053 /*@} */ 02054 02055 02056 02057 /******************************************************************************* 02058 * Hardware Abstraction Layer 02059 Core Function Interface contains: 02060 - Core NVIC Functions 02061 - Core SysTick Functions 02062 - Core Debug Functions 02063 - Core Register Access Functions 02064 ******************************************************************************/ 02065 /** 02066 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 02067 */ 02068 02069 02070 02071 /* ########################## NVIC functions #################################### */ 02072 /** 02073 \ingroup CMSIS_Core_FunctionInterface 02074 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 02075 \brief Functions that manage interrupts and exceptions via the NVIC. 02076 @{ 02077 */ 02078 02079 #ifdef CMSIS_NVIC_VIRTUAL 02080 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 02081 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 02082 #endif 02083 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 02084 #else 02085 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 02086 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 02087 #define NVIC_EnableIRQ __NVIC_EnableIRQ 02088 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 02089 #define NVIC_DisableIRQ __NVIC_DisableIRQ 02090 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 02091 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 02092 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 02093 #define NVIC_GetActive __NVIC_GetActive 02094 #define NVIC_SetPriority __NVIC_SetPriority 02095 #define NVIC_GetPriority __NVIC_GetPriority 02096 #define NVIC_SystemReset __NVIC_SystemReset 02097 #endif /* CMSIS_NVIC_VIRTUAL */ 02098 02099 #ifdef CMSIS_VECTAB_VIRTUAL 02100 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 02101 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 02102 #endif 02103 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 02104 #else 02105 #define NVIC_SetVector __NVIC_SetVector 02106 #define NVIC_GetVector __NVIC_GetVector 02107 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 02108 02109 #define NVIC_USER_IRQ_OFFSET 16 02110 02111 02112 /* Special LR values for Secure/Non-Secure call handling and exception handling */ 02113 02114 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ 02115 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ 02116 02117 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ 02118 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ 02119 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ 02120 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ 02121 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ 02122 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ 02123 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ 02124 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ 02125 02126 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ 02127 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ 02128 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ 02129 #else 02130 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ 02131 #endif 02132 02133 02134 /** 02135 \brief Set Priority Grouping 02136 \details Sets the priority grouping field using the required unlock sequence. 02137 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 02138 Only values from 0..7 are used. 02139 In case of a conflict between priority grouping and available 02140 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 02141 \param [in] PriorityGroup Priority grouping field. 02142 */ 02143 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 02144 { 02145 uint32_t reg_value; 02146 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02147 02148 reg_value = SCB->AIRCR; /* read old register configuration */ 02149 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 02150 reg_value = (reg_value | 02151 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 02152 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 02153 SCB->AIRCR = reg_value; 02154 } 02155 02156 02157 /** 02158 \brief Get Priority Grouping 02159 \details Reads the priority grouping field from the NVIC Interrupt Controller. 02160 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 02161 */ 02162 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 02163 { 02164 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 02165 } 02166 02167 02168 /** 02169 \brief Enable Interrupt 02170 \details Enables a device specific interrupt in the NVIC interrupt controller. 02171 \param [in] IRQn Device specific interrupt number. 02172 \note IRQn must not be negative. 02173 */ 02174 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 02175 { 02176 if ((int32_t)(IRQn) >= 0) 02177 { 02178 __COMPILER_BARRIER(); 02179 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02180 __COMPILER_BARRIER(); 02181 } 02182 } 02183 02184 02185 /** 02186 \brief Get Interrupt Enable status 02187 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 02188 \param [in] IRQn Device specific interrupt number. 02189 \return 0 Interrupt is not enabled. 02190 \return 1 Interrupt is enabled. 02191 \note IRQn must not be negative. 02192 */ 02193 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 02194 { 02195 if ((int32_t)(IRQn) >= 0) 02196 { 02197 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02198 } 02199 else 02200 { 02201 return(0U); 02202 } 02203 } 02204 02205 02206 /** 02207 \brief Disable Interrupt 02208 \details Disables a device specific interrupt in the NVIC interrupt controller. 02209 \param [in] IRQn Device specific interrupt number. 02210 \note IRQn must not be negative. 02211 */ 02212 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 02213 { 02214 if ((int32_t)(IRQn) >= 0) 02215 { 02216 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02217 __DSB(); 02218 __ISB(); 02219 } 02220 } 02221 02222 02223 /** 02224 \brief Get Pending Interrupt 02225 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 02226 \param [in] IRQn Device specific interrupt number. 02227 \return 0 Interrupt status is not pending. 02228 \return 1 Interrupt status is pending. 02229 \note IRQn must not be negative. 02230 */ 02231 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 02232 { 02233 if ((int32_t)(IRQn) >= 0) 02234 { 02235 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02236 } 02237 else 02238 { 02239 return(0U); 02240 } 02241 } 02242 02243 02244 /** 02245 \brief Set Pending Interrupt 02246 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 02247 \param [in] IRQn Device specific interrupt number. 02248 \note IRQn must not be negative. 02249 */ 02250 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 02251 { 02252 if ((int32_t)(IRQn) >= 0) 02253 { 02254 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02255 } 02256 } 02257 02258 02259 /** 02260 \brief Clear Pending Interrupt 02261 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 02262 \param [in] IRQn Device specific interrupt number. 02263 \note IRQn must not be negative. 02264 */ 02265 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 02266 { 02267 if ((int32_t)(IRQn) >= 0) 02268 { 02269 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02270 } 02271 } 02272 02273 02274 /** 02275 \brief Get Active Interrupt 02276 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 02277 \param [in] IRQn Device specific interrupt number. 02278 \return 0 Interrupt status is not active. 02279 \return 1 Interrupt status is active. 02280 \note IRQn must not be negative. 02281 */ 02282 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 02283 { 02284 if ((int32_t)(IRQn) >= 0) 02285 { 02286 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02287 } 02288 else 02289 { 02290 return(0U); 02291 } 02292 } 02293 02294 02295 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02296 /** 02297 \brief Get Interrupt Target State 02298 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 02299 \param [in] IRQn Device specific interrupt number. 02300 \return 0 if interrupt is assigned to Secure 02301 \return 1 if interrupt is assigned to Non Secure 02302 \note IRQn must not be negative. 02303 */ 02304 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 02305 { 02306 if ((int32_t)(IRQn) >= 0) 02307 { 02308 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02309 } 02310 else 02311 { 02312 return(0U); 02313 } 02314 } 02315 02316 02317 /** 02318 \brief Set Interrupt Target State 02319 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 02320 \param [in] IRQn Device specific interrupt number. 02321 \return 0 if interrupt is assigned to Secure 02322 1 if interrupt is assigned to Non Secure 02323 \note IRQn must not be negative. 02324 */ 02325 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 02326 { 02327 if ((int32_t)(IRQn) >= 0) 02328 { 02329 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 02330 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02331 } 02332 else 02333 { 02334 return(0U); 02335 } 02336 } 02337 02338 02339 /** 02340 \brief Clear Interrupt Target State 02341 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 02342 \param [in] IRQn Device specific interrupt number. 02343 \return 0 if interrupt is assigned to Secure 02344 1 if interrupt is assigned to Non Secure 02345 \note IRQn must not be negative. 02346 */ 02347 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 02348 { 02349 if ((int32_t)(IRQn) >= 0) 02350 { 02351 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 02352 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02353 } 02354 else 02355 { 02356 return(0U); 02357 } 02358 } 02359 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02360 02361 02362 /** 02363 \brief Set Interrupt Priority 02364 \details Sets the priority of a device specific interrupt or a processor exception. 02365 The interrupt number can be positive to specify a device specific interrupt, 02366 or negative to specify a processor exception. 02367 \param [in] IRQn Interrupt number. 02368 \param [in] priority Priority to set. 02369 \note The priority cannot be set for every processor exception. 02370 */ 02371 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 02372 { 02373 if ((int32_t)(IRQn) >= 0) 02374 { 02375 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02376 } 02377 else 02378 { 02379 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02380 } 02381 } 02382 02383 02384 /** 02385 \brief Get Interrupt Priority 02386 \details Reads the priority of a device specific interrupt or a processor exception. 02387 The interrupt number can be positive to specify a device specific interrupt, 02388 or negative to specify a processor exception. 02389 \param [in] IRQn Interrupt number. 02390 \return Interrupt Priority. 02391 Value is aligned automatically to the implemented priority bits of the microcontroller. 02392 */ 02393 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 02394 { 02395 02396 if ((int32_t)(IRQn) >= 0) 02397 { 02398 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 02399 } 02400 else 02401 { 02402 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 02403 } 02404 } 02405 02406 02407 /** 02408 \brief Encode Priority 02409 \details Encodes the priority for an interrupt with the given priority group, 02410 preemptive priority value, and subpriority value. 02411 In case of a conflict between priority grouping and available 02412 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 02413 \param [in] PriorityGroup Used priority group. 02414 \param [in] PreemptPriority Preemptive priority value (starting from 0). 02415 \param [in] SubPriority Subpriority value (starting from 0). 02416 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 02417 */ 02418 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 02419 { 02420 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02421 uint32_t PreemptPriorityBits; 02422 uint32_t SubPriorityBits; 02423 02424 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 02425 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 02426 02427 return ( 02428 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 02429 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 02430 ); 02431 } 02432 02433 02434 /** 02435 \brief Decode Priority 02436 \details Decodes an interrupt priority value with a given priority group to 02437 preemptive priority value and subpriority value. 02438 In case of a conflict between priority grouping and available 02439 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 02440 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 02441 \param [in] PriorityGroup Used priority group. 02442 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 02443 \param [out] pSubPriority Subpriority value (starting from 0). 02444 */ 02445 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 02446 { 02447 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02448 uint32_t PreemptPriorityBits; 02449 uint32_t SubPriorityBits; 02450 02451 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 02452 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 02453 02454 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 02455 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 02456 } 02457 02458 02459 /** 02460 \brief Set Interrupt Vector 02461 \details Sets an interrupt vector in SRAM based interrupt vector table. 02462 The interrupt number can be positive to specify a device specific interrupt, 02463 or negative to specify a processor exception. 02464 VTOR must been relocated to SRAM before. 02465 \param [in] IRQn Interrupt number 02466 \param [in] vector Address of interrupt handler function 02467 */ 02468 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 02469 { 02470 uint32_t *vectors = (uint32_t *)SCB->VTOR; 02471 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 02472 __DSB(); 02473 } 02474 02475 02476 /** 02477 \brief Get Interrupt Vector 02478 \details Reads an interrupt vector from interrupt vector table. 02479 The interrupt number can be positive to specify a device specific interrupt, 02480 or negative to specify a processor exception. 02481 \param [in] IRQn Interrupt number. 02482 \return Address of interrupt handler function 02483 */ 02484 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 02485 { 02486 uint32_t *vectors = (uint32_t *)SCB->VTOR; 02487 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 02488 } 02489 02490 02491 /** 02492 \brief System Reset 02493 \details Initiates a system reset request to reset the MCU. 02494 */ 02495 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 02496 { 02497 __DSB(); /* Ensure all outstanding memory accesses included 02498 buffered write are completed before reset */ 02499 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 02500 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 02501 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 02502 __DSB(); /* Ensure completion of memory access */ 02503 02504 for(;;) /* wait until reset */ 02505 { 02506 __NOP(); 02507 } 02508 } 02509 02510 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02511 /** 02512 \brief Set Priority Grouping (non-secure) 02513 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. 02514 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 02515 Only values from 0..7 are used. 02516 In case of a conflict between priority grouping and available 02517 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 02518 \param [in] PriorityGroup Priority grouping field. 02519 */ 02520 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) 02521 { 02522 uint32_t reg_value; 02523 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02524 02525 reg_value = SCB_NS->AIRCR; /* read old register configuration */ 02526 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 02527 reg_value = (reg_value | 02528 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 02529 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 02530 SCB_NS->AIRCR = reg_value; 02531 } 02532 02533 02534 /** 02535 \brief Get Priority Grouping (non-secure) 02536 \details Reads the priority grouping field from the non-secure NVIC when in secure state. 02537 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 02538 */ 02539 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) 02540 { 02541 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 02542 } 02543 02544 02545 /** 02546 \brief Enable Interrupt (non-secure) 02547 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 02548 \param [in] IRQn Device specific interrupt number. 02549 \note IRQn must not be negative. 02550 */ 02551 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 02552 { 02553 if ((int32_t)(IRQn) >= 0) 02554 { 02555 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02556 } 02557 } 02558 02559 02560 /** 02561 \brief Get Interrupt Enable status (non-secure) 02562 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 02563 \param [in] IRQn Device specific interrupt number. 02564 \return 0 Interrupt is not enabled. 02565 \return 1 Interrupt is enabled. 02566 \note IRQn must not be negative. 02567 */ 02568 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 02569 { 02570 if ((int32_t)(IRQn) >= 0) 02571 { 02572 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02573 } 02574 else 02575 { 02576 return(0U); 02577 } 02578 } 02579 02580 02581 /** 02582 \brief Disable Interrupt (non-secure) 02583 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 02584 \param [in] IRQn Device specific interrupt number. 02585 \note IRQn must not be negative. 02586 */ 02587 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 02588 { 02589 if ((int32_t)(IRQn) >= 0) 02590 { 02591 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02592 } 02593 } 02594 02595 02596 /** 02597 \brief Get Pending Interrupt (non-secure) 02598 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 02599 \param [in] IRQn Device specific interrupt number. 02600 \return 0 Interrupt status is not pending. 02601 \return 1 Interrupt status is pending. 02602 \note IRQn must not be negative. 02603 */ 02604 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 02605 { 02606 if ((int32_t)(IRQn) >= 0) 02607 { 02608 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02609 } 02610 else 02611 { 02612 return(0U); 02613 } 02614 } 02615 02616 02617 /** 02618 \brief Set Pending Interrupt (non-secure) 02619 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 02620 \param [in] IRQn Device specific interrupt number. 02621 \note IRQn must not be negative. 02622 */ 02623 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 02624 { 02625 if ((int32_t)(IRQn) >= 0) 02626 { 02627 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02628 } 02629 } 02630 02631 02632 /** 02633 \brief Clear Pending Interrupt (non-secure) 02634 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 02635 \param [in] IRQn Device specific interrupt number. 02636 \note IRQn must not be negative. 02637 */ 02638 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 02639 { 02640 if ((int32_t)(IRQn) >= 0) 02641 { 02642 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02643 } 02644 } 02645 02646 02647 /** 02648 \brief Get Active Interrupt (non-secure) 02649 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 02650 \param [in] IRQn Device specific interrupt number. 02651 \return 0 Interrupt status is not active. 02652 \return 1 Interrupt status is active. 02653 \note IRQn must not be negative. 02654 */ 02655 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 02656 { 02657 if ((int32_t)(IRQn) >= 0) 02658 { 02659 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02660 } 02661 else 02662 { 02663 return(0U); 02664 } 02665 } 02666 02667 02668 /** 02669 \brief Set Interrupt Priority (non-secure) 02670 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 02671 The interrupt number can be positive to specify a device specific interrupt, 02672 or negative to specify a processor exception. 02673 \param [in] IRQn Interrupt number. 02674 \param [in] priority Priority to set. 02675 \note The priority cannot be set for every non-secure processor exception. 02676 */ 02677 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 02678 { 02679 if ((int32_t)(IRQn) >= 0) 02680 { 02681 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02682 } 02683 else 02684 { 02685 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02686 } 02687 } 02688 02689 02690 /** 02691 \brief Get Interrupt Priority (non-secure) 02692 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 02693 The interrupt number can be positive to specify a device specific interrupt, 02694 or negative to specify a processor exception. 02695 \param [in] IRQn Interrupt number. 02696 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 02697 */ 02698 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 02699 { 02700 02701 if ((int32_t)(IRQn) >= 0) 02702 { 02703 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 02704 } 02705 else 02706 { 02707 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 02708 } 02709 } 02710 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 02711 02712 /*@} end of CMSIS_Core_NVICFunctions */ 02713 02714 /* ########################## MPU functions #################################### */ 02715 02716 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 02717 02718 #include "mpu_armv8.h" 02719 02720 #endif 02721 02722 /* ########################## FPU functions #################################### */ 02723 /** 02724 \ingroup CMSIS_Core_FunctionInterface 02725 \defgroup CMSIS_Core_FpuFunctions FPU Functions 02726 \brief Function that provides FPU type. 02727 @{ 02728 */ 02729 02730 /** 02731 \brief get FPU type 02732 \details returns the FPU type 02733 \returns 02734 - \b 0: No FPU 02735 - \b 1: Single precision FPU 02736 - \b 2: Double + Single precision FPU 02737 */ 02738 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 02739 { 02740 uint32_t mvfr0; 02741 02742 mvfr0 = FPU->MVFR0; 02743 if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) 02744 { 02745 return 2U; /* Double + Single precision FPU */ 02746 } 02747 else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) 02748 { 02749 return 1U; /* Single precision FPU */ 02750 } 02751 else 02752 { 02753 return 0U; /* No FPU */ 02754 } 02755 } 02756 02757 02758 /*@} end of CMSIS_Core_FpuFunctions */ 02759 02760 02761 02762 /* ########################## SAU functions #################################### */ 02763 /** 02764 \ingroup CMSIS_Core_FunctionInterface 02765 \defgroup CMSIS_Core_SAUFunctions SAU Functions 02766 \brief Functions that configure the SAU. 02767 @{ 02768 */ 02769 02770 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02771 02772 /** 02773 \brief Enable SAU 02774 \details Enables the Security Attribution Unit (SAU). 02775 */ 02776 __STATIC_INLINE void TZ_SAU_Enable(void) 02777 { 02778 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 02779 } 02780 02781 02782 02783 /** 02784 \brief Disable SAU 02785 \details Disables the Security Attribution Unit (SAU). 02786 */ 02787 __STATIC_INLINE void TZ_SAU_Disable(void) 02788 { 02789 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 02790 } 02791 02792 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02793 02794 /*@} end of CMSIS_Core_SAUFunctions */ 02795 02796 02797 02798 02799 /* ################################## SysTick function ############################################ */ 02800 /** 02801 \ingroup CMSIS_Core_FunctionInterface 02802 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 02803 \brief Functions that configure the System. 02804 @{ 02805 */ 02806 02807 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 02808 02809 /** 02810 \brief System Tick Configuration 02811 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 02812 Counter is in free running mode to generate periodic interrupts. 02813 \param [in] ticks Number of ticks between two interrupts. 02814 \return 0 Function succeeded. 02815 \return 1 Function failed. 02816 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 02817 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 02818 must contain a vendor-specific implementation of this function. 02819 */ 02820 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 02821 { 02822 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 02823 { 02824 return (1UL); /* Reload value impossible */ 02825 } 02826 02827 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 02828 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 02829 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 02830 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02831 SysTick_CTRL_TICKINT_Msk | 02832 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02833 return (0UL); /* Function successful */ 02834 } 02835 02836 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02837 /** 02838 \brief System Tick Configuration (non-secure) 02839 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 02840 Counter is in free running mode to generate periodic interrupts. 02841 \param [in] ticks Number of ticks between two interrupts. 02842 \return 0 Function succeeded. 02843 \return 1 Function failed. 02844 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 02845 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 02846 must contain a vendor-specific implementation of this function. 02847 02848 */ 02849 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 02850 { 02851 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 02852 { 02853 return (1UL); /* Reload value impossible */ 02854 } 02855 02856 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 02857 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 02858 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 02859 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02860 SysTick_CTRL_TICKINT_Msk | 02861 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02862 return (0UL); /* Function successful */ 02863 } 02864 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02865 02866 #endif 02867 02868 /*@} end of CMSIS_Core_SysTickFunctions */ 02869 02870 02871 02872 /* ##################################### Debug In/Output function ########################################### */ 02873 /** 02874 \ingroup CMSIS_Core_FunctionInterface 02875 \defgroup CMSIS_core_DebugFunctions ITM Functions 02876 \brief Functions that access the ITM debug interface. 02877 @{ 02878 */ 02879 02880 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 02881 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 02882 02883 02884 /** 02885 \brief ITM Send Character 02886 \details Transmits a character via the ITM channel 0, and 02887 \li Just returns when no debugger is connected that has booked the output. 02888 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 02889 \param [in] ch Character to transmit. 02890 \returns Character to transmit. 02891 */ 02892 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 02893 { 02894 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 02895 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 02896 { 02897 while (ITM->PORT[0U].u32 == 0UL) 02898 { 02899 __NOP(); 02900 } 02901 ITM->PORT[0U].u8 = (uint8_t)ch; 02902 } 02903 return (ch); 02904 } 02905 02906 02907 /** 02908 \brief ITM Receive Character 02909 \details Inputs a character via the external variable \ref ITM_RxBuffer. 02910 \return Received character. 02911 \return -1 No character pending. 02912 */ 02913 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 02914 { 02915 int32_t ch = -1; /* no character available */ 02916 02917 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 02918 { 02919 ch = ITM_RxBuffer; 02920 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 02921 } 02922 02923 return (ch); 02924 } 02925 02926 02927 /** 02928 \brief ITM Check Character 02929 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 02930 \return 0 No character available. 02931 \return 1 Character available. 02932 */ 02933 __STATIC_INLINE int32_t ITM_CheckChar (void) 02934 { 02935 02936 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 02937 { 02938 return (0); /* no character available */ 02939 } 02940 else 02941 { 02942 return (1); /* character available */ 02943 } 02944 } 02945 02946 /*@} end of CMSIS_core_DebugFunctions */ 02947 02948 02949 02950 02951 #ifdef __cplusplus 02952 } 02953 #endif 02954 02955 #endif /* __CORE_ARMV81MML_H_DEPENDANT */ 02956 02957 #endif /* __CMSIS_GENERIC */
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