wdt.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAM3U_WDT_COMPONENT_
00031 #define _SAM3U_WDT_COMPONENT_
00032 
00033 /* ============================================================================= */
00034 /**  SOFTWARE API DEFINITION FOR Watchdog Timer */
00035 /* ============================================================================= */
00036 /** \addtogroup SAM3U_WDT Watchdog Timer */
00037 /*@{*/
00038 
00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00040 /** \brief Wdt hardware registers */
00041 typedef struct {
00042   WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
00043   RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
00044   RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
00045 } Wdt;
00046 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00047 /* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
00048 #define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
00049 #define WDT_CR_KEY_Pos 24
00050 #define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
00051 #define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
00052 /* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
00053 #define WDT_MR_WDV_Pos 0
00054 #define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
00055 #define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
00056 #define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
00057 #define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
00058 #define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
00059 #define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
00060 #define WDT_MR_WDD_Pos 16
00061 #define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
00062 #define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
00063 #define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
00064 #define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
00065 /* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
00066 #define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
00067 #define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
00068 
00069 /*@}*/
00070 
00071 
00072 #endif /* _SAM3U_WDT_COMPONENT_ */