rstc.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAM3U_RSTC_COMPONENT_
00031 #define _SAM3U_RSTC_COMPONENT_
00032 
00033 /* ============================================================================= */
00034 /**  SOFTWARE API DEFINITION FOR Reset Controller */
00035 /* ============================================================================= */
00036 /** \addtogroup SAM3U_RSTC Reset Controller */
00037 /*@{*/
00038 
00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00040 /** \brief Rstc hardware registers */
00041 typedef struct {
00042   WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
00043   RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
00044   RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
00045 } Rstc;
00046 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00047 /* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
00048 #define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
00049 #define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
00050 #define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
00051 #define RSTC_CR_KEY_Pos 24
00052 #define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
00053 #define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
00054 /* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
00055 #define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
00056 #define RSTC_SR_RSTTYP_Pos 8
00057 #define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
00058 #define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
00059 #define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
00060 /* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
00061 #define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
00062 #define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
00063 #define RSTC_MR_ERSTL_Pos 8
00064 #define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
00065 #define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
00066 #define RSTC_MR_KEY_Pos 24
00067 #define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
00068 #define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
00069 
00070 /*@}*/
00071 
00072 
00073 #endif /* _SAM3U_RSTC_COMPONENT_ */