cmsis_iccarm.h

00001 /**************************************************************************//**
00002  * @file     cmsis_iccarm.h
00003  * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
00004  * @version  V5.1.1
00005  * @date     30. July 2019
00006  ******************************************************************************/
00007 
00008 //------------------------------------------------------------------------------
00009 //
00010 // Copyright (c) 2017-2019 IAR Systems
00011 // Copyright (c) 2017-2019 Arm Limited. All rights reserved. 
00012 //
00013 // Licensed under the Apache License, Version 2.0 (the "License")
00014 // you may not use this file except in compliance with the License.
00015 // You may obtain a copy of the License at
00016 //     http://www.apache.org/licenses/LICENSE-2.0
00017 //
00018 // Unless required by applicable law or agreed to in writing, software
00019 // distributed under the License is distributed on an "AS IS" BASIS,
00020 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00021 // See the License for the specific language governing permissions and
00022 // limitations under the License.
00023 //
00024 //------------------------------------------------------------------------------
00025 
00026 
00027 #ifndef __CMSIS_ICCARM_H__
00028 #define __CMSIS_ICCARM_H__
00029 
00030 #ifndef __ICCARM__
00031   #error This file should only be compiled by ICCARM
00032 #endif
00033 
00034 #pragma system_include
00035 
00036 #define __IAR_FT _Pragma("inline=forced") __intrinsic
00037 
00038 #if (__VER__ >= 8000000)
00039   #define __ICCARM_V8 1
00040 #else
00041   #define __ICCARM_V8 0
00042 #endif
00043 
00044 #ifndef __ALIGNED
00045   #if __ICCARM_V8
00046     #define __ALIGNED(x) __attribute__((aligned(x)))
00047   #elif (__VER__ >= 7080000)
00048     /* Needs IAR language extensions */
00049     #define __ALIGNED(x) __attribute__((aligned(x)))
00050   #else
00051     #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
00052     #define __ALIGNED(x)
00053   #endif
00054 #endif
00055 
00056 
00057 /* Define compiler macros for CPU architecture, used in CMSIS 5.
00058  */
00059 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
00060 /* Macros already defined */
00061 #else
00062   #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
00063     #define __ARM_ARCH_8M_MAIN__ 1
00064   #elif defined(__ARM8M_BASELINE__)
00065     #define __ARM_ARCH_8M_BASE__ 1
00066   #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
00067     #if __ARM_ARCH == 6
00068       #define __ARM_ARCH_6M__ 1
00069     #elif __ARM_ARCH == 7
00070       #if __ARM_FEATURE_DSP
00071         #define __ARM_ARCH_7EM__ 1
00072       #else
00073         #define __ARM_ARCH_7M__ 1
00074       #endif
00075     #endif /* __ARM_ARCH */
00076   #endif /* __ARM_ARCH_PROFILE == 'M' */
00077 #endif
00078 
00079 /* Alternativ core deduction for older ICCARM's */
00080 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
00081     !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
00082   #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
00083     #define __ARM_ARCH_6M__ 1
00084   #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
00085     #define __ARM_ARCH_7M__ 1
00086   #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
00087     #define __ARM_ARCH_7EM__  1
00088   #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
00089     #define __ARM_ARCH_8M_BASE__ 1
00090   #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
00091     #define __ARM_ARCH_8M_MAIN__ 1
00092   #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
00093     #define __ARM_ARCH_8M_MAIN__ 1
00094   #else
00095     #error "Unknown target."
00096   #endif
00097 #endif
00098 
00099 
00100 
00101 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
00102   #define __IAR_M0_FAMILY  1
00103 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
00104   #define __IAR_M0_FAMILY  1
00105 #else
00106   #define __IAR_M0_FAMILY  0
00107 #endif
00108 
00109 
00110 #ifndef __ASM
00111   #define __ASM __asm
00112 #endif
00113 
00114 #ifndef   __COMPILER_BARRIER
00115   #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
00116 #endif
00117 
00118 #ifndef __INLINE
00119   #define __INLINE inline
00120 #endif
00121 
00122 #ifndef   __NO_RETURN
00123   #if __ICCARM_V8
00124     #define __NO_RETURN __attribute__((__noreturn__))
00125   #else
00126     #define __NO_RETURN _Pragma("object_attribute=__noreturn")
00127   #endif
00128 #endif
00129 
00130 #ifndef   __PACKED
00131   #if __ICCARM_V8
00132     #define __PACKED __attribute__((packed, aligned(1)))
00133   #else
00134     /* Needs IAR language extensions */
00135     #define __PACKED __packed
00136   #endif
00137 #endif
00138 
00139 #ifndef   __PACKED_STRUCT
00140   #if __ICCARM_V8
00141     #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
00142   #else
00143     /* Needs IAR language extensions */
00144     #define __PACKED_STRUCT __packed struct
00145   #endif
00146 #endif
00147 
00148 #ifndef   __PACKED_UNION
00149   #if __ICCARM_V8
00150     #define __PACKED_UNION union __attribute__((packed, aligned(1)))
00151   #else
00152     /* Needs IAR language extensions */
00153     #define __PACKED_UNION __packed union
00154   #endif
00155 #endif
00156 
00157 #ifndef   __RESTRICT
00158   #if __ICCARM_V8
00159     #define __RESTRICT            __restrict
00160   #else
00161     /* Needs IAR language extensions */
00162     #define __RESTRICT            restrict
00163   #endif
00164 #endif
00165 
00166 #ifndef   __STATIC_INLINE
00167   #define __STATIC_INLINE       static inline
00168 #endif
00169 
00170 #ifndef   __FORCEINLINE
00171   #define __FORCEINLINE         _Pragma("inline=forced")
00172 #endif
00173 
00174 #ifndef   __STATIC_FORCEINLINE
00175   #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
00176 #endif
00177 
00178 #ifndef __UNALIGNED_UINT16_READ
00179 #pragma language=save
00180 #pragma language=extended
00181 __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
00182 {
00183   return *(__packed uint16_t*)(ptr);
00184 }
00185 #pragma language=restore
00186 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
00187 #endif
00188 
00189 
00190 #ifndef __UNALIGNED_UINT16_WRITE
00191 #pragma language=save
00192 #pragma language=extended
00193 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
00194 {
00195   *(__packed uint16_t*)(ptr) = val;;
00196 }
00197 #pragma language=restore
00198 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
00199 #endif
00200 
00201 #ifndef __UNALIGNED_UINT32_READ
00202 #pragma language=save
00203 #pragma language=extended
00204 __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
00205 {
00206   return *(__packed uint32_t*)(ptr);
00207 }
00208 #pragma language=restore
00209 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
00210 #endif
00211 
00212 #ifndef __UNALIGNED_UINT32_WRITE
00213 #pragma language=save
00214 #pragma language=extended
00215 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
00216 {
00217   *(__packed uint32_t*)(ptr) = val;;
00218 }
00219 #pragma language=restore
00220 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
00221 #endif
00222 
00223 #ifndef __UNALIGNED_UINT32   /* deprecated */
00224 #pragma language=save
00225 #pragma language=extended
00226 __packed struct  __iar_u32 { uint32_t v; };
00227 #pragma language=restore
00228 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
00229 #endif
00230 
00231 #ifndef   __USED
00232   #if __ICCARM_V8
00233     #define __USED __attribute__((used))
00234   #else
00235     #define __USED _Pragma("__root")
00236   #endif
00237 #endif
00238 
00239 #ifndef   __WEAK
00240   #if __ICCARM_V8
00241     #define __WEAK __attribute__((weak))
00242   #else
00243     #define __WEAK _Pragma("__weak")
00244   #endif
00245 #endif
00246 
00247 #ifndef __PROGRAM_START
00248 #define __PROGRAM_START           __iar_program_start
00249 #endif
00250 
00251 #ifndef __INITIAL_SP
00252 #define __INITIAL_SP              CSTACK$$Limit
00253 #endif
00254 
00255 #ifndef __STACK_LIMIT
00256 #define __STACK_LIMIT             CSTACK$$Base
00257 #endif
00258 
00259 #ifndef __VECTOR_TABLE
00260 #define __VECTOR_TABLE            __vector_table
00261 #endif
00262 
00263 #ifndef __VECTOR_TABLE_ATTRIBUTE
00264 #define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
00265 #endif
00266 
00267 #ifndef __ICCARM_INTRINSICS_VERSION__
00268   #define __ICCARM_INTRINSICS_VERSION__  0
00269 #endif
00270 
00271 #if __ICCARM_INTRINSICS_VERSION__ == 2
00272 
00273   #if defined(__CLZ)
00274     #undef __CLZ
00275   #endif
00276   #if defined(__REVSH)
00277     #undef __REVSH
00278   #endif
00279   #if defined(__RBIT)
00280     #undef __RBIT
00281   #endif
00282   #if defined(__SSAT)
00283     #undef __SSAT
00284   #endif
00285   #if defined(__USAT)
00286     #undef __USAT
00287   #endif
00288 
00289   #include "iccarm_builtin.h"
00290 
00291   #define __disable_fault_irq __iar_builtin_disable_fiq
00292   #define __disable_irq       __iar_builtin_disable_interrupt
00293   #define __enable_fault_irq  __iar_builtin_enable_fiq
00294   #define __enable_irq        __iar_builtin_enable_interrupt
00295   #define __arm_rsr           __iar_builtin_rsr
00296   #define __arm_wsr           __iar_builtin_wsr
00297 
00298 
00299   #define __get_APSR()                (__arm_rsr("APSR"))
00300   #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
00301   #define __get_CONTROL()             (__arm_rsr("CONTROL"))
00302   #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
00303 
00304   #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
00305        (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
00306     #define __get_FPSCR()             (__arm_rsr("FPSCR"))
00307     #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
00308   #else
00309     #define __get_FPSCR()             ( 0 )
00310     #define __set_FPSCR(VALUE)        ((void)VALUE)
00311   #endif
00312 
00313   #define __get_IPSR()                (__arm_rsr("IPSR"))
00314   #define __get_MSP()                 (__arm_rsr("MSP"))
00315   #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
00316        (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
00317     // without main extensions, the non-secure MSPLIM is RAZ/WI
00318     #define __get_MSPLIM()            (0U)
00319   #else
00320     #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
00321   #endif
00322   #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
00323   #define __get_PSP()                 (__arm_rsr("PSP"))
00324 
00325   #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
00326        (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
00327     // without main extensions, the non-secure PSPLIM is RAZ/WI
00328     #define __get_PSPLIM()            (0U)
00329   #else
00330     #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
00331   #endif
00332 
00333   #define __get_xPSR()                (__arm_rsr("xPSR"))
00334 
00335   #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
00336   #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
00337   #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
00338   #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
00339   #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
00340 
00341   #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
00342        (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
00343     // without main extensions, the non-secure MSPLIM is RAZ/WI
00344     #define __set_MSPLIM(VALUE)       ((void)(VALUE))
00345   #else
00346     #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
00347   #endif
00348   #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
00349   #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
00350   #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
00351        (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
00352     // without main extensions, the non-secure PSPLIM is RAZ/WI
00353     #define __set_PSPLIM(VALUE)       ((void)(VALUE))
00354   #else
00355     #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
00356   #endif
00357 
00358   #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
00359   #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
00360   #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
00361   #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
00362   #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
00363   #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
00364   #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
00365   #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
00366   #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
00367   #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
00368   #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
00369   #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
00370   #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
00371   #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
00372 
00373   #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
00374        (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
00375     // without main extensions, the non-secure PSPLIM is RAZ/WI
00376     #define __TZ_get_PSPLIM_NS()      (0U)
00377     #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
00378   #else
00379     #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
00380     #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
00381   #endif
00382 
00383   #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
00384   #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
00385 
00386   #define __NOP     __iar_builtin_no_operation
00387 
00388   #define __CLZ     __iar_builtin_CLZ
00389   #define __CLREX   __iar_builtin_CLREX
00390 
00391   #define __DMB     __iar_builtin_DMB
00392   #define __DSB     __iar_builtin_DSB
00393   #define __ISB     __iar_builtin_ISB
00394 
00395   #define __LDREXB  __iar_builtin_LDREXB
00396   #define __LDREXH  __iar_builtin_LDREXH
00397   #define __LDREXW  __iar_builtin_LDREX
00398 
00399   #define __RBIT    __iar_builtin_RBIT
00400   #define __REV     __iar_builtin_REV
00401   #define __REV16   __iar_builtin_REV16
00402 
00403   __IAR_FT int16_t __REVSH(int16_t val)
00404   {
00405     return (int16_t) __iar_builtin_REVSH(val);
00406   }
00407 
00408   #define __ROR     __iar_builtin_ROR
00409   #define __RRX     __iar_builtin_RRX
00410 
00411   #define __SEV     __iar_builtin_SEV
00412 
00413   #if !__IAR_M0_FAMILY
00414     #define __SSAT    __iar_builtin_SSAT
00415   #endif
00416 
00417   #define __STREXB  __iar_builtin_STREXB
00418   #define __STREXH  __iar_builtin_STREXH
00419   #define __STREXW  __iar_builtin_STREX
00420 
00421   #if !__IAR_M0_FAMILY
00422     #define __USAT    __iar_builtin_USAT
00423   #endif
00424 
00425   #define __WFE     __iar_builtin_WFE
00426   #define __WFI     __iar_builtin_WFI
00427 
00428   #if __ARM_MEDIA__
00429     #define __SADD8   __iar_builtin_SADD8
00430     #define __QADD8   __iar_builtin_QADD8
00431     #define __SHADD8  __iar_builtin_SHADD8
00432     #define __UADD8   __iar_builtin_UADD8
00433     #define __UQADD8  __iar_builtin_UQADD8
00434     #define __UHADD8  __iar_builtin_UHADD8
00435     #define __SSUB8   __iar_builtin_SSUB8
00436     #define __QSUB8   __iar_builtin_QSUB8
00437     #define __SHSUB8  __iar_builtin_SHSUB8
00438     #define __USUB8   __iar_builtin_USUB8
00439     #define __UQSUB8  __iar_builtin_UQSUB8
00440     #define __UHSUB8  __iar_builtin_UHSUB8
00441     #define __SADD16  __iar_builtin_SADD16
00442     #define __QADD16  __iar_builtin_QADD16
00443     #define __SHADD16 __iar_builtin_SHADD16
00444     #define __UADD16  __iar_builtin_UADD16
00445     #define __UQADD16 __iar_builtin_UQADD16
00446     #define __UHADD16 __iar_builtin_UHADD16
00447     #define __SSUB16  __iar_builtin_SSUB16
00448     #define __QSUB16  __iar_builtin_QSUB16
00449     #define __SHSUB16 __iar_builtin_SHSUB16
00450     #define __USUB16  __iar_builtin_USUB16
00451     #define __UQSUB16 __iar_builtin_UQSUB16
00452     #define __UHSUB16 __iar_builtin_UHSUB16
00453     #define __SASX    __iar_builtin_SASX
00454     #define __QASX    __iar_builtin_QASX
00455     #define __SHASX   __iar_builtin_SHASX
00456     #define __UASX    __iar_builtin_UASX
00457     #define __UQASX   __iar_builtin_UQASX
00458     #define __UHASX   __iar_builtin_UHASX
00459     #define __SSAX    __iar_builtin_SSAX
00460     #define __QSAX    __iar_builtin_QSAX
00461     #define __SHSAX   __iar_builtin_SHSAX
00462     #define __USAX    __iar_builtin_USAX
00463     #define __UQSAX   __iar_builtin_UQSAX
00464     #define __UHSAX   __iar_builtin_UHSAX
00465     #define __USAD8   __iar_builtin_USAD8
00466     #define __USADA8  __iar_builtin_USADA8
00467     #define __SSAT16  __iar_builtin_SSAT16
00468     #define __USAT16  __iar_builtin_USAT16
00469     #define __UXTB16  __iar_builtin_UXTB16
00470     #define __UXTAB16 __iar_builtin_UXTAB16
00471     #define __SXTB16  __iar_builtin_SXTB16
00472     #define __SXTAB16 __iar_builtin_SXTAB16
00473     #define __SMUAD   __iar_builtin_SMUAD
00474     #define __SMUADX  __iar_builtin_SMUADX
00475     #define __SMMLA   __iar_builtin_SMMLA
00476     #define __SMLAD   __iar_builtin_SMLAD
00477     #define __SMLADX  __iar_builtin_SMLADX
00478     #define __SMLALD  __iar_builtin_SMLALD
00479     #define __SMLALDX __iar_builtin_SMLALDX
00480     #define __SMUSD   __iar_builtin_SMUSD
00481     #define __SMUSDX  __iar_builtin_SMUSDX
00482     #define __SMLSD   __iar_builtin_SMLSD
00483     #define __SMLSDX  __iar_builtin_SMLSDX
00484     #define __SMLSLD  __iar_builtin_SMLSLD
00485     #define __SMLSLDX __iar_builtin_SMLSLDX
00486     #define __SEL     __iar_builtin_SEL
00487     #define __QADD    __iar_builtin_QADD
00488     #define __QSUB    __iar_builtin_QSUB
00489     #define __PKHBT   __iar_builtin_PKHBT
00490     #define __PKHTB   __iar_builtin_PKHTB
00491   #endif
00492 
00493 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
00494 
00495   #if __IAR_M0_FAMILY
00496    /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
00497     #define __CLZ  __cmsis_iar_clz_not_active
00498     #define __SSAT __cmsis_iar_ssat_not_active
00499     #define __USAT __cmsis_iar_usat_not_active
00500     #define __RBIT __cmsis_iar_rbit_not_active
00501     #define __get_APSR  __cmsis_iar_get_APSR_not_active
00502   #endif
00503 
00504 
00505   #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
00506          (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
00507     #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
00508     #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
00509   #endif
00510 
00511   #ifdef __INTRINSICS_INCLUDED
00512   #error intrinsics.h is already included previously!
00513   #endif
00514 
00515   #include <intrinsics.h>
00516 
00517   #if __IAR_M0_FAMILY
00518    /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
00519     #undef __CLZ
00520     #undef __SSAT
00521     #undef __USAT
00522     #undef __RBIT
00523     #undef __get_APSR
00524 
00525     __STATIC_INLINE uint8_t __CLZ(uint32_t data)
00526     {
00527       if (data == 0U) { return 32U; }
00528 
00529       uint32_t count = 0U;
00530       uint32_t mask = 0x80000000U;
00531 
00532       while ((data & mask) == 0U)
00533       {
00534         count += 1U;
00535         mask = mask >> 1U;
00536       }
00537       return count;
00538     }
00539 
00540     __STATIC_INLINE uint32_t __RBIT(uint32_t v)
00541     {
00542       uint8_t sc = 31U;
00543       uint32_t r = v;
00544       for (v >>= 1U; v; v >>= 1U)
00545       {
00546         r <<= 1U;
00547         r |= v & 1U;
00548         sc--;
00549       }
00550       return (r << sc);
00551     }
00552 
00553     __STATIC_INLINE  uint32_t __get_APSR(void)
00554     {
00555       uint32_t res;
00556       __asm("MRS      %0,APSR" : "=r" (res));
00557       return res;
00558     }
00559 
00560   #endif
00561 
00562   #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
00563          (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
00564     #undef __get_FPSCR
00565     #undef __set_FPSCR
00566     #define __get_FPSCR()       (0)
00567     #define __set_FPSCR(VALUE)  ((void)VALUE)
00568   #endif
00569 
00570   #pragma diag_suppress=Pe940
00571   #pragma diag_suppress=Pe177
00572 
00573   #define __enable_irq    __enable_interrupt
00574   #define __disable_irq   __disable_interrupt
00575   #define __NOP           __no_operation
00576 
00577   #define __get_xPSR      __get_PSR
00578 
00579   #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
00580 
00581     __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
00582     {
00583       return __LDREX((unsigned long *)ptr);
00584     }
00585 
00586     __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
00587     {
00588       return __STREX(value, (unsigned long *)ptr);
00589     }
00590   #endif
00591 
00592 
00593   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
00594   #if (__CORTEX_M >= 0x03)
00595 
00596     __IAR_FT uint32_t __RRX(uint32_t value)
00597     {
00598       uint32_t result;
00599       __ASM volatile("RRX      %0, %1" : "=r"(result) : "r" (value));
00600       return(result);
00601     }
00602 
00603     __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
00604     {
00605       __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
00606     }
00607 
00608 
00609     #define __enable_fault_irq  __enable_fiq
00610     #define __disable_fault_irq __disable_fiq
00611 
00612 
00613   #endif /* (__CORTEX_M >= 0x03) */
00614 
00615   __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
00616   {
00617     return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
00618   }
00619 
00620   #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
00621        (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
00622 
00623    __IAR_FT uint32_t __get_MSPLIM(void)
00624     {
00625       uint32_t res;
00626     #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
00627          (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
00628       // without main extensions, the non-secure MSPLIM is RAZ/WI
00629       res = 0U;
00630     #else
00631       __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
00632     #endif
00633       return res;
00634     }
00635 
00636     __IAR_FT void   __set_MSPLIM(uint32_t value)
00637     {
00638     #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
00639          (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
00640       // without main extensions, the non-secure MSPLIM is RAZ/WI
00641       (void)value;
00642     #else
00643       __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
00644     #endif
00645     }
00646 
00647     __IAR_FT uint32_t __get_PSPLIM(void)
00648     {
00649       uint32_t res;
00650     #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
00651          (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
00652       // without main extensions, the non-secure PSPLIM is RAZ/WI
00653       res = 0U;
00654     #else
00655       __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
00656     #endif
00657       return res;
00658     }
00659 
00660     __IAR_FT void   __set_PSPLIM(uint32_t value)
00661     {
00662     #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
00663          (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
00664       // without main extensions, the non-secure PSPLIM is RAZ/WI
00665       (void)value;
00666     #else
00667       __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
00668     #endif
00669     }
00670 
00671     __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
00672     {
00673       uint32_t res;
00674       __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
00675       return res;
00676     }
00677 
00678     __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
00679     {
00680       __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
00681     }
00682 
00683     __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
00684     {
00685       uint32_t res;
00686       __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
00687       return res;
00688     }
00689 
00690     __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
00691     {
00692       __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
00693     }
00694 
00695     __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
00696     {
00697       uint32_t res;
00698       __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
00699       return res;
00700     }
00701 
00702     __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
00703     {
00704       __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
00705     }
00706 
00707     __IAR_FT uint32_t   __TZ_get_SP_NS(void)
00708     {
00709       uint32_t res;
00710       __asm volatile("MRS      %0,SP_NS" : "=r" (res));
00711       return res;
00712     }
00713     __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
00714     {
00715       __asm volatile("MSR      SP_NS,%0" :: "r" (value));
00716     }
00717 
00718     __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
00719     {
00720       uint32_t res;
00721       __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
00722       return res;
00723     }
00724 
00725     __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
00726     {
00727       __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
00728     }
00729 
00730     __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
00731     {
00732       uint32_t res;
00733       __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
00734       return res;
00735     }
00736 
00737     __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
00738     {
00739       __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
00740     }
00741 
00742     __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
00743     {
00744       uint32_t res;
00745       __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
00746       return res;
00747     }
00748 
00749     __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
00750     {
00751       __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
00752     }
00753 
00754     __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
00755     {
00756       uint32_t res;
00757     #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
00758          (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
00759       // without main extensions, the non-secure PSPLIM is RAZ/WI
00760       res = 0U;
00761     #else
00762       __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
00763     #endif
00764       return res;
00765     }
00766 
00767     __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
00768     {
00769     #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
00770          (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
00771       // without main extensions, the non-secure PSPLIM is RAZ/WI
00772       (void)value;
00773     #else
00774       __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
00775     #endif
00776     }
00777 
00778     __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
00779     {
00780       uint32_t res;
00781       __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
00782       return res;
00783     }
00784 
00785     __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
00786     {
00787       __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
00788     }
00789 
00790   #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
00791 
00792 #endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
00793 
00794 #define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
00795 
00796 #if __IAR_M0_FAMILY
00797   __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
00798   {
00799     if ((sat >= 1U) && (sat <= 32U))
00800     {
00801       const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
00802       const int32_t min = -1 - max ;
00803       if (val > max)
00804       {
00805         return max;
00806       }
00807       else if (val < min)
00808       {
00809         return min;
00810       }
00811     }
00812     return val;
00813   }
00814 
00815   __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
00816   {
00817     if (sat <= 31U)
00818     {
00819       const uint32_t max = ((1U << sat) - 1U);
00820       if (val > (int32_t)max)
00821       {
00822         return max;
00823       }
00824       else if (val < 0)
00825       {
00826         return 0U;
00827       }
00828     }
00829     return (uint32_t)val;
00830   }
00831 #endif
00832 
00833 #if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
00834 
00835   __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
00836   {
00837     uint32_t res;
00838     __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
00839     return ((uint8_t)res);
00840   }
00841 
00842   __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
00843   {
00844     uint32_t res;
00845     __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
00846     return ((uint16_t)res);
00847   }
00848 
00849   __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
00850   {
00851     uint32_t res;
00852     __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
00853     return res;
00854   }
00855 
00856   __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
00857   {
00858     __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
00859   }
00860 
00861   __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
00862   {
00863     __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
00864   }
00865 
00866   __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
00867   {
00868     __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
00869   }
00870 
00871 #endif /* (__CORTEX_M >= 0x03) */
00872 
00873 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
00874      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
00875 
00876 
00877   __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
00878   {
00879     uint32_t res;
00880     __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
00881     return ((uint8_t)res);
00882   }
00883 
00884   __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
00885   {
00886     uint32_t res;
00887     __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
00888     return ((uint16_t)res);
00889   }
00890 
00891   __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
00892   {
00893     uint32_t res;
00894     __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
00895     return res;
00896   }
00897 
00898   __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
00899   {
00900     __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
00901   }
00902 
00903   __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
00904   {
00905     __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
00906   }
00907 
00908   __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
00909   {
00910     __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
00911   }
00912 
00913   __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
00914   {
00915     uint32_t res;
00916     __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
00917     return ((uint8_t)res);
00918   }
00919 
00920   __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
00921   {
00922     uint32_t res;
00923     __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
00924     return ((uint16_t)res);
00925   }
00926 
00927   __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
00928   {
00929     uint32_t res;
00930     __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
00931     return res;
00932   }
00933 
00934   __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
00935   {
00936     uint32_t res;
00937     __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
00938     return res;
00939   }
00940 
00941   __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
00942   {
00943     uint32_t res;
00944     __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
00945     return res;
00946   }
00947 
00948   __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
00949   {
00950     uint32_t res;
00951     __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
00952     return res;
00953   }
00954 
00955 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
00956 
00957 #undef __IAR_FT
00958 #undef __IAR_M0_FAMILY
00959 #undef __ICCARM_V8
00960 
00961 #pragma diag_default=Pe940
00962 #pragma diag_default=Pe177
00963 
00964 #endif /* __CMSIS_ICCARM_H__ */