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cmsis_armclang.h
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00001 /**************************************************************************//** 00002 * @file cmsis_armclang.h 00003 * @brief CMSIS compiler armclang (Arm Compiler 6) header file 00004 * @version V5.2.1 00005 * @date 30. July 2019 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ 00026 00027 #ifndef __CMSIS_ARMCLANG_H 00028 #define __CMSIS_ARMCLANG_H 00029 00030 #pragma clang system_header /* treat file as system include file */ 00031 00032 #ifndef __ARM_COMPAT_H 00033 #include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */ 00034 #endif 00035 00036 /* CMSIS compiler specific defines */ 00037 #ifndef __ASM 00038 #define __ASM __asm 00039 #endif 00040 #ifndef __INLINE 00041 #define __INLINE __inline 00042 #endif 00043 #ifndef __STATIC_INLINE 00044 #define __STATIC_INLINE static __inline 00045 #endif 00046 #ifndef __STATIC_FORCEINLINE 00047 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline 00048 #endif 00049 #ifndef __NO_RETURN 00050 #define __NO_RETURN __attribute__((__noreturn__)) 00051 #endif 00052 #ifndef __USED 00053 #define __USED __attribute__((used)) 00054 #endif 00055 #ifndef __WEAK 00056 #define __WEAK __attribute__((weak)) 00057 #endif 00058 #ifndef __PACKED 00059 #define __PACKED __attribute__((packed, aligned(1))) 00060 #endif 00061 #ifndef __PACKED_STRUCT 00062 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 00063 #endif 00064 #ifndef __PACKED_UNION 00065 #define __PACKED_UNION union __attribute__((packed, aligned(1))) 00066 #endif 00067 #ifndef __UNALIGNED_UINT32 /* deprecated */ 00068 #pragma clang diagnostic push 00069 #pragma clang diagnostic ignored "-Wpacked" 00070 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ 00071 struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 00072 #pragma clang diagnostic pop 00073 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 00074 #endif 00075 #ifndef __UNALIGNED_UINT16_WRITE 00076 #pragma clang diagnostic push 00077 #pragma clang diagnostic ignored "-Wpacked" 00078 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ 00079 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 00080 #pragma clang diagnostic pop 00081 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 00082 #endif 00083 #ifndef __UNALIGNED_UINT16_READ 00084 #pragma clang diagnostic push 00085 #pragma clang diagnostic ignored "-Wpacked" 00086 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ 00087 __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 00088 #pragma clang diagnostic pop 00089 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 00090 #endif 00091 #ifndef __UNALIGNED_UINT32_WRITE 00092 #pragma clang diagnostic push 00093 #pragma clang diagnostic ignored "-Wpacked" 00094 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ 00095 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 00096 #pragma clang diagnostic pop 00097 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 00098 #endif 00099 #ifndef __UNALIGNED_UINT32_READ 00100 #pragma clang diagnostic push 00101 #pragma clang diagnostic ignored "-Wpacked" 00102 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ 00103 __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 00104 #pragma clang diagnostic pop 00105 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 00106 #endif 00107 #ifndef __ALIGNED 00108 #define __ALIGNED(x) __attribute__((aligned(x))) 00109 #endif 00110 #ifndef __RESTRICT 00111 #define __RESTRICT __restrict 00112 #endif 00113 #ifndef __COMPILER_BARRIER 00114 #define __COMPILER_BARRIER() __ASM volatile("":::"memory") 00115 #endif 00116 00117 /* ######################### Startup and Lowlevel Init ######################## */ 00118 00119 #ifndef __PROGRAM_START 00120 #define __PROGRAM_START __main 00121 #endif 00122 00123 #ifndef __INITIAL_SP 00124 #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit 00125 #endif 00126 00127 #ifndef __STACK_LIMIT 00128 #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base 00129 #endif 00130 00131 #ifndef __VECTOR_TABLE 00132 #define __VECTOR_TABLE __Vectors 00133 #endif 00134 00135 #ifndef __VECTOR_TABLE_ATTRIBUTE 00136 #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) 00137 #endif 00138 00139 /* ########################### Core Function Access ########################### */ 00140 /** \ingroup CMSIS_Core_FunctionInterface 00141 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 00142 @{ 00143 */ 00144 00145 /** 00146 \brief Enable IRQ Interrupts 00147 \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 00148 Can only be executed in Privileged modes. 00149 */ 00150 /* intrinsic void __enable_irq(); see arm_compat.h */ 00151 00152 00153 /** 00154 \brief Disable IRQ Interrupts 00155 \details Disables IRQ interrupts by setting the I-bit in the CPSR. 00156 Can only be executed in Privileged modes. 00157 */ 00158 /* intrinsic void __disable_irq(); see arm_compat.h */ 00159 00160 00161 /** 00162 \brief Get Control Register 00163 \details Returns the content of the Control Register. 00164 \return Control Register value 00165 */ 00166 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 00167 { 00168 uint32_t result; 00169 00170 __ASM volatile ("MRS %0, control" : "=r" (result) ); 00171 return(result); 00172 } 00173 00174 00175 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00176 /** 00177 \brief Get Control Register (non-secure) 00178 \details Returns the content of the non-secure Control Register when in secure mode. 00179 \return non-secure Control Register value 00180 */ 00181 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 00182 { 00183 uint32_t result; 00184 00185 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 00186 return(result); 00187 } 00188 #endif 00189 00190 00191 /** 00192 \brief Set Control Register 00193 \details Writes the given value to the Control Register. 00194 \param [in] control Control Register value to set 00195 */ 00196 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 00197 { 00198 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 00199 } 00200 00201 00202 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00203 /** 00204 \brief Set Control Register (non-secure) 00205 \details Writes the given value to the non-secure Control Register when in secure state. 00206 \param [in] control Control Register value to set 00207 */ 00208 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 00209 { 00210 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 00211 } 00212 #endif 00213 00214 00215 /** 00216 \brief Get IPSR Register 00217 \details Returns the content of the IPSR Register. 00218 \return IPSR Register value 00219 */ 00220 __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 00221 { 00222 uint32_t result; 00223 00224 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 00225 return(result); 00226 } 00227 00228 00229 /** 00230 \brief Get APSR Register 00231 \details Returns the content of the APSR Register. 00232 \return APSR Register value 00233 */ 00234 __STATIC_FORCEINLINE uint32_t __get_APSR(void) 00235 { 00236 uint32_t result; 00237 00238 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 00239 return(result); 00240 } 00241 00242 00243 /** 00244 \brief Get xPSR Register 00245 \details Returns the content of the xPSR Register. 00246 \return xPSR Register value 00247 */ 00248 __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 00249 { 00250 uint32_t result; 00251 00252 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 00253 return(result); 00254 } 00255 00256 00257 /** 00258 \brief Get Process Stack Pointer 00259 \details Returns the current value of the Process Stack Pointer (PSP). 00260 \return PSP Register value 00261 */ 00262 __STATIC_FORCEINLINE uint32_t __get_PSP(void) 00263 { 00264 uint32_t result; 00265 00266 __ASM volatile ("MRS %0, psp" : "=r" (result) ); 00267 return(result); 00268 } 00269 00270 00271 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00272 /** 00273 \brief Get Process Stack Pointer (non-secure) 00274 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. 00275 \return PSP Register value 00276 */ 00277 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 00278 { 00279 uint32_t result; 00280 00281 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 00282 return(result); 00283 } 00284 #endif 00285 00286 00287 /** 00288 \brief Set Process Stack Pointer 00289 \details Assigns the given value to the Process Stack Pointer (PSP). 00290 \param [in] topOfProcStack Process Stack Pointer value to set 00291 */ 00292 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 00293 { 00294 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 00295 } 00296 00297 00298 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00299 /** 00300 \brief Set Process Stack Pointer (non-secure) 00301 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. 00302 \param [in] topOfProcStack Process Stack Pointer value to set 00303 */ 00304 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 00305 { 00306 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 00307 } 00308 #endif 00309 00310 00311 /** 00312 \brief Get Main Stack Pointer 00313 \details Returns the current value of the Main Stack Pointer (MSP). 00314 \return MSP Register value 00315 */ 00316 __STATIC_FORCEINLINE uint32_t __get_MSP(void) 00317 { 00318 uint32_t result; 00319 00320 __ASM volatile ("MRS %0, msp" : "=r" (result) ); 00321 return(result); 00322 } 00323 00324 00325 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00326 /** 00327 \brief Get Main Stack Pointer (non-secure) 00328 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. 00329 \return MSP Register value 00330 */ 00331 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 00332 { 00333 uint32_t result; 00334 00335 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 00336 return(result); 00337 } 00338 #endif 00339 00340 00341 /** 00342 \brief Set Main Stack Pointer 00343 \details Assigns the given value to the Main Stack Pointer (MSP). 00344 \param [in] topOfMainStack Main Stack Pointer value to set 00345 */ 00346 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 00347 { 00348 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 00349 } 00350 00351 00352 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00353 /** 00354 \brief Set Main Stack Pointer (non-secure) 00355 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 00356 \param [in] topOfMainStack Main Stack Pointer value to set 00357 */ 00358 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 00359 { 00360 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 00361 } 00362 #endif 00363 00364 00365 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00366 /** 00367 \brief Get Stack Pointer (non-secure) 00368 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 00369 \return SP Register value 00370 */ 00371 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 00372 { 00373 uint32_t result; 00374 00375 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 00376 return(result); 00377 } 00378 00379 00380 /** 00381 \brief Set Stack Pointer (non-secure) 00382 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 00383 \param [in] topOfStack Stack Pointer value to set 00384 */ 00385 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 00386 { 00387 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 00388 } 00389 #endif 00390 00391 00392 /** 00393 \brief Get Priority Mask 00394 \details Returns the current state of the priority mask bit from the Priority Mask Register. 00395 \return Priority Mask value 00396 */ 00397 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 00398 { 00399 uint32_t result; 00400 00401 __ASM volatile ("MRS %0, primask" : "=r" (result) ); 00402 return(result); 00403 } 00404 00405 00406 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00407 /** 00408 \brief Get Priority Mask (non-secure) 00409 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. 00410 \return Priority Mask value 00411 */ 00412 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 00413 { 00414 uint32_t result; 00415 00416 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); 00417 return(result); 00418 } 00419 #endif 00420 00421 00422 /** 00423 \brief Set Priority Mask 00424 \details Assigns the given value to the Priority Mask Register. 00425 \param [in] priMask Priority Mask 00426 */ 00427 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 00428 { 00429 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 00430 } 00431 00432 00433 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00434 /** 00435 \brief Set Priority Mask (non-secure) 00436 \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 00437 \param [in] priMask Priority Mask 00438 */ 00439 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 00440 { 00441 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 00442 } 00443 #endif 00444 00445 00446 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 00447 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 00448 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 00449 /** 00450 \brief Enable FIQ 00451 \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 00452 Can only be executed in Privileged modes. 00453 */ 00454 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */ 00455 00456 00457 /** 00458 \brief Disable FIQ 00459 \details Disables FIQ interrupts by setting the F-bit in the CPSR. 00460 Can only be executed in Privileged modes. 00461 */ 00462 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */ 00463 00464 00465 /** 00466 \brief Get Base Priority 00467 \details Returns the current value of the Base Priority register. 00468 \return Base Priority register value 00469 */ 00470 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 00471 { 00472 uint32_t result; 00473 00474 __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 00475 return(result); 00476 } 00477 00478 00479 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00480 /** 00481 \brief Get Base Priority (non-secure) 00482 \details Returns the current value of the non-secure Base Priority register when in secure state. 00483 \return Base Priority register value 00484 */ 00485 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 00486 { 00487 uint32_t result; 00488 00489 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 00490 return(result); 00491 } 00492 #endif 00493 00494 00495 /** 00496 \brief Set Base Priority 00497 \details Assigns the given value to the Base Priority register. 00498 \param [in] basePri Base Priority value to set 00499 */ 00500 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 00501 { 00502 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 00503 } 00504 00505 00506 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00507 /** 00508 \brief Set Base Priority (non-secure) 00509 \details Assigns the given value to the non-secure Base Priority register when in secure state. 00510 \param [in] basePri Base Priority value to set 00511 */ 00512 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 00513 { 00514 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 00515 } 00516 #endif 00517 00518 00519 /** 00520 \brief Set Base Priority with condition 00521 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, 00522 or the new value increases the BASEPRI priority level. 00523 \param [in] basePri Base Priority value to set 00524 */ 00525 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 00526 { 00527 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 00528 } 00529 00530 00531 /** 00532 \brief Get Fault Mask 00533 \details Returns the current value of the Fault Mask register. 00534 \return Fault Mask register value 00535 */ 00536 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 00537 { 00538 uint32_t result; 00539 00540 __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 00541 return(result); 00542 } 00543 00544 00545 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00546 /** 00547 \brief Get Fault Mask (non-secure) 00548 \details Returns the current value of the non-secure Fault Mask register when in secure state. 00549 \return Fault Mask register value 00550 */ 00551 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 00552 { 00553 uint32_t result; 00554 00555 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 00556 return(result); 00557 } 00558 #endif 00559 00560 00561 /** 00562 \brief Set Fault Mask 00563 \details Assigns the given value to the Fault Mask register. 00564 \param [in] faultMask Fault Mask value to set 00565 */ 00566 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 00567 { 00568 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 00569 } 00570 00571 00572 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00573 /** 00574 \brief Set Fault Mask (non-secure) 00575 \details Assigns the given value to the non-secure Fault Mask register when in secure state. 00576 \param [in] faultMask Fault Mask value to set 00577 */ 00578 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 00579 { 00580 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 00581 } 00582 #endif 00583 00584 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 00585 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 00586 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 00587 00588 00589 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 00590 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 00591 00592 /** 00593 \brief Get Process Stack Pointer Limit 00594 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 00595 Stack Pointer Limit register hence zero is returned always in non-secure 00596 mode. 00597 00598 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 00599 \return PSPLIM Register value 00600 */ 00601 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 00602 { 00603 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00604 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 00605 // without main extensions, the non-secure PSPLIM is RAZ/WI 00606 return 0U; 00607 #else 00608 uint32_t result; 00609 __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 00610 return result; 00611 #endif 00612 } 00613 00614 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 00615 /** 00616 \brief Get Process Stack Pointer Limit (non-secure) 00617 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 00618 Stack Pointer Limit register hence zero is returned always in non-secure 00619 mode. 00620 00621 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. 00622 \return PSPLIM Register value 00623 */ 00624 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 00625 { 00626 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 00627 // without main extensions, the non-secure PSPLIM is RAZ/WI 00628 return 0U; 00629 #else 00630 uint32_t result; 00631 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 00632 return result; 00633 #endif 00634 } 00635 #endif 00636 00637 00638 /** 00639 \brief Set Process Stack Pointer Limit 00640 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 00641 Stack Pointer Limit register hence the write is silently ignored in non-secure 00642 mode. 00643 00644 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 00645 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 00646 */ 00647 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 00648 { 00649 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00650 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 00651 // without main extensions, the non-secure PSPLIM is RAZ/WI 00652 (void)ProcStackPtrLimit; 00653 #else 00654 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 00655 #endif 00656 } 00657 00658 00659 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00660 /** 00661 \brief Set Process Stack Pointer (non-secure) 00662 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 00663 Stack Pointer Limit register hence the write is silently ignored in non-secure 00664 mode. 00665 00666 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. 00667 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 00668 */ 00669 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 00670 { 00671 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 00672 // without main extensions, the non-secure PSPLIM is RAZ/WI 00673 (void)ProcStackPtrLimit; 00674 #else 00675 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 00676 #endif 00677 } 00678 #endif 00679 00680 00681 /** 00682 \brief Get Main Stack Pointer Limit 00683 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 00684 Stack Pointer Limit register hence zero is returned always. 00685 00686 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 00687 \return MSPLIM Register value 00688 */ 00689 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 00690 { 00691 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00692 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 00693 // without main extensions, the non-secure MSPLIM is RAZ/WI 00694 return 0U; 00695 #else 00696 uint32_t result; 00697 __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 00698 return result; 00699 #endif 00700 } 00701 00702 00703 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00704 /** 00705 \brief Get Main Stack Pointer Limit (non-secure) 00706 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 00707 Stack Pointer Limit register hence zero is returned always. 00708 00709 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. 00710 \return MSPLIM Register value 00711 */ 00712 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 00713 { 00714 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 00715 // without main extensions, the non-secure MSPLIM is RAZ/WI 00716 return 0U; 00717 #else 00718 uint32_t result; 00719 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 00720 return result; 00721 #endif 00722 } 00723 #endif 00724 00725 00726 /** 00727 \brief Set Main Stack Pointer Limit 00728 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 00729 Stack Pointer Limit register hence the write is silently ignored. 00730 00731 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 00732 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 00733 */ 00734 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 00735 { 00736 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00737 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 00738 // without main extensions, the non-secure MSPLIM is RAZ/WI 00739 (void)MainStackPtrLimit; 00740 #else 00741 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 00742 #endif 00743 } 00744 00745 00746 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 00747 /** 00748 \brief Set Main Stack Pointer Limit (non-secure) 00749 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 00750 Stack Pointer Limit register hence the write is silently ignored. 00751 00752 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. 00753 \param [in] MainStackPtrLimit Main Stack Pointer value to set 00754 */ 00755 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 00756 { 00757 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 00758 // without main extensions, the non-secure MSPLIM is RAZ/WI 00759 (void)MainStackPtrLimit; 00760 #else 00761 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 00762 #endif 00763 } 00764 #endif 00765 00766 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 00767 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 00768 00769 /** 00770 \brief Get FPSCR 00771 \details Returns the current value of the Floating Point Status/Control register. 00772 \return Floating Point Status/Control register value 00773 */ 00774 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 00775 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 00776 #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr 00777 #else 00778 #define __get_FPSCR() ((uint32_t)0U) 00779 #endif 00780 00781 /** 00782 \brief Set FPSCR 00783 \details Assigns the given value to the Floating Point Status/Control register. 00784 \param [in] fpscr Floating Point Status/Control value to set 00785 */ 00786 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 00787 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 00788 #define __set_FPSCR __builtin_arm_set_fpscr 00789 #else 00790 #define __set_FPSCR(x) ((void)(x)) 00791 #endif 00792 00793 00794 /*@} end of CMSIS_Core_RegAccFunctions */ 00795 00796 00797 /* ########################## Core Instruction Access ######################### */ 00798 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 00799 Access to dedicated instructions 00800 @{ 00801 */ 00802 00803 /* Define macros for porting to both thumb1 and thumb2. 00804 * For thumb1, use low register (r0-r7), specified by constraint "l" 00805 * Otherwise, use general registers, specified by constraint "r" */ 00806 #if defined (__thumb__) && !defined (__thumb2__) 00807 #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 00808 #define __CMSIS_GCC_RW_REG(r) "+l" (r) 00809 #define __CMSIS_GCC_USE_REG(r) "l" (r) 00810 #else 00811 #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 00812 #define __CMSIS_GCC_RW_REG(r) "+r" (r) 00813 #define __CMSIS_GCC_USE_REG(r) "r" (r) 00814 #endif 00815 00816 /** 00817 \brief No Operation 00818 \details No Operation does nothing. This instruction can be used for code alignment purposes. 00819 */ 00820 #define __NOP __builtin_arm_nop 00821 00822 /** 00823 \brief Wait For Interrupt 00824 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. 00825 */ 00826 #define __WFI __builtin_arm_wfi 00827 00828 00829 /** 00830 \brief Wait For Event 00831 \details Wait For Event is a hint instruction that permits the processor to enter 00832 a low-power state until one of a number of events occurs. 00833 */ 00834 #define __WFE __builtin_arm_wfe 00835 00836 00837 /** 00838 \brief Send Event 00839 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 00840 */ 00841 #define __SEV __builtin_arm_sev 00842 00843 00844 /** 00845 \brief Instruction Synchronization Barrier 00846 \details Instruction Synchronization Barrier flushes the pipeline in the processor, 00847 so that all instructions following the ISB are fetched from cache or memory, 00848 after the instruction has been completed. 00849 */ 00850 #define __ISB() __builtin_arm_isb(0xF) 00851 00852 /** 00853 \brief Data Synchronization Barrier 00854 \details Acts as a special kind of Data Memory Barrier. 00855 It completes when all explicit memory accesses before this instruction complete. 00856 */ 00857 #define __DSB() __builtin_arm_dsb(0xF) 00858 00859 00860 /** 00861 \brief Data Memory Barrier 00862 \details Ensures the apparent order of the explicit memory operations before 00863 and after the instruction, without ensuring their completion. 00864 */ 00865 #define __DMB() __builtin_arm_dmb(0xF) 00866 00867 00868 /** 00869 \brief Reverse byte order (32 bit) 00870 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. 00871 \param [in] value Value to reverse 00872 \return Reversed value 00873 */ 00874 #define __REV(value) __builtin_bswap32(value) 00875 00876 00877 /** 00878 \brief Reverse byte order (16 bit) 00879 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. 00880 \param [in] value Value to reverse 00881 \return Reversed value 00882 */ 00883 #define __REV16(value) __ROR(__REV(value), 16) 00884 00885 00886 /** 00887 \brief Reverse byte order (16 bit) 00888 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. 00889 \param [in] value Value to reverse 00890 \return Reversed value 00891 */ 00892 #define __REVSH(value) (int16_t)__builtin_bswap16(value) 00893 00894 00895 /** 00896 \brief Rotate Right in unsigned value (32 bit) 00897 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 00898 \param [in] op1 Value to rotate 00899 \param [in] op2 Number of Bits to rotate 00900 \return Rotated value 00901 */ 00902 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 00903 { 00904 op2 %= 32U; 00905 if (op2 == 0U) 00906 { 00907 return op1; 00908 } 00909 return (op1 >> op2) | (op1 << (32U - op2)); 00910 } 00911 00912 00913 /** 00914 \brief Breakpoint 00915 \details Causes the processor to enter Debug state. 00916 Debug tools can use this to investigate system state when the instruction at a particular address is reached. 00917 \param [in] value is ignored by the processor. 00918 If required, a debugger can use it to store additional information about the breakpoint. 00919 */ 00920 #define __BKPT(value) __ASM volatile ("bkpt "#value) 00921 00922 00923 /** 00924 \brief Reverse bit order of value 00925 \details Reverses the bit order of the given value. 00926 \param [in] value Value to reverse 00927 \return Reversed value 00928 */ 00929 #define __RBIT __builtin_arm_rbit 00930 00931 /** 00932 \brief Count leading zeros 00933 \details Counts the number of leading zeros of a data value. 00934 \param [in] value Value to count the leading zeros 00935 \return number of leading zeros in value 00936 */ 00937 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) 00938 { 00939 /* Even though __builtin_clz produces a CLZ instruction on ARM, formally 00940 __builtin_clz(0) is undefined behaviour, so handle this case specially. 00941 This guarantees ARM-compatible results if happening to compile on a non-ARM 00942 target, and ensures the compiler doesn't decide to activate any 00943 optimisations using the logic "value was passed to __builtin_clz, so it 00944 is non-zero". 00945 ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a 00946 single CLZ instruction. 00947 */ 00948 if (value == 0U) 00949 { 00950 return 32U; 00951 } 00952 return __builtin_clz(value); 00953 } 00954 00955 00956 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 00957 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 00958 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 00959 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 00960 /** 00961 \brief LDR Exclusive (8 bit) 00962 \details Executes a exclusive LDR instruction for 8 bit value. 00963 \param [in] ptr Pointer to data 00964 \return value of type uint8_t at (*ptr) 00965 */ 00966 #define __LDREXB (uint8_t)__builtin_arm_ldrex 00967 00968 00969 /** 00970 \brief LDR Exclusive (16 bit) 00971 \details Executes a exclusive LDR instruction for 16 bit values. 00972 \param [in] ptr Pointer to data 00973 \return value of type uint16_t at (*ptr) 00974 */ 00975 #define __LDREXH (uint16_t)__builtin_arm_ldrex 00976 00977 00978 /** 00979 \brief LDR Exclusive (32 bit) 00980 \details Executes a exclusive LDR instruction for 32 bit values. 00981 \param [in] ptr Pointer to data 00982 \return value of type uint32_t at (*ptr) 00983 */ 00984 #define __LDREXW (uint32_t)__builtin_arm_ldrex 00985 00986 00987 /** 00988 \brief STR Exclusive (8 bit) 00989 \details Executes a exclusive STR instruction for 8 bit values. 00990 \param [in] value Value to store 00991 \param [in] ptr Pointer to location 00992 \return 0 Function succeeded 00993 \return 1 Function failed 00994 */ 00995 #define __STREXB (uint32_t)__builtin_arm_strex 00996 00997 00998 /** 00999 \brief STR Exclusive (16 bit) 01000 \details Executes a exclusive STR instruction for 16 bit values. 01001 \param [in] value Value to store 01002 \param [in] ptr Pointer to location 01003 \return 0 Function succeeded 01004 \return 1 Function failed 01005 */ 01006 #define __STREXH (uint32_t)__builtin_arm_strex 01007 01008 01009 /** 01010 \brief STR Exclusive (32 bit) 01011 \details Executes a exclusive STR instruction for 32 bit values. 01012 \param [in] value Value to store 01013 \param [in] ptr Pointer to location 01014 \return 0 Function succeeded 01015 \return 1 Function failed 01016 */ 01017 #define __STREXW (uint32_t)__builtin_arm_strex 01018 01019 01020 /** 01021 \brief Remove the exclusive lock 01022 \details Removes the exclusive lock which is created by LDREX. 01023 */ 01024 #define __CLREX __builtin_arm_clrex 01025 01026 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 01027 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 01028 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 01029 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 01030 01031 01032 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 01033 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 01034 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 01035 01036 /** 01037 \brief Signed Saturate 01038 \details Saturates a signed value. 01039 \param [in] value Value to be saturated 01040 \param [in] sat Bit position to saturate to (1..32) 01041 \return Saturated value 01042 */ 01043 #define __SSAT __builtin_arm_ssat 01044 01045 01046 /** 01047 \brief Unsigned Saturate 01048 \details Saturates an unsigned value. 01049 \param [in] value Value to be saturated 01050 \param [in] sat Bit position to saturate to (0..31) 01051 \return Saturated value 01052 */ 01053 #define __USAT __builtin_arm_usat 01054 01055 01056 /** 01057 \brief Rotate Right with Extend (32 bit) 01058 \details Moves each bit of a bitstring right by one bit. 01059 The carry input is shifted in at the left end of the bitstring. 01060 \param [in] value Value to rotate 01061 \return Rotated value 01062 */ 01063 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) 01064 { 01065 uint32_t result; 01066 01067 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 01068 return(result); 01069 } 01070 01071 01072 /** 01073 \brief LDRT Unprivileged (8 bit) 01074 \details Executes a Unprivileged LDRT instruction for 8 bit value. 01075 \param [in] ptr Pointer to data 01076 \return value of type uint8_t at (*ptr) 01077 */ 01078 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) 01079 { 01080 uint32_t result; 01081 01082 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); 01083 return ((uint8_t) result); /* Add explicit type cast here */ 01084 } 01085 01086 01087 /** 01088 \brief LDRT Unprivileged (16 bit) 01089 \details Executes a Unprivileged LDRT instruction for 16 bit values. 01090 \param [in] ptr Pointer to data 01091 \return value of type uint16_t at (*ptr) 01092 */ 01093 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) 01094 { 01095 uint32_t result; 01096 01097 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); 01098 return ((uint16_t) result); /* Add explicit type cast here */ 01099 } 01100 01101 01102 /** 01103 \brief LDRT Unprivileged (32 bit) 01104 \details Executes a Unprivileged LDRT instruction for 32 bit values. 01105 \param [in] ptr Pointer to data 01106 \return value of type uint32_t at (*ptr) 01107 */ 01108 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) 01109 { 01110 uint32_t result; 01111 01112 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); 01113 return(result); 01114 } 01115 01116 01117 /** 01118 \brief STRT Unprivileged (8 bit) 01119 \details Executes a Unprivileged STRT instruction for 8 bit values. 01120 \param [in] value Value to store 01121 \param [in] ptr Pointer to location 01122 */ 01123 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) 01124 { 01125 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 01126 } 01127 01128 01129 /** 01130 \brief STRT Unprivileged (16 bit) 01131 \details Executes a Unprivileged STRT instruction for 16 bit values. 01132 \param [in] value Value to store 01133 \param [in] ptr Pointer to location 01134 */ 01135 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) 01136 { 01137 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 01138 } 01139 01140 01141 /** 01142 \brief STRT Unprivileged (32 bit) 01143 \details Executes a Unprivileged STRT instruction for 32 bit values. 01144 \param [in] value Value to store 01145 \param [in] ptr Pointer to location 01146 */ 01147 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) 01148 { 01149 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); 01150 } 01151 01152 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 01153 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 01154 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 01155 01156 /** 01157 \brief Signed Saturate 01158 \details Saturates a signed value. 01159 \param [in] value Value to be saturated 01160 \param [in] sat Bit position to saturate to (1..32) 01161 \return Saturated value 01162 */ 01163 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) 01164 { 01165 if ((sat >= 1U) && (sat <= 32U)) 01166 { 01167 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 01168 const int32_t min = -1 - max ; 01169 if (val > max) 01170 { 01171 return max; 01172 } 01173 else if (val < min) 01174 { 01175 return min; 01176 } 01177 } 01178 return val; 01179 } 01180 01181 /** 01182 \brief Unsigned Saturate 01183 \details Saturates an unsigned value. 01184 \param [in] value Value to be saturated 01185 \param [in] sat Bit position to saturate to (0..31) 01186 \return Saturated value 01187 */ 01188 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) 01189 { 01190 if (sat <= 31U) 01191 { 01192 const uint32_t max = ((1U << sat) - 1U); 01193 if (val > (int32_t)max) 01194 { 01195 return max; 01196 } 01197 else if (val < 0) 01198 { 01199 return 0U; 01200 } 01201 } 01202 return (uint32_t)val; 01203 } 01204 01205 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 01206 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 01207 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 01208 01209 01210 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 01211 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 01212 /** 01213 \brief Load-Acquire (8 bit) 01214 \details Executes a LDAB instruction for 8 bit value. 01215 \param [in] ptr Pointer to data 01216 \return value of type uint8_t at (*ptr) 01217 */ 01218 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) 01219 { 01220 uint32_t result; 01221 01222 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 01223 return ((uint8_t) result); 01224 } 01225 01226 01227 /** 01228 \brief Load-Acquire (16 bit) 01229 \details Executes a LDAH instruction for 16 bit values. 01230 \param [in] ptr Pointer to data 01231 \return value of type uint16_t at (*ptr) 01232 */ 01233 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) 01234 { 01235 uint32_t result; 01236 01237 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 01238 return ((uint16_t) result); 01239 } 01240 01241 01242 /** 01243 \brief Load-Acquire (32 bit) 01244 \details Executes a LDA instruction for 32 bit values. 01245 \param [in] ptr Pointer to data 01246 \return value of type uint32_t at (*ptr) 01247 */ 01248 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) 01249 { 01250 uint32_t result; 01251 01252 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 01253 return(result); 01254 } 01255 01256 01257 /** 01258 \brief Store-Release (8 bit) 01259 \details Executes a STLB instruction for 8 bit values. 01260 \param [in] value Value to store 01261 \param [in] ptr Pointer to location 01262 */ 01263 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) 01264 { 01265 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 01266 } 01267 01268 01269 /** 01270 \brief Store-Release (16 bit) 01271 \details Executes a STLH instruction for 16 bit values. 01272 \param [in] value Value to store 01273 \param [in] ptr Pointer to location 01274 */ 01275 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) 01276 { 01277 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 01278 } 01279 01280 01281 /** 01282 \brief Store-Release (32 bit) 01283 \details Executes a STL instruction for 32 bit values. 01284 \param [in] value Value to store 01285 \param [in] ptr Pointer to location 01286 */ 01287 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) 01288 { 01289 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 01290 } 01291 01292 01293 /** 01294 \brief Load-Acquire Exclusive (8 bit) 01295 \details Executes a LDAB exclusive instruction for 8 bit value. 01296 \param [in] ptr Pointer to data 01297 \return value of type uint8_t at (*ptr) 01298 */ 01299 #define __LDAEXB (uint8_t)__builtin_arm_ldaex 01300 01301 01302 /** 01303 \brief Load-Acquire Exclusive (16 bit) 01304 \details Executes a LDAH exclusive instruction for 16 bit values. 01305 \param [in] ptr Pointer to data 01306 \return value of type uint16_t at (*ptr) 01307 */ 01308 #define __LDAEXH (uint16_t)__builtin_arm_ldaex 01309 01310 01311 /** 01312 \brief Load-Acquire Exclusive (32 bit) 01313 \details Executes a LDA exclusive instruction for 32 bit values. 01314 \param [in] ptr Pointer to data 01315 \return value of type uint32_t at (*ptr) 01316 */ 01317 #define __LDAEX (uint32_t)__builtin_arm_ldaex 01318 01319 01320 /** 01321 \brief Store-Release Exclusive (8 bit) 01322 \details Executes a STLB exclusive instruction for 8 bit values. 01323 \param [in] value Value to store 01324 \param [in] ptr Pointer to location 01325 \return 0 Function succeeded 01326 \return 1 Function failed 01327 */ 01328 #define __STLEXB (uint32_t)__builtin_arm_stlex 01329 01330 01331 /** 01332 \brief Store-Release Exclusive (16 bit) 01333 \details Executes a STLH exclusive instruction for 16 bit values. 01334 \param [in] value Value to store 01335 \param [in] ptr Pointer to location 01336 \return 0 Function succeeded 01337 \return 1 Function failed 01338 */ 01339 #define __STLEXH (uint32_t)__builtin_arm_stlex 01340 01341 01342 /** 01343 \brief Store-Release Exclusive (32 bit) 01344 \details Executes a STL exclusive instruction for 32 bit values. 01345 \param [in] value Value to store 01346 \param [in] ptr Pointer to location 01347 \return 0 Function succeeded 01348 \return 1 Function failed 01349 */ 01350 #define __STLEX (uint32_t)__builtin_arm_stlex 01351 01352 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 01353 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 01354 01355 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 01356 01357 01358 /* ################### Compiler specific Intrinsics ########################### */ 01359 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics 01360 Access to dedicated SIMD instructions 01361 @{ 01362 */ 01363 01364 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) 01365 01366 #define __SADD8 __builtin_arm_sadd8 01367 #define __QADD8 __builtin_arm_qadd8 01368 #define __SHADD8 __builtin_arm_shadd8 01369 #define __UADD8 __builtin_arm_uadd8 01370 #define __UQADD8 __builtin_arm_uqadd8 01371 #define __UHADD8 __builtin_arm_uhadd8 01372 #define __SSUB8 __builtin_arm_ssub8 01373 #define __QSUB8 __builtin_arm_qsub8 01374 #define __SHSUB8 __builtin_arm_shsub8 01375 #define __USUB8 __builtin_arm_usub8 01376 #define __UQSUB8 __builtin_arm_uqsub8 01377 #define __UHSUB8 __builtin_arm_uhsub8 01378 #define __SADD16 __builtin_arm_sadd16 01379 #define __QADD16 __builtin_arm_qadd16 01380 #define __SHADD16 __builtin_arm_shadd16 01381 #define __UADD16 __builtin_arm_uadd16 01382 #define __UQADD16 __builtin_arm_uqadd16 01383 #define __UHADD16 __builtin_arm_uhadd16 01384 #define __SSUB16 __builtin_arm_ssub16 01385 #define __QSUB16 __builtin_arm_qsub16 01386 #define __SHSUB16 __builtin_arm_shsub16 01387 #define __USUB16 __builtin_arm_usub16 01388 #define __UQSUB16 __builtin_arm_uqsub16 01389 #define __UHSUB16 __builtin_arm_uhsub16 01390 #define __SASX __builtin_arm_sasx 01391 #define __QASX __builtin_arm_qasx 01392 #define __SHASX __builtin_arm_shasx 01393 #define __UASX __builtin_arm_uasx 01394 #define __UQASX __builtin_arm_uqasx 01395 #define __UHASX __builtin_arm_uhasx 01396 #define __SSAX __builtin_arm_ssax 01397 #define __QSAX __builtin_arm_qsax 01398 #define __SHSAX __builtin_arm_shsax 01399 #define __USAX __builtin_arm_usax 01400 #define __UQSAX __builtin_arm_uqsax 01401 #define __UHSAX __builtin_arm_uhsax 01402 #define __USAD8 __builtin_arm_usad8 01403 #define __USADA8 __builtin_arm_usada8 01404 #define __SSAT16 __builtin_arm_ssat16 01405 #define __USAT16 __builtin_arm_usat16 01406 #define __UXTB16 __builtin_arm_uxtb16 01407 #define __UXTAB16 __builtin_arm_uxtab16 01408 #define __SXTB16 __builtin_arm_sxtb16 01409 #define __SXTAB16 __builtin_arm_sxtab16 01410 #define __SMUAD __builtin_arm_smuad 01411 #define __SMUADX __builtin_arm_smuadx 01412 #define __SMLAD __builtin_arm_smlad 01413 #define __SMLADX __builtin_arm_smladx 01414 #define __SMLALD __builtin_arm_smlald 01415 #define __SMLALDX __builtin_arm_smlaldx 01416 #define __SMUSD __builtin_arm_smusd 01417 #define __SMUSDX __builtin_arm_smusdx 01418 #define __SMLSD __builtin_arm_smlsd 01419 #define __SMLSDX __builtin_arm_smlsdx 01420 #define __SMLSLD __builtin_arm_smlsld 01421 #define __SMLSLDX __builtin_arm_smlsldx 01422 #define __SEL __builtin_arm_sel 01423 #define __QADD __builtin_arm_qadd 01424 #define __QSUB __builtin_arm_qsub 01425 01426 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ 01427 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) 01428 01429 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ 01430 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) 01431 01432 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) 01433 { 01434 int32_t result; 01435 01436 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); 01437 return(result); 01438 } 01439 01440 #endif /* (__ARM_FEATURE_DSP == 1) */ 01441 /*@} end of group CMSIS_SIMD_intrinsics */ 01442 01443 01444 #endif /* __CMSIS_ARMCLANG_H */
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