cmsis_armcc.h

00001 /**************************************************************************//**
00002  * @file     cmsis_armcc.h
00003  * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
00004  * @version  V5.1.1
00005  * @date     30. July 2019
00006  ******************************************************************************/
00007 /*
00008  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
00009  *
00010  * SPDX-License-Identifier: Apache-2.0
00011  *
00012  * Licensed under the Apache License, Version 2.0 (the License); you may
00013  * not use this file except in compliance with the License.
00014  * You may obtain a copy of the License at
00015  *
00016  * www.apache.org/licenses/LICENSE-2.0
00017  *
00018  * Unless required by applicable law or agreed to in writing, software
00019  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00020  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00021  * See the License for the specific language governing permissions and
00022  * limitations under the License.
00023  */
00024 
00025 #ifndef __CMSIS_ARMCC_H
00026 #define __CMSIS_ARMCC_H
00027 
00028 
00029 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
00030   #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
00031 #endif
00032 
00033 /* CMSIS compiler control architecture macros */
00034 #if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
00035      (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
00036   #define __ARM_ARCH_6M__           1
00037 #endif
00038 
00039 #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
00040   #define __ARM_ARCH_7M__           1
00041 #endif
00042 
00043 #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
00044   #define __ARM_ARCH_7EM__          1
00045 #endif
00046 
00047   /* __ARM_ARCH_8M_BASE__  not applicable */
00048   /* __ARM_ARCH_8M_MAIN__  not applicable */
00049 
00050 /* CMSIS compiler control DSP macros */
00051 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
00052   #define __ARM_FEATURE_DSP         1
00053 #endif
00054 
00055 /* CMSIS compiler specific defines */
00056 #ifndef   __ASM
00057   #define __ASM                                  __asm
00058 #endif
00059 #ifndef   __INLINE
00060   #define __INLINE                               __inline
00061 #endif
00062 #ifndef   __STATIC_INLINE
00063   #define __STATIC_INLINE                        static __inline
00064 #endif
00065 #ifndef   __STATIC_FORCEINLINE                 
00066   #define __STATIC_FORCEINLINE                   static __forceinline
00067 #endif           
00068 #ifndef   __NO_RETURN
00069   #define __NO_RETURN                            __declspec(noreturn)
00070 #endif
00071 #ifndef   __USED
00072   #define __USED                                 __attribute__((used))
00073 #endif
00074 #ifndef   __WEAK
00075   #define __WEAK                                 __attribute__((weak))
00076 #endif
00077 #ifndef   __PACKED
00078   #define __PACKED                               __attribute__((packed))
00079 #endif
00080 #ifndef   __PACKED_STRUCT
00081   #define __PACKED_STRUCT                        __packed struct
00082 #endif
00083 #ifndef   __PACKED_UNION
00084   #define __PACKED_UNION                         __packed union
00085 #endif
00086 #ifndef   __UNALIGNED_UINT32        /* deprecated */
00087   #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
00088 #endif
00089 #ifndef   __UNALIGNED_UINT16_WRITE
00090   #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
00091 #endif
00092 #ifndef   __UNALIGNED_UINT16_READ
00093   #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
00094 #endif
00095 #ifndef   __UNALIGNED_UINT32_WRITE
00096   #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
00097 #endif
00098 #ifndef   __UNALIGNED_UINT32_READ
00099   #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
00100 #endif
00101 #ifndef   __ALIGNED
00102   #define __ALIGNED(x)                           __attribute__((aligned(x)))
00103 #endif
00104 #ifndef   __RESTRICT
00105   #define __RESTRICT                             __restrict
00106 #endif
00107 #ifndef   __COMPILER_BARRIER
00108   #define __COMPILER_BARRIER()                   __memory_changed()
00109 #endif
00110 
00111 /* #########################  Startup and Lowlevel Init  ######################## */
00112 
00113 #ifndef __PROGRAM_START
00114 #define __PROGRAM_START           __main
00115 #endif
00116 
00117 #ifndef __INITIAL_SP
00118 #define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
00119 #endif
00120 
00121 #ifndef __STACK_LIMIT
00122 #define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
00123 #endif
00124 
00125 #ifndef __VECTOR_TABLE
00126 #define __VECTOR_TABLE            __Vectors
00127 #endif
00128 
00129 #ifndef __VECTOR_TABLE_ATTRIBUTE
00130 #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section("RESET")))
00131 #endif
00132 
00133 /* ###########################  Core Function Access  ########################### */
00134 /** \ingroup  CMSIS_Core_FunctionInterface
00135     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
00136   @{
00137  */
00138 
00139 /**
00140   \brief   Enable IRQ Interrupts
00141   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
00142            Can only be executed in Privileged modes.
00143  */
00144 /* intrinsic void __enable_irq();     */
00145 
00146 
00147 /**
00148   \brief   Disable IRQ Interrupts
00149   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
00150            Can only be executed in Privileged modes.
00151  */
00152 /* intrinsic void __disable_irq();    */
00153 
00154 /**
00155   \brief   Get Control Register
00156   \details Returns the content of the Control Register.
00157   \return               Control Register value
00158  */
00159 __STATIC_INLINE uint32_t __get_CONTROL(void)
00160 {
00161   register uint32_t __regControl         __ASM("control");
00162   return(__regControl);
00163 }
00164 
00165 
00166 /**
00167   \brief   Set Control Register
00168   \details Writes the given value to the Control Register.
00169   \param [in]    control  Control Register value to set
00170  */
00171 __STATIC_INLINE void __set_CONTROL(uint32_t control)
00172 {
00173   register uint32_t __regControl         __ASM("control");
00174   __regControl = control;
00175 }
00176 
00177 
00178 /**
00179   \brief   Get IPSR Register
00180   \details Returns the content of the IPSR Register.
00181   \return               IPSR Register value
00182  */
00183 __STATIC_INLINE uint32_t __get_IPSR(void)
00184 {
00185   register uint32_t __regIPSR          __ASM("ipsr");
00186   return(__regIPSR);
00187 }
00188 
00189 
00190 /**
00191   \brief   Get APSR Register
00192   \details Returns the content of the APSR Register.
00193   \return               APSR Register value
00194  */
00195 __STATIC_INLINE uint32_t __get_APSR(void)
00196 {
00197   register uint32_t __regAPSR          __ASM("apsr");
00198   return(__regAPSR);
00199 }
00200 
00201 
00202 /**
00203   \brief   Get xPSR Register
00204   \details Returns the content of the xPSR Register.
00205   \return               xPSR Register value
00206  */
00207 __STATIC_INLINE uint32_t __get_xPSR(void)
00208 {
00209   register uint32_t __regXPSR          __ASM("xpsr");
00210   return(__regXPSR);
00211 }
00212 
00213 
00214 /**
00215   \brief   Get Process Stack Pointer
00216   \details Returns the current value of the Process Stack Pointer (PSP).
00217   \return               PSP Register value
00218  */
00219 __STATIC_INLINE uint32_t __get_PSP(void)
00220 {
00221   register uint32_t __regProcessStackPointer  __ASM("psp");
00222   return(__regProcessStackPointer);
00223 }
00224 
00225 
00226 /**
00227   \brief   Set Process Stack Pointer
00228   \details Assigns the given value to the Process Stack Pointer (PSP).
00229   \param [in]    topOfProcStack  Process Stack Pointer value to set
00230  */
00231 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
00232 {
00233   register uint32_t __regProcessStackPointer  __ASM("psp");
00234   __regProcessStackPointer = topOfProcStack;
00235 }
00236 
00237 
00238 /**
00239   \brief   Get Main Stack Pointer
00240   \details Returns the current value of the Main Stack Pointer (MSP).
00241   \return               MSP Register value
00242  */
00243 __STATIC_INLINE uint32_t __get_MSP(void)
00244 {
00245   register uint32_t __regMainStackPointer     __ASM("msp");
00246   return(__regMainStackPointer);
00247 }
00248 
00249 
00250 /**
00251   \brief   Set Main Stack Pointer
00252   \details Assigns the given value to the Main Stack Pointer (MSP).
00253   \param [in]    topOfMainStack  Main Stack Pointer value to set
00254  */
00255 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
00256 {
00257   register uint32_t __regMainStackPointer     __ASM("msp");
00258   __regMainStackPointer = topOfMainStack;
00259 }
00260 
00261 
00262 /**
00263   \brief   Get Priority Mask
00264   \details Returns the current state of the priority mask bit from the Priority Mask Register.
00265   \return               Priority Mask value
00266  */
00267 __STATIC_INLINE uint32_t __get_PRIMASK(void)
00268 {
00269   register uint32_t __regPriMask         __ASM("primask");
00270   return(__regPriMask);
00271 }
00272 
00273 
00274 /**
00275   \brief   Set Priority Mask
00276   \details Assigns the given value to the Priority Mask Register.
00277   \param [in]    priMask  Priority Mask
00278  */
00279 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
00280 {
00281   register uint32_t __regPriMask         __ASM("primask");
00282   __regPriMask = (priMask);
00283 }
00284 
00285 
00286 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
00287      (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
00288 
00289 /**
00290   \brief   Enable FIQ
00291   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
00292            Can only be executed in Privileged modes.
00293  */
00294 #define __enable_fault_irq                __enable_fiq
00295 
00296 
00297 /**
00298   \brief   Disable FIQ
00299   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
00300            Can only be executed in Privileged modes.
00301  */
00302 #define __disable_fault_irq               __disable_fiq
00303 
00304 
00305 /**
00306   \brief   Get Base Priority
00307   \details Returns the current value of the Base Priority register.
00308   \return               Base Priority register value
00309  */
00310 __STATIC_INLINE uint32_t  __get_BASEPRI(void)
00311 {
00312   register uint32_t __regBasePri         __ASM("basepri");
00313   return(__regBasePri);
00314 }
00315 
00316 
00317 /**
00318   \brief   Set Base Priority
00319   \details Assigns the given value to the Base Priority register.
00320   \param [in]    basePri  Base Priority value to set
00321  */
00322 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
00323 {
00324   register uint32_t __regBasePri         __ASM("basepri");
00325   __regBasePri = (basePri & 0xFFU);
00326 }
00327 
00328 
00329 /**
00330   \brief   Set Base Priority with condition
00331   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
00332            or the new value increases the BASEPRI priority level.
00333   \param [in]    basePri  Base Priority value to set
00334  */
00335 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
00336 {
00337   register uint32_t __regBasePriMax      __ASM("basepri_max");
00338   __regBasePriMax = (basePri & 0xFFU);
00339 }
00340 
00341 
00342 /**
00343   \brief   Get Fault Mask
00344   \details Returns the current value of the Fault Mask register.
00345   \return               Fault Mask register value
00346  */
00347 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
00348 {
00349   register uint32_t __regFaultMask       __ASM("faultmask");
00350   return(__regFaultMask);
00351 }
00352 
00353 
00354 /**
00355   \brief   Set Fault Mask
00356   \details Assigns the given value to the Fault Mask register.
00357   \param [in]    faultMask  Fault Mask value to set
00358  */
00359 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
00360 {
00361   register uint32_t __regFaultMask       __ASM("faultmask");
00362   __regFaultMask = (faultMask & (uint32_t)1U);
00363 }
00364 
00365 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
00366            (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
00367 
00368 
00369 /**
00370   \brief   Get FPSCR
00371   \details Returns the current value of the Floating Point Status/Control register.
00372   \return               Floating Point Status/Control register value
00373  */
00374 __STATIC_INLINE uint32_t __get_FPSCR(void)
00375 {
00376 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
00377      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
00378   register uint32_t __regfpscr         __ASM("fpscr");
00379   return(__regfpscr);
00380 #else
00381    return(0U);
00382 #endif
00383 }
00384 
00385 
00386 /**
00387   \brief   Set FPSCR
00388   \details Assigns the given value to the Floating Point Status/Control register.
00389   \param [in]    fpscr  Floating Point Status/Control value to set
00390  */
00391 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
00392 {
00393 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
00394      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
00395   register uint32_t __regfpscr         __ASM("fpscr");
00396   __regfpscr = (fpscr);
00397 #else
00398   (void)fpscr;
00399 #endif
00400 }
00401 
00402 
00403 /*@} end of CMSIS_Core_RegAccFunctions */
00404 
00405 
00406 /* ##########################  Core Instruction Access  ######################### */
00407 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
00408   Access to dedicated instructions
00409   @{
00410 */
00411 
00412 /**
00413   \brief   No Operation
00414   \details No Operation does nothing. This instruction can be used for code alignment purposes.
00415  */
00416 #define __NOP                             __nop
00417 
00418 
00419 /**
00420   \brief   Wait For Interrupt
00421   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
00422  */
00423 #define __WFI                             __wfi
00424 
00425 
00426 /**
00427   \brief   Wait For Event
00428   \details Wait For Event is a hint instruction that permits the processor to enter
00429            a low-power state until one of a number of events occurs.
00430  */
00431 #define __WFE                             __wfe
00432 
00433 
00434 /**
00435   \brief   Send Event
00436   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
00437  */
00438 #define __SEV                             __sev
00439 
00440 
00441 /**
00442   \brief   Instruction Synchronization Barrier
00443   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
00444            so that all instructions following the ISB are fetched from cache or memory,
00445            after the instruction has been completed.
00446  */
00447 #define __ISB()                           __isb(0xF)
00448 
00449 /**
00450   \brief   Data Synchronization Barrier
00451   \details Acts as a special kind of Data Memory Barrier.
00452            It completes when all explicit memory accesses before this instruction complete.
00453  */
00454 #define __DSB()                           __dsb(0xF)
00455 
00456 /**
00457   \brief   Data Memory Barrier
00458   \details Ensures the apparent order of the explicit memory operations before
00459            and after the instruction, without ensuring their completion.
00460  */
00461 #define __DMB()                           __dmb(0xF)
00462 
00463                   
00464 /**
00465   \brief   Reverse byte order (32 bit)
00466   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
00467   \param [in]    value  Value to reverse
00468   \return               Reversed value
00469  */
00470 #define __REV                             __rev
00471 
00472 
00473 /**
00474   \brief   Reverse byte order (16 bit)
00475   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
00476   \param [in]    value  Value to reverse
00477   \return               Reversed value
00478  */
00479 #ifndef __NO_EMBEDDED_ASM
00480 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
00481 {
00482   rev16 r0, r0
00483   bx lr
00484 }
00485 #endif
00486 
00487 
00488 /**
00489   \brief   Reverse byte order (16 bit)
00490   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
00491   \param [in]    value  Value to reverse
00492   \return               Reversed value
00493  */
00494 #ifndef __NO_EMBEDDED_ASM
00495 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
00496 {
00497   revsh r0, r0
00498   bx lr
00499 }
00500 #endif
00501 
00502 
00503 /**
00504   \brief   Rotate Right in unsigned value (32 bit)
00505   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
00506   \param [in]    op1  Value to rotate
00507   \param [in]    op2  Number of Bits to rotate
00508   \return               Rotated value
00509  */
00510 #define __ROR                             __ror
00511 
00512 
00513 /**
00514   \brief   Breakpoint
00515   \details Causes the processor to enter Debug state.
00516            Debug tools can use this to investigate system state when the instruction at a particular address is reached.
00517   \param [in]    value  is ignored by the processor.
00518                  If required, a debugger can use it to store additional information about the breakpoint.
00519  */
00520 #define __BKPT(value)                       __breakpoint(value)
00521 
00522 
00523 /**
00524   \brief   Reverse bit order of value
00525   \details Reverses the bit order of the given value.
00526   \param [in]    value  Value to reverse
00527   \return               Reversed value
00528  */
00529 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
00530      (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
00531   #define __RBIT                          __rbit
00532 #else
00533 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
00534 {
00535   uint32_t result;
00536   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
00537 
00538   result = value;                      /* r will be reversed bits of v; first get LSB of v */
00539   for (value >>= 1U; value != 0U; value >>= 1U)
00540   {
00541     result <<= 1U;
00542     result |= value & 1U;
00543     s--;
00544   }
00545   result <<= s;                        /* shift when v's highest bits are zero */
00546   return result;
00547 }
00548 #endif
00549 
00550 
00551 /**
00552   \brief   Count leading zeros
00553   \details Counts the number of leading zeros of a data value.
00554   \param [in]  value  Value to count the leading zeros
00555   \return             number of leading zeros in value
00556  */
00557 #define __CLZ                             __clz
00558 
00559 
00560 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
00561      (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
00562 
00563 /**
00564   \brief   LDR Exclusive (8 bit)
00565   \details Executes a exclusive LDR instruction for 8 bit value.
00566   \param [in]    ptr  Pointer to data
00567   \return             value of type uint8_t at (*ptr)
00568  */
00569 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
00570   #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
00571 #else
00572   #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
00573 #endif
00574 
00575 
00576 /**
00577   \brief   LDR Exclusive (16 bit)
00578   \details Executes a exclusive LDR instruction for 16 bit values.
00579   \param [in]    ptr  Pointer to data
00580   \return        value of type uint16_t at (*ptr)
00581  */
00582 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
00583   #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
00584 #else
00585   #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
00586 #endif
00587 
00588 
00589 /**
00590   \brief   LDR Exclusive (32 bit)
00591   \details Executes a exclusive LDR instruction for 32 bit values.
00592   \param [in]    ptr  Pointer to data
00593   \return        value of type uint32_t at (*ptr)
00594  */
00595 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
00596   #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
00597 #else
00598   #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
00599 #endif
00600 
00601 
00602 /**
00603   \brief   STR Exclusive (8 bit)
00604   \details Executes a exclusive STR instruction for 8 bit values.
00605   \param [in]  value  Value to store
00606   \param [in]    ptr  Pointer to location
00607   \return          0  Function succeeded
00608   \return          1  Function failed
00609  */
00610 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
00611   #define __STREXB(value, ptr)                                                 __strex(value, ptr)
00612 #else
00613   #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
00614 #endif
00615 
00616 
00617 /**
00618   \brief   STR Exclusive (16 bit)
00619   \details Executes a exclusive STR instruction for 16 bit values.
00620   \param [in]  value  Value to store
00621   \param [in]    ptr  Pointer to location
00622   \return          0  Function succeeded
00623   \return          1  Function failed
00624  */
00625 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
00626   #define __STREXH(value, ptr)                                                 __strex(value, ptr)
00627 #else
00628   #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
00629 #endif
00630 
00631 
00632 /**
00633   \brief   STR Exclusive (32 bit)
00634   \details Executes a exclusive STR instruction for 32 bit values.
00635   \param [in]  value  Value to store
00636   \param [in]    ptr  Pointer to location
00637   \return          0  Function succeeded
00638   \return          1  Function failed
00639  */
00640 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
00641   #define __STREXW(value, ptr)                                                 __strex(value, ptr)
00642 #else
00643   #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
00644 #endif
00645 
00646 
00647 /**
00648   \brief   Remove the exclusive lock
00649   \details Removes the exclusive lock which is created by LDREX.
00650  */
00651 #define __CLREX                           __clrex
00652 
00653 
00654 /**
00655   \brief   Signed Saturate
00656   \details Saturates a signed value.
00657   \param [in]  value  Value to be saturated
00658   \param [in]    sat  Bit position to saturate to (1..32)
00659   \return             Saturated value
00660  */
00661 #define __SSAT                            __ssat
00662 
00663 
00664 /**
00665   \brief   Unsigned Saturate
00666   \details Saturates an unsigned value.
00667   \param [in]  value  Value to be saturated
00668   \param [in]    sat  Bit position to saturate to (0..31)
00669   \return             Saturated value
00670  */
00671 #define __USAT                            __usat
00672 
00673 
00674 /**
00675   \brief   Rotate Right with Extend (32 bit)
00676   \details Moves each bit of a bitstring right by one bit.
00677            The carry input is shifted in at the left end of the bitstring.
00678   \param [in]    value  Value to rotate
00679   \return               Rotated value
00680  */
00681 #ifndef __NO_EMBEDDED_ASM
00682 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
00683 {
00684   rrx r0, r0
00685   bx lr
00686 }
00687 #endif
00688 
00689 
00690 /**
00691   \brief   LDRT Unprivileged (8 bit)
00692   \details Executes a Unprivileged LDRT instruction for 8 bit value.
00693   \param [in]    ptr  Pointer to data
00694   \return             value of type uint8_t at (*ptr)
00695  */
00696 #define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
00697 
00698 
00699 /**
00700   \brief   LDRT Unprivileged (16 bit)
00701   \details Executes a Unprivileged LDRT instruction for 16 bit values.
00702   \param [in]    ptr  Pointer to data
00703   \return        value of type uint16_t at (*ptr)
00704  */
00705 #define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
00706 
00707 
00708 /**
00709   \brief   LDRT Unprivileged (32 bit)
00710   \details Executes a Unprivileged LDRT instruction for 32 bit values.
00711   \param [in]    ptr  Pointer to data
00712   \return        value of type uint32_t at (*ptr)
00713  */
00714 #define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
00715 
00716 
00717 /**
00718   \brief   STRT Unprivileged (8 bit)
00719   \details Executes a Unprivileged STRT instruction for 8 bit values.
00720   \param [in]  value  Value to store
00721   \param [in]    ptr  Pointer to location
00722  */
00723 #define __STRBT(value, ptr)               __strt(value, ptr)
00724 
00725 
00726 /**
00727   \brief   STRT Unprivileged (16 bit)
00728   \details Executes a Unprivileged STRT instruction for 16 bit values.
00729   \param [in]  value  Value to store
00730   \param [in]    ptr  Pointer to location
00731  */
00732 #define __STRHT(value, ptr)               __strt(value, ptr)
00733 
00734 
00735 /**
00736   \brief   STRT Unprivileged (32 bit)
00737   \details Executes a Unprivileged STRT instruction for 32 bit values.
00738   \param [in]  value  Value to store
00739   \param [in]    ptr  Pointer to location
00740  */
00741 #define __STRT(value, ptr)                __strt(value, ptr)
00742 
00743 #else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
00744            (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
00745 
00746 /**
00747   \brief   Signed Saturate
00748   \details Saturates a signed value.
00749   \param [in]  value  Value to be saturated
00750   \param [in]    sat  Bit position to saturate to (1..32)
00751   \return             Saturated value
00752  */
00753 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
00754 {
00755   if ((sat >= 1U) && (sat <= 32U))
00756   {
00757     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
00758     const int32_t min = -1 - max ;
00759     if (val > max)
00760     {
00761       return max;
00762     }
00763     else if (val < min)
00764     {
00765       return min;
00766     }
00767   }
00768   return val;
00769 }
00770 
00771 /**
00772   \brief   Unsigned Saturate
00773   \details Saturates an unsigned value.
00774   \param [in]  value  Value to be saturated
00775   \param [in]    sat  Bit position to saturate to (0..31)
00776   \return             Saturated value
00777  */
00778 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
00779 {
00780   if (sat <= 31U)
00781   {
00782     const uint32_t max = ((1U << sat) - 1U);
00783     if (val > (int32_t)max)
00784     {
00785       return max;
00786     }
00787     else if (val < 0)
00788     {
00789       return 0U;
00790     }
00791   }
00792   return (uint32_t)val;
00793 }
00794 
00795 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
00796            (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
00797 
00798 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
00799 
00800 
00801 /* ###################  Compiler specific Intrinsics  ########################### */
00802 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
00803   Access to dedicated SIMD instructions
00804   @{
00805 */
00806 
00807 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
00808 
00809 #define __SADD8                           __sadd8
00810 #define __QADD8                           __qadd8
00811 #define __SHADD8                          __shadd8
00812 #define __UADD8                           __uadd8
00813 #define __UQADD8                          __uqadd8
00814 #define __UHADD8                          __uhadd8
00815 #define __SSUB8                           __ssub8
00816 #define __QSUB8                           __qsub8
00817 #define __SHSUB8                          __shsub8
00818 #define __USUB8                           __usub8
00819 #define __UQSUB8                          __uqsub8
00820 #define __UHSUB8                          __uhsub8
00821 #define __SADD16                          __sadd16
00822 #define __QADD16                          __qadd16
00823 #define __SHADD16                         __shadd16
00824 #define __UADD16                          __uadd16
00825 #define __UQADD16                         __uqadd16
00826 #define __UHADD16                         __uhadd16
00827 #define __SSUB16                          __ssub16
00828 #define __QSUB16                          __qsub16
00829 #define __SHSUB16                         __shsub16
00830 #define __USUB16                          __usub16
00831 #define __UQSUB16                         __uqsub16
00832 #define __UHSUB16                         __uhsub16
00833 #define __SASX                            __sasx
00834 #define __QASX                            __qasx
00835 #define __SHASX                           __shasx
00836 #define __UASX                            __uasx
00837 #define __UQASX                           __uqasx
00838 #define __UHASX                           __uhasx
00839 #define __SSAX                            __ssax
00840 #define __QSAX                            __qsax
00841 #define __SHSAX                           __shsax
00842 #define __USAX                            __usax
00843 #define __UQSAX                           __uqsax
00844 #define __UHSAX                           __uhsax
00845 #define __USAD8                           __usad8
00846 #define __USADA8                          __usada8
00847 #define __SSAT16                          __ssat16
00848 #define __USAT16                          __usat16
00849 #define __UXTB16                          __uxtb16
00850 #define __UXTAB16                         __uxtab16
00851 #define __SXTB16                          __sxtb16
00852 #define __SXTAB16                         __sxtab16
00853 #define __SMUAD                           __smuad
00854 #define __SMUADX                          __smuadx
00855 #define __SMLAD                           __smlad
00856 #define __SMLADX                          __smladx
00857 #define __SMLALD                          __smlald
00858 #define __SMLALDX                         __smlaldx
00859 #define __SMUSD                           __smusd
00860 #define __SMUSDX                          __smusdx
00861 #define __SMLSD                           __smlsd
00862 #define __SMLSDX                          __smlsdx
00863 #define __SMLSLD                          __smlsld
00864 #define __SMLSLDX                         __smlsldx
00865 #define __SEL                             __sel
00866 #define __QADD                            __qadd
00867 #define __QSUB                            __qsub
00868 
00869 #define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
00870                                            ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
00871 
00872 #define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
00873                                            ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
00874 
00875 #define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
00876                                                       ((int64_t)(ARG3) << 32U)     ) >> 32U))
00877 
00878 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
00879 /*@} end of group CMSIS_SIMD_intrinsics */
00880 
00881 
00882 #endif /* __CMSIS_ARMCC_H */