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Show/hide line numbers read_uid.c Source File

read_uid.c

00001 /**
00002  * @file    read_uid.c
00003  * @brief   
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #include "stdbool.h"
00023 
00024 #include "read_uid.h"
00025 #include "sam3u.h"
00026 #include "cortex_m.h"
00027 
00028 bool unique_id_created = false;
00029 static uint32_t unique_id[4];
00030 void read_unique_id(uint32_t *id)
00031 {
00032     if (!unique_id_created) {
00033         create_unique_id();
00034         unique_id_created = true;
00035     }
00036 
00037     id[0] = unique_id[0];
00038     id[1] = unique_id[1];
00039     id[2] = unique_id[2];
00040     id[3] = unique_id[3];
00041 }
00042 
00043 __attribute__((section("ram_func")))
00044 void create_unique_id(void)
00045 {
00046     cortex_int_state_t state;
00047     state = cortex_int_get_and_disable();
00048     EFC0->EEFC_FMR |= (1UL << 16);
00049     EFC0->EEFC_FCR = 0x5A00000E;
00050 
00051     /*Monitor FRDY*/
00052     while ((EFC0->EEFC_FSR & EEFC_FSR_FRDY) == EEFC_FSR_FRDY);
00053 
00054     unique_id[0] = *(uint32_t *)0x80000;
00055     unique_id[1] = *(uint32_t *)0x80004;
00056     unique_id[2] = *(uint32_t *)0x80008;
00057     unique_id[3] = *(uint32_t *)0x8000C;
00058     EFC0->EEFC_FCR = 0x5A00000F;
00059 
00060     /*Monitor FRDY*/
00061     while ((EFC0->EEFC_FSR & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);
00062 
00063     EFC0->EEFC_FMR &= ~(1UL << 16);
00064     cortex_int_restore(state);
00065 }