DAP_config.h

00001 /**
00002  * @file    DAP_config.h
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #ifndef __DAP_CONFIG_H__
00023 #define __DAP_CONFIG_H__
00024 
00025 //**************************************************************************************************
00026 /**
00027 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
00028 \ingroup DAP_ConfigIO_gr
00029 @{
00030 Provides definitions about:
00031  - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
00032  - Debug Unit communication packet size.
00033  - Debug Access Port communication mode (JTAG or SWD).
00034  - Optional information about a connected Target Device (for Evaluation Boards).
00035 */
00036 
00037 #include "IO_Config.h"
00038 
00039 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
00040 /// This value is used to calculate the SWD/JTAG clock speed.
00041 #define CPU_CLOCK               SystemCoreClock        ///< Specifies the CPU Clock in Hz
00042 
00043 /// Number of processor cycles for I/O Port write operations.
00044 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
00045 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
00046 /// requrie 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
00047 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
00048 /// requrired.
00049 #define IO_PORT_WRITE_CYCLES    2               ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
00050 
00051 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
00052 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00053 #define DAP_SWD                 1               ///< SWD Mode:  1 = available, 0 = not available
00054 
00055 /// Indicate that JTAG communication mode is available at the Debug Port.
00056 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00057 #define DAP_JTAG                0               ///< JTAG Mode: 1 = available, 0 = not available.
00058 
00059 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
00060 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
00061 #define DAP_JTAG_DEV_CNT        0               ///< Maximum number of JTAG devices on scan chain
00062 
00063 /// Default communication mode on the Debug Access Port.
00064 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
00065 #define DAP_DEFAULT_PORT        1               ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
00066 
00067 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
00068 /// Used to initialize the default SWD/JTAG clock frequency.
00069 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
00070 #define DAP_DEFAULT_SWJ_CLOCK   2000000         ///< Default SWD/JTAG clock frequency in Hz.
00071 
00072 /// Maximum Package Size for Command and Response data.
00073 /// This configuration settings is used to optimized the communication performance with the
00074 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
00075 #define DAP_PACKET_SIZE        64              ///< USB: 64 = Full-Speed, 1024 = High-Speed.
00076 
00077 /// Maximum Package Buffers for Command and Response data.
00078 /// This configuration settings is used to optimized the communication performance with the
00079 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
00080 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
00081 #define DAP_PACKET_COUNT        4              ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
00082 
00083 /// Indicate that UART Serial Wire Output (SWO) trace is available.
00084 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00085 #define SWO_UART                0               ///< SWO UART:  1 = available, 0 = not available
00086 
00087 /// Maximum SWO UART Baudrate
00088 #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz
00089 
00090 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
00091 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00092 #define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available
00093 
00094 /// SWO Trace Buffer Size.
00095 #define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n)
00096 
00097 /// SWO Streaming Trace.
00098 #define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
00099 
00100 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
00101 #define TIMESTAMP_CLOCK         1000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
00102 
00103 
00104 /// Debug Unit is connected to fixed Target Device.
00105 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
00106 /// known device.  In this case a Device Vendor and Device Name string is stored which
00107 /// may be used by the debugger or IDE to configure device parameters.
00108 #define TARGET_DEVICE_FIXED     0               ///< Target Device: 1 = known, 0 = unknown;
00109 
00110 #if TARGET_DEVICE_FIXED
00111 #define TARGET_DEVICE_VENDOR    ""              ///< String indicating the Silicon Vendor
00112 #define TARGET_DEVICE_NAME      ""              ///< String indicating the Target Device
00113 #endif
00114 
00115 ///@}
00116 
00117 
00118 //**************************************************************************************************
00119 /**
00120 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
00121 \ingroup DAP_ConfigIO_gr
00122 @{
00123 
00124 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
00125 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
00126 interface of a device. The following I/O Pins are provided:
00127 
00128 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
00129 ---------------------------- | -------------------- | ---------------------------------------------
00130 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
00131 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
00132 TDI: Test Data Input         |                      | Output Push/Pull
00133 TDO: Test Data Output        |                      | Input
00134 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
00135 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
00136 
00137 
00138 DAP Hardware I/O Pin Access Functions
00139 -------------------------------------
00140 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
00141 these I/O Pins.
00142 
00143 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
00144 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
00145 peripherals that can independently write/read a single I/O pin without affecting any other pins
00146 of the same I/O port. The following SWDIO I/O Pin functions are provided:
00147  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
00148  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
00149  - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
00150  - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
00151 */
00152 
00153 
00154 // Configure DAP I/O pins ------------------------------
00155 
00156 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
00157 Configures the DAP Hardware I/O pins for JTAG mode:
00158  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
00159  - TDO to input mode.
00160 */
00161 __STATIC_INLINE void PORT_JTAG_SETUP(void) {}
00162 
00163 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
00164 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
00165  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
00166  - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
00167 */
00168 __STATIC_INLINE void PORT_SWD_SETUP(void)
00169 {
00170     PMC->PMC_PCER0 = (1 << 10) | (1 << 11) | (1 << 12);  // Enable clock for all PIOs
00171 
00172     PIN_nRESET_PORT->PIO_MDDR = PIN_nRESET; // Disable multi drive
00173     PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable
00174     PIN_nRESET_PORT->PIO_SODR = PIN_nRESET; // HIGH
00175     PIN_nRESET_PORT->PIO_OER  = PIN_nRESET; // output
00176     PIN_nRESET_PORT->PIO_PER  = PIN_nRESET; // GPIO control
00177 
00178     PIN_SWCLK_PORT->PIO_MDDR = PIN_SWCLK; // Disable multi drive
00179     PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable
00180     PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK; // HIGH
00181     PIN_SWCLK_PORT->PIO_OER  = PIN_SWCLK; // output
00182     PIN_SWCLK_PORT->PIO_PER  = PIN_SWCLK; // GPIO control
00183 
00184     PIN_SWDIO_PORT->PIO_MDDR = PIN_SWDIO; // Disable multi drive
00185     PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable
00186     PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; // HIGH
00187     PIN_SWDIO_PORT->PIO_OER  = PIN_SWDIO; // output
00188     PIN_SWDIO_PORT->PIO_PER  = PIN_SWDIO; // GPIO control
00189 }
00190 
00191 /** Disable JTAG/SWD I/O Pins.
00192 Disables the DAP Hardware I/O pins which configures:
00193  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
00194 */
00195 __STATIC_INLINE void PORT_OFF(void)
00196 {
00197     PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable
00198     PIN_nRESET_PORT->PIO_ODR  = PIN_nRESET; // input
00199     PIN_nRESET_PORT->PIO_PER  = PIN_nRESET; // GPIO control
00200 
00201     PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable
00202     PIN_SWCLK_PORT->PIO_ODR  = PIN_SWCLK; // input
00203     PIN_SWCLK_PORT->PIO_PER  = PIN_SWCLK; // GPIO control
00204 
00205     PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable
00206     PIN_SWDIO_PORT->PIO_ODR  = PIN_SWDIO; // input
00207     PIN_SWDIO_PORT->PIO_PER  = PIN_SWDIO; // GPIO control
00208 
00209 }
00210 
00211 // SWCLK/TCK I/O pin -------------------------------------
00212 
00213 /** SWCLK/TCK I/O pin: Get Input.
00214 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
00215 */
00216 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
00217 {
00218     return ((PIN_SWCLK_PORT->PIO_PDSR >> PIN_SWCLK_BIT) & 1);
00219 }
00220 
00221 /** SWCLK/TCK I/O pin: Set Output to High.
00222 Set the SWCLK/TCK DAP hardware I/O pin to high level.
00223 */
00224 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET(void)
00225 {
00226     PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK;
00227 }
00228 
00229 /** SWCLK/TCK I/O pin: Set Output to Low.
00230 Set the SWCLK/TCK DAP hardware I/O pin to low level.
00231 */
00232 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR(void)
00233 {
00234     PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK;
00235 }
00236 
00237 // SWDIO/TMS Pin I/O --------------------------------------
00238 
00239 /** SWDIO/TMS I/O pin: Get Input.
00240 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
00241 */
00242 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
00243 {
00244     return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1);
00245 }
00246 
00247 /** SWDIO/TMS I/O pin: Set Output to High.
00248 Set the SWDIO/TMS DAP hardware I/O pin to high level.
00249 */
00250 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET(void)
00251 {
00252     PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO;
00253 }
00254 
00255 /** SWDIO/TMS I/O pin: Set Output to Low.
00256 Set the SWDIO/TMS DAP hardware I/O pin to low level.
00257 */
00258 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR(void)
00259 {
00260     PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO;
00261 }
00262 
00263 /** SWDIO I/O pin: Get Input (used in SWD mode only).
00264 \return Current status of the SWDIO DAP hardware I/O pin.
00265 */
00266 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
00267 {
00268     return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1);
00269 }
00270 
00271 /** SWDIO I/O pin: Set Output (used in SWD mode only).
00272 \param bit Output value for the SWDIO DAP hardware I/O pin.
00273 */
00274 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT(uint32_t bit)
00275 {
00276     if (bit & 1) {
00277         PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO;
00278 
00279     } else {
00280         PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO;
00281     }
00282 }
00283 
00284 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
00285 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
00286 called prior \ref PIN_SWDIO_OUT function calls.
00287 */
00288 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE(void)
00289 {
00290     PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO;
00291 }
00292 
00293 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
00294 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
00295 called prior \ref PIN_SWDIO_IN function calls.
00296 */
00297 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE(void)
00298 {
00299     PIN_SWDIO_PORT->PIO_ODR = PIN_SWDIO;
00300 }
00301 
00302 
00303 // TDI Pin I/O ---------------------------------------------
00304 
00305 /** TDI I/O pin: Get Input.
00306 \return Current status of the TDI DAP hardware I/O pin.
00307 */
00308 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
00309 {
00310     return (0);   // Not available
00311 }
00312 
00313 /** TDI I/O pin: Set Output.
00314 \param bit Output value for the TDI DAP hardware I/O pin.
00315 */
00316 __STATIC_FORCEINLINE void     PIN_TDI_OUT(uint32_t bit)
00317 {
00318     ;             // Not available
00319 }
00320 
00321 
00322 // TDO Pin I/O ---------------------------------------------
00323 
00324 /** TDO I/O pin: Get Input.
00325 \return Current status of the TDO DAP hardware I/O pin.
00326 */
00327 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
00328 {
00329     return (0);   // Not available
00330 }
00331 
00332 
00333 // nTRST Pin I/O -------------------------------------------
00334 
00335 /** nTRST I/O pin: Get Input.
00336 \return Current status of the nTRST DAP hardware I/O pin.
00337 */
00338 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
00339 {
00340     return (0);   // Not available
00341 }
00342 
00343 /** nTRST I/O pin: Set Output.
00344 \param bit JTAG TRST Test Reset pin status:
00345            - 0: issue a JTAG TRST Test Reset.
00346            - 1: release JTAG TRST Test Reset.
00347 */
00348 __STATIC_FORCEINLINE void     PIN_nTRST_OUT(uint32_t bit)
00349 {
00350     ;             // Not available
00351 }
00352 
00353 // nRESET Pin I/O------------------------------------------
00354 
00355 /** nRESET I/O pin: Get Input.
00356 \return Current status of the nRESET DAP hardware I/O pin.
00357 */
00358 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
00359 {
00360     return ((PIN_nRESET_PORT->PIO_PDSR >> PIN_nRESET_BIT) & 1);
00361 }
00362 
00363 /** nRESET I/O pin: Set Output.
00364 \param bit target device hardware reset pin status:
00365            - 0: issue a device hardware reset.
00366            - 1: release device hardware reset.
00367 */
00368 // TODO - sw specific implementation should be created
00369 #if defined (DBG_NRF51822AA)
00370 __STATIC_FORCEINLINE void     PIN_nRESET_OUT(uint32_t bit)
00371 {
00372     /**There is no reset pin on the nRF51822, so we need to use a reset routine:
00373     Enable reset through the RESET register in the POWER peripheral.
00374     Hold the SWDCLK and SWDIO/nRESET line low for a minimum of 100 us.
00375      */
00376     if (bit & 1) {
00377         PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO;
00378 
00379         PIN_SWDIO_PORT->PIO_MDER = PIN_SWDIO;
00380         PIN_SWCLK_PORT->PIO_MDER = PIN_SWCLK;
00381         PIN_nRESET_PORT->PIO_MDER = PIN_nRESET;
00382 
00383     } else {
00384         swd_init_debug();
00385 
00386         //Set POWER->RESET on NRF to 1
00387         if (!swd_write_ap(AP_TAR, 0x40000000 + 0x544)) {
00388             return;
00389         }
00390 
00391         if (!swd_write_ap(AP_DRW, 1)) {
00392             return;
00393         }
00394 
00395         //Hold RESET and SWCLK low for a minimum of 100us
00396         PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO;
00397         PIN_SWCLK_PORT->PIO_OER = PIN_SWCLK;
00398         PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO;
00399         PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK;
00400         osDelay(1);
00401     }
00402 }
00403 #else
00404 __STATIC_FORCEINLINE void     PIN_nRESET_OUT(uint32_t bit)
00405 {
00406     if (bit & 1) {
00407         PIN_nRESET_PORT->PIO_SODR = PIN_nRESET;
00408 
00409     } else {
00410         PIN_nRESET_PORT->PIO_CODR = PIN_nRESET;
00411     }
00412 }
00413 #endif
00414 ///@}
00415 
00416 
00417 //**************************************************************************************************
00418 /**
00419 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
00420 \ingroup DAP_ConfigIO_gr
00421 @{
00422 
00423 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
00424 
00425 It is recommended to provide the following LEDs for status indication:
00426  - Connect LED: is active when the DAP hardware is connected to a debugger.
00427  - Running LED: is active when the debugger has put the target device into running state.
00428 */
00429 
00430 /** Debug Unit: Set status of Connected LED.
00431 \param bit status of the Connect LED.
00432            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
00433            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
00434 */
00435 __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
00436 {
00437 }
00438 
00439 /** Debug Unit: Set status Target Running LED.
00440 \param bit status of the Target Running LED.
00441            - 1: Target Running LED ON: program execution in target started.
00442            - 0: Target Running LED OFF: program execution in target stopped.
00443 */
00444 __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
00445 {
00446     ;             // Not available
00447 }
00448 
00449 ///@}
00450 
00451 
00452 //**************************************************************************************************
00453 /**
00454 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
00455 \ingroup DAP_ConfigIO_gr
00456 @{
00457 Access function for Test Domain Timer.
00458 
00459 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
00460 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
00461 
00462 */
00463 
00464 /** Get timestamp of Test Domain Timer.
00465 \return Current timestamp value.
00466 */
00467 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
00468   return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
00469 }
00470 
00471 ///@}
00472 
00473 
00474 //**************************************************************************************************
00475 /**
00476 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
00477 \ingroup DAP_ConfigIO_gr
00478 @{
00479 
00480 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
00481 */
00482 
00483 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
00484 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
00485 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
00486  - I/O clock system enabled.
00487  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
00488  - for nTRST, nRESET a weak pull-up (if available) is enabled.
00489  - LED output pins are enabled and LEDs are turned off.
00490 */
00491 __STATIC_INLINE void DAP_SETUP(void)
00492 {
00493 }
00494 
00495 /** Reset Target Device with custom specific I/O pin or command sequence.
00496 This function allows the optional implementation of a device specific reset sequence.
00497 It is called when the command \ref DAP_ResetTarget and is for example required
00498 when a device needs a time-critical unlock sequence that enables the debug port.
00499 \return 0 = no device specific reset sequence is implemented.\n
00500         1 = a device specific reset sequence is implemented.
00501 */
00502 __STATIC_INLINE uint32_t RESET_TARGET(void)
00503 {
00504     return (0);              // change to '1' when a device reset sequence is implemented
00505 }
00506 
00507 ///@}
00508 
00509 
00510 #endif /* __DAP_CONFIG_H__ */