target_reset.c

00001 /**
00002  * @file    target_reset.c
00003  * @brief   Target reset for Musca B target
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #include "target_family.h"
00023 #include "target_config.h"  // for target_device
00024 #include "swd_host.h"
00025 #include "gpio.h"
00026 #include "i2c_gpio.h"
00027 #include "debug_cm.h"
00028 #include "utils.h"
00029 #include "power_ctrl.h"
00030 #include "uart.h"
00031 
00032 static void musca_b_target_before_init_debug(void)
00033 {
00034     uint8_t buf[12];
00035 
00036     // go into controlled shutdown
00037     power_off_sequence();
00038 
00039     // Drive SCC signals
00040     LPC_GPIO->DIR[PIN_SCC_CLK_PORT]     |= PIN_SCC_CLK;
00041     LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT]  |= PIN_SCC_DATAIN;
00042     LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
00043     LPC_GPIO->DIR[PIN_SCC_WNR_PORT]     |= PIN_SCC_WNR;
00044     LPC_GPIO->DIR[PIN_SCC_LOAD_PORT]    |= PIN_SCC_LOAD;
00045 
00046     // Wait 10ms
00047     delay(10);
00048 
00049     // Release CFG_nRST to allow SCC config
00050     LPC_GPIO->SET[PIN_CFG_nRST_PORT] = PIN_CFG_nRST;
00051 
00052     // Wait 10ms
00053     delay(10);
00054 
00055     // Configure SCC
00056     configure_syscon(0x1A400000);
00057 
00058     // Wait 10ms
00059     delay(10);
00060 
00061     // Creating branch to self in SRAM
00062     buf[0] = 0x00;
00063     buf[1] = 0x00;
00064     buf[2] = 0x08;
00065     buf[3] = 0x30;
00066     buf[4] = 0x09;
00067     buf[5] = 0x00;
00068     buf[6] = 0x40;
00069     buf[7] = 0x1A;
00070     buf[8] = 0xFE;
00071     buf[9] = 0xE7;
00072     buf[10] = 0xFE;
00073     buf[11] = 0xE7;
00074 
00075     swd_write_memory(0x1A400000, (uint8_t *)buf, 12);
00076 
00077 //    swd_write_word(0x1A400000, 0x30008000);
00078 //    swd_write_word(0x1A400004, 0x1A400009);
00079 //    swd_write_word(0x1A400008, 0xE7FEE7FE);
00080 
00081     // Wait 10ms
00082     delay(10);
00083 
00084     // Release SCC signals
00085     LPC_GPIO->DIR[PIN_SCC_CLK_PORT]     &= ~PIN_SCC_CLK;
00086     LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT]  &= ~PIN_SCC_DATAIN;
00087     LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
00088     LPC_GPIO->DIR[PIN_SCC_WNR_PORT]     &= ~PIN_SCC_WNR;
00089     LPC_GPIO->DIR[PIN_SCC_LOAD_PORT]    &= ~PIN_SCC_LOAD;
00090 
00091     // Wait 10ms
00092     delay(10);
00093 
00094     // Release CB_nRST (nPORESET)
00095     LPC_GPIO->SET[PIN_CB_nRST_PORT] = PIN_CB_nRST;
00096 
00097     // Wait 10ms
00098     delay(10);
00099 
00100     // Release CS_nSRST
00101     LPC_GPIO->SET[PIN_nRESET_PORT] = PIN_nRESET;
00102 
00103     // Wait 10ms
00104     delay(10);
00105 
00106     return;
00107 }
00108 
00109 static uint8_t musca_b_target_set_state(target_state_t state)
00110 {
00111     if(state == RESET_RUN)
00112     {
00113         // go through controlled reset
00114         power_off_sequence();
00115 
00116         power_on_sequence();
00117 
00118         // Wait 10ms
00119         delay(10);
00120 
00121         swd_off();
00122 
00123         return 1;
00124     }
00125     if(state == SHUTDOWN)
00126     {
00127         // go through controlled shutdown
00128         power_off_sequence();
00129 
00130         // Turn OFF power
00131         i2cio_power_off();
00132 
00133         // Wait 10ms
00134         delay(10);
00135 
00136         uart_reset();
00137 
00138         return 1;
00139     }
00140     if(state == POWER_ON)
00141     {
00142         // Turn ON power
00143         i2cio_power_on();
00144 
00145         // Wait 10ms
00146         delay(10);
00147 
00148         // power on the target
00149         power_on_sequence();
00150 
00151         // Wait 10ms
00152         delay(10);
00153 
00154         swd_off();
00155         return 1;
00156     }
00157 
00158     return swd_set_target_state_sw(state);
00159 }
00160 
00161 const target_family_descriptor_t g_target_family_musca_b = {
00162     .target_before_init_debug  = musca_b_target_before_init_debug,
00163     .target_set_state = musca_b_target_set_state,
00164     .apsel = 0x01000000,
00165 };
00166 
00167 const target_family_descriptor_t *g_target_family = &g_target_family_musca_b;