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MKL26Z4_features.h
00001 /* 00002 ** ################################################################### 00003 ** Version: rev. 1.11, 2015-05-27 00004 ** Build: b160217 00005 ** 00006 ** Abstract: 00007 ** Chip specific module features. 00008 ** 00009 ** Copyright (c) 2016 Freescale Semiconductor, Inc. 00010 ** All rights reserved. 00011 ** 00012 ** Redistribution and use in source and binary forms, with or without modification, 00013 ** are permitted provided that the following conditions are met: 00014 ** 00015 ** o Redistributions of source code must retain the above copyright notice, this list 00016 ** of conditions and the following disclaimer. 00017 ** 00018 ** o Redistributions in binary form must reproduce the above copyright notice, this 00019 ** list of conditions and the following disclaimer in the documentation and/or 00020 ** other materials provided with the distribution. 00021 ** 00022 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00023 ** contributors may be used to endorse or promote products derived from this 00024 ** software without specific prior written permission. 00025 ** 00026 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00027 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00028 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00029 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00030 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00031 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00032 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00033 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00034 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00035 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00036 ** 00037 ** http: www.freescale.com 00038 ** mail: support@freescale.com 00039 ** 00040 ** Revisions: 00041 ** - rev. 1.0 (2012-12-12) 00042 ** Initial version. 00043 ** - rev. 1.1 (2013-04-12) 00044 ** SystemInit function fixed for clock configuration 1. 00045 ** Name of the interrupt num. 31 updated to reflect proper function. 00046 ** - rev. 1.2 (2014-01-30) 00047 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. 00048 ** - rev. 1.3 (2014-05-27) 00049 ** Updated to Kinetis SDK support standard. 00050 ** MCG OSC clock select supported (MCG_C7[OSCSEL]). 00051 ** - rev. 1.4 (2014-07-25) 00052 ** System initialization updated: 00053 ** - Prefix added to the system initialization parameterization constants to avoid name conflicts.. 00054 ** - VLLSx wake-up recovery added. 00055 ** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes. 00056 ** - rev. 1.5 (2014-08-28) 00057 ** Update of system files - default clock configuration changed, fix of OSC initialization. 00058 ** Update of startup files - possibility to override DefaultISR added. 00059 ** - rev. 1.6 (2014-10-14) 00060 ** Renamed interrupt vector LPTimer to LPTMR0 00061 ** - rev. 1.7 (2015-01-21) 00062 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 00063 ** - rev. 1.8 (2015-02-18) 00064 ** Renamed interrupt vector LLW to LLWU 00065 ** - rev. 1.9 (2015-05-19) 00066 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 00067 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 00068 ** Added features for PORT. 00069 ** - rev. 1.10 (2015-05-25) 00070 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 00071 ** - rev. 1.11 (2015-05-27) 00072 ** Several USB features added. 00073 ** 00074 ** ################################################################### 00075 */ 00076 00077 #ifndef _MKL26Z4_FEATURES_H_ 00078 #define _MKL26Z4_FEATURES_H_ 00079 00080 /* SOC module features */ 00081 00082 /* @brief ACMP availability on the SoC. */ 00083 #define FSL_FEATURE_SOC_ACMP_COUNT (0) 00084 /* @brief ADC16 availability on the SoC. */ 00085 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 00086 /* @brief ADC12 availability on the SoC. */ 00087 #define FSL_FEATURE_SOC_ADC12_COUNT (0) 00088 /* @brief AFE availability on the SoC. */ 00089 #define FSL_FEATURE_SOC_AFE_COUNT (0) 00090 /* @brief AIPS availability on the SoC. */ 00091 #define FSL_FEATURE_SOC_AIPS_COUNT (0) 00092 /* @brief AOI availability on the SoC. */ 00093 #define FSL_FEATURE_SOC_AOI_COUNT (0) 00094 /* @brief AXBS availability on the SoC. */ 00095 #define FSL_FEATURE_SOC_AXBS_COUNT (0) 00096 /* @brief ASMC availability on the SoC. */ 00097 #define FSL_FEATURE_SOC_ASMC_COUNT (0) 00098 /* @brief CADC availability on the SoC. */ 00099 #define FSL_FEATURE_SOC_CADC_COUNT (0) 00100 /* @brief FLEXCAN availability on the SoC. */ 00101 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) 00102 /* @brief MMCAU availability on the SoC. */ 00103 #define FSL_FEATURE_SOC_MMCAU_COUNT (0) 00104 /* @brief CMP availability on the SoC. */ 00105 #define FSL_FEATURE_SOC_CMP_COUNT (1) 00106 /* @brief CMT availability on the SoC. */ 00107 #define FSL_FEATURE_SOC_CMT_COUNT (0) 00108 /* @brief CNC availability on the SoC. */ 00109 #define FSL_FEATURE_SOC_CNC_COUNT (0) 00110 /* @brief CRC availability on the SoC. */ 00111 #define FSL_FEATURE_SOC_CRC_COUNT (0) 00112 /* @brief DAC availability on the SoC. */ 00113 #define FSL_FEATURE_SOC_DAC_COUNT (1) 00114 /* @brief DAC32 availability on the SoC. */ 00115 #define FSL_FEATURE_SOC_DAC32_COUNT (0) 00116 /* @brief DCDC availability on the SoC. */ 00117 #define FSL_FEATURE_SOC_DCDC_COUNT (0) 00118 /* @brief DDR availability on the SoC. */ 00119 #define FSL_FEATURE_SOC_DDR_COUNT (0) 00120 /* @brief DMA availability on the SoC. */ 00121 #define FSL_FEATURE_SOC_DMA_COUNT (1) 00122 /* @brief EDMA availability on the SoC. */ 00123 #define FSL_FEATURE_SOC_EDMA_COUNT (0) 00124 /* @brief DMAMUX availability on the SoC. */ 00125 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 00126 /* @brief DRY availability on the SoC. */ 00127 #define FSL_FEATURE_SOC_DRY_COUNT (0) 00128 /* @brief DSPI availability on the SoC. */ 00129 #define FSL_FEATURE_SOC_DSPI_COUNT (0) 00130 /* @brief EMVSIM availability on the SoC. */ 00131 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) 00132 /* @brief ENC availability on the SoC. */ 00133 #define FSL_FEATURE_SOC_ENC_COUNT (0) 00134 /* @brief ENET availability on the SoC. */ 00135 #define FSL_FEATURE_SOC_ENET_COUNT (0) 00136 /* @brief EWM availability on the SoC. */ 00137 #define FSL_FEATURE_SOC_EWM_COUNT (0) 00138 /* @brief FB availability on the SoC. */ 00139 #define FSL_FEATURE_SOC_FB_COUNT (0) 00140 /* @brief FGPIO availability on the SoC. */ 00141 #define FSL_FEATURE_SOC_FGPIO_COUNT (5) 00142 /* @brief FLEXIO availability on the SoC. */ 00143 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) 00144 /* @brief FMC availability on the SoC. */ 00145 #define FSL_FEATURE_SOC_FMC_COUNT (0) 00146 /* @brief FSKDT availability on the SoC. */ 00147 #define FSL_FEATURE_SOC_FSKDT_COUNT (0) 00148 /* @brief FTFA availability on the SoC. */ 00149 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 00150 /* @brief FTFE availability on the SoC. */ 00151 #define FSL_FEATURE_SOC_FTFE_COUNT (0) 00152 /* @brief FTFL availability on the SoC. */ 00153 #define FSL_FEATURE_SOC_FTFL_COUNT (0) 00154 /* @brief FTM availability on the SoC. */ 00155 #define FSL_FEATURE_SOC_FTM_COUNT (0) 00156 /* @brief FTMRA availability on the SoC. */ 00157 #define FSL_FEATURE_SOC_FTMRA_COUNT (0) 00158 /* @brief FTMRE availability on the SoC. */ 00159 #define FSL_FEATURE_SOC_FTMRE_COUNT (0) 00160 /* @brief FTMRH availability on the SoC. */ 00161 #define FSL_FEATURE_SOC_FTMRH_COUNT (0) 00162 /* @brief GPIO availability on the SoC. */ 00163 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 00164 /* @brief HSADC availability on the SoC. */ 00165 #define FSL_FEATURE_SOC_HSADC_COUNT (0) 00166 /* @brief I2C availability on the SoC. */ 00167 #define FSL_FEATURE_SOC_I2C_COUNT (2) 00168 /* @brief I2S availability on the SoC. */ 00169 #define FSL_FEATURE_SOC_I2S_COUNT (1) 00170 /* @brief ICS availability on the SoC. */ 00171 #define FSL_FEATURE_SOC_ICS_COUNT (0) 00172 /* @brief INTMUX availability on the SoC. */ 00173 #define FSL_FEATURE_SOC_INTMUX_COUNT (0) 00174 /* @brief IRQ availability on the SoC. */ 00175 #define FSL_FEATURE_SOC_IRQ_COUNT (0) 00176 /* @brief KBI availability on the SoC. */ 00177 #define FSL_FEATURE_SOC_KBI_COUNT (0) 00178 /* @brief SLCD availability on the SoC. */ 00179 #define FSL_FEATURE_SOC_SLCD_COUNT (0) 00180 /* @brief LCDC availability on the SoC. */ 00181 #define FSL_FEATURE_SOC_LCDC_COUNT (0) 00182 /* @brief LDO availability on the SoC. */ 00183 #define FSL_FEATURE_SOC_LDO_COUNT (0) 00184 /* @brief LLWU availability on the SoC. */ 00185 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 00186 /* @brief LMEM availability on the SoC. */ 00187 #define FSL_FEATURE_SOC_LMEM_COUNT (0) 00188 /* @brief LPI2C availability on the SoC. */ 00189 #define FSL_FEATURE_SOC_LPI2C_COUNT (0) 00190 /* @brief LPIT availability on the SoC. */ 00191 #define FSL_FEATURE_SOC_LPIT_COUNT (0) 00192 /* @brief LPSCI availability on the SoC. */ 00193 #define FSL_FEATURE_SOC_LPSCI_COUNT (1) 00194 /* @brief LPSPI availability on the SoC. */ 00195 #define FSL_FEATURE_SOC_LPSPI_COUNT (0) 00196 /* @brief LPTMR availability on the SoC. */ 00197 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 00198 /* @brief LPTPM availability on the SoC. */ 00199 #define FSL_FEATURE_SOC_LPTPM_COUNT (0) 00200 /* @brief LPUART availability on the SoC. */ 00201 #define FSL_FEATURE_SOC_LPUART_COUNT (0) 00202 /* @brief LTC availability on the SoC. */ 00203 #define FSL_FEATURE_SOC_LTC_COUNT (0) 00204 /* @brief MC availability on the SoC. */ 00205 #define FSL_FEATURE_SOC_MC_COUNT (0) 00206 /* @brief MCG availability on the SoC. */ 00207 #define FSL_FEATURE_SOC_MCG_COUNT (1) 00208 /* @brief MCGLITE availability on the SoC. */ 00209 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) 00210 /* @brief MCM availability on the SoC. */ 00211 #define FSL_FEATURE_SOC_MCM_COUNT (1) 00212 /* @brief MMAU availability on the SoC. */ 00213 #define FSL_FEATURE_SOC_MMAU_COUNT (0) 00214 /* @brief MMDVSQ availability on the SoC. */ 00215 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) 00216 /* @brief MPU availability on the SoC. */ 00217 #define FSL_FEATURE_SOC_MPU_COUNT (0) 00218 /* @brief MSCAN availability on the SoC. */ 00219 #define FSL_FEATURE_SOC_MSCAN_COUNT (0) 00220 /* @brief MSCM availability on the SoC. */ 00221 #define FSL_FEATURE_SOC_MSCM_COUNT (0) 00222 /* @brief MTB availability on the SoC. */ 00223 #define FSL_FEATURE_SOC_MTB_COUNT (1) 00224 /* @brief MTBDWT availability on the SoC. */ 00225 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 00226 /* @brief MU availability on the SoC. */ 00227 #define FSL_FEATURE_SOC_MU_COUNT (0) 00228 /* @brief NFC availability on the SoC. */ 00229 #define FSL_FEATURE_SOC_NFC_COUNT (0) 00230 /* @brief OPAMP availability on the SoC. */ 00231 #define FSL_FEATURE_SOC_OPAMP_COUNT (0) 00232 /* @brief OSC availability on the SoC. */ 00233 #define FSL_FEATURE_SOC_OSC_COUNT (1) 00234 /* @brief OSC32 availability on the SoC. */ 00235 #define FSL_FEATURE_SOC_OSC32_COUNT (0) 00236 /* @brief OTFAD availability on the SoC. */ 00237 #define FSL_FEATURE_SOC_OTFAD_COUNT (0) 00238 /* @brief PDB availability on the SoC. */ 00239 #define FSL_FEATURE_SOC_PDB_COUNT (0) 00240 /* @brief PCC availability on the SoC. */ 00241 #define FSL_FEATURE_SOC_PCC_COUNT (0) 00242 /* @brief PGA availability on the SoC. */ 00243 #define FSL_FEATURE_SOC_PGA_COUNT (0) 00244 /* @brief PIT availability on the SoC. */ 00245 #define FSL_FEATURE_SOC_PIT_COUNT (1) 00246 /* @brief PMC availability on the SoC. */ 00247 #define FSL_FEATURE_SOC_PMC_COUNT (1) 00248 /* @brief PORT availability on the SoC. */ 00249 #define FSL_FEATURE_SOC_PORT_COUNT (5) 00250 /* @brief PWM availability on the SoC. */ 00251 #define FSL_FEATURE_SOC_PWM_COUNT (0) 00252 /* @brief PWT availability on the SoC. */ 00253 #define FSL_FEATURE_SOC_PWT_COUNT (0) 00254 /* @brief QuadSPI availability on the SoC. */ 00255 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) 00256 /* @brief RCM availability on the SoC. */ 00257 #define FSL_FEATURE_SOC_RCM_COUNT (1) 00258 /* @brief RFSYS availability on the SoC. */ 00259 #define FSL_FEATURE_SOC_RFSYS_COUNT (0) 00260 /* @brief RFVBAT availability on the SoC. */ 00261 #define FSL_FEATURE_SOC_RFVBAT_COUNT (0) 00262 /* @brief RNG availability on the SoC. */ 00263 #define FSL_FEATURE_SOC_RNG_COUNT (0) 00264 /* @brief RNGB availability on the SoC. */ 00265 #define FSL_FEATURE_SOC_RNGB_COUNT (0) 00266 /* @brief ROM availability on the SoC. */ 00267 #define FSL_FEATURE_SOC_ROM_COUNT (1) 00268 /* @brief RSIM availability on the SoC. */ 00269 #define FSL_FEATURE_SOC_RSIM_COUNT (0) 00270 /* @brief RTC availability on the SoC. */ 00271 #define FSL_FEATURE_SOC_RTC_COUNT (1) 00272 /* @brief SCG availability on the SoC. */ 00273 #define FSL_FEATURE_SOC_SCG_COUNT (0) 00274 /* @brief SCI availability on the SoC. */ 00275 #define FSL_FEATURE_SOC_SCI_COUNT (0) 00276 /* @brief SDHC availability on the SoC. */ 00277 #define FSL_FEATURE_SOC_SDHC_COUNT (0) 00278 /* @brief SDRAM availability on the SoC. */ 00279 #define FSL_FEATURE_SOC_SDRAM_COUNT (0) 00280 /* @brief SEMA42 availability on the SoC. */ 00281 #define FSL_FEATURE_SOC_SEMA42_COUNT (0) 00282 /* @brief SIM availability on the SoC. */ 00283 #define FSL_FEATURE_SOC_SIM_COUNT (1) 00284 /* @brief SMC availability on the SoC. */ 00285 #define FSL_FEATURE_SOC_SMC_COUNT (1) 00286 /* @brief SPI availability on the SoC. */ 00287 #define FSL_FEATURE_SOC_SPI_COUNT (2) 00288 /* @brief TMR availability on the SoC. */ 00289 #define FSL_FEATURE_SOC_TMR_COUNT (0) 00290 /* @brief TPM availability on the SoC. */ 00291 #define FSL_FEATURE_SOC_TPM_COUNT (3) 00292 /* @brief TRGMUX availability on the SoC. */ 00293 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) 00294 /* @brief TRIAMP availability on the SoC. */ 00295 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) 00296 /* @brief TRNG availability on the SoC. */ 00297 #define FSL_FEATURE_SOC_TRNG_COUNT (0) 00298 /* @brief TSI availability on the SoC. */ 00299 #define FSL_FEATURE_SOC_TSI_COUNT (1) 00300 /* @brief TSTMR availability on the SoC. */ 00301 #define FSL_FEATURE_SOC_TSTMR_COUNT (0) 00302 /* @brief UART availability on the SoC. */ 00303 #define FSL_FEATURE_SOC_UART_COUNT (2) 00304 /* @brief USB availability on the SoC. */ 00305 #define FSL_FEATURE_SOC_USB_COUNT (1) 00306 /* @brief USBDCD availability on the SoC. */ 00307 #define FSL_FEATURE_SOC_USBDCD_COUNT (0) 00308 /* @brief USBHSDCD availability on the SoC. */ 00309 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) 00310 /* @brief USBPHY availability on the SoC. */ 00311 #define FSL_FEATURE_SOC_USBPHY_COUNT (0) 00312 /* @brief VREF availability on the SoC. */ 00313 #define FSL_FEATURE_SOC_VREF_COUNT (0) 00314 /* @brief WDOG availability on the SoC. */ 00315 #define FSL_FEATURE_SOC_WDOG_COUNT (0) 00316 /* @brief XBAR availability on the SoC. */ 00317 #define FSL_FEATURE_SOC_XBAR_COUNT (0) 00318 /* @brief XBARA availability on the SoC. */ 00319 #define FSL_FEATURE_SOC_XBARA_COUNT (0) 00320 /* @brief XBARB availability on the SoC. */ 00321 #define FSL_FEATURE_SOC_XBARB_COUNT (0) 00322 /* @brief XCVR availability on the SoC. */ 00323 #define FSL_FEATURE_SOC_XCVR_COUNT (0) 00324 /* @brief XRDC availability on the SoC. */ 00325 #define FSL_FEATURE_SOC_XRDC_COUNT (0) 00326 /* @brief ZLL availability on the SoC. */ 00327 #define FSL_FEATURE_SOC_ZLL_COUNT (0) 00328 00329 /* ADC16 module features */ 00330 00331 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 00332 #define FSL_FEATURE_ADC16_HAS_PGA (0) 00333 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 00334 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 00335 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 00336 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 00337 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 00338 #define FSL_FEATURE_ADC16_HAS_DMA (1) 00339 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 00340 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 00341 /* @brief Has FIFO (bit SC4[AFDEP]). */ 00342 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 00343 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 00344 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 00345 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 00346 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 00347 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 00348 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 00349 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 00350 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 00351 /* @brief Has HW averaging (bit SC3[AVGE]). */ 00352 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 00353 /* @brief Has offset correction (register OFS). */ 00354 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 00355 /* @brief Maximum ADC resolution. */ 00356 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 00357 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 00358 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 00359 00360 /* CMP module features */ 00361 00362 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 00363 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 00364 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 00365 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 00366 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 00367 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 00368 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 00369 #define FSL_FEATURE_CMP_HAS_DMA (1) 00370 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 00371 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) 00372 /* @brief Has DAC Test function in CMP (register DACTEST). */ 00373 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 00374 00375 /* COP module features */ 00376 00377 /* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ 00378 #define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (0) 00379 /* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ 00380 #define FSL_FEATURE_COP_HAS_STOP_ENABLE (0) 00381 /* @brief Has more clock sources like MCGIRC */ 00382 #define FSL_FEATURE_COP_HAS_MORE_CLKSRC (0) 00383 /* @brief Has the timeout long and short mode bit (COPC[COPCLKSEL] and COPC[COPCLKS]) */ 00384 #define FSL_FEATURE_COP_HAS_LONGTIME_MODE (0) 00385 00386 /* DAC module features */ 00387 00388 /* @brief Define the size of hardware buffer */ 00389 #define FSL_FEATURE_DAC_BUFFER_SIZE (2) 00390 /* @brief Define whether the buffer supports watermark event detection or not. */ 00391 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0) 00392 /* @brief Define whether the buffer supports watermark selection detection or not. */ 00393 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0) 00394 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 00395 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0) 00396 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 00397 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0) 00398 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 00399 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0) 00400 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 00401 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0) 00402 /* @brief Define whether FIFO buffer mode is available or not. */ 00403 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) 00404 /* @brief Define whether swing buffer mode is available or not.. */ 00405 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) 00406 00407 /* DMA module features */ 00408 00409 /* @brief Total number of DMA channels on all modules. */ 00410 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMA_COUNT * 4) 00411 00412 /* DMAMUX module features */ 00413 00414 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 00415 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) 00416 /* @brief Total number of DMA channels on all modules. */ 00417 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) 00418 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 00419 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 00420 00421 /* FLASH module features */ 00422 00423 #if defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) 00424 /* @brief Is of type FTFA. */ 00425 #define FSL_FEATURE_FLASH_IS_FTFA (1) 00426 /* @brief Is of type FTFE. */ 00427 #define FSL_FEATURE_FLASH_IS_FTFE (0) 00428 /* @brief Is of type FTFL. */ 00429 #define FSL_FEATURE_FLASH_IS_FTFL (0) 00430 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 00431 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 00432 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 00433 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 00434 /* @brief Has EEPROM region protection (register FEPROT). */ 00435 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 00436 /* @brief Has data flash region protection (register FDPROT). */ 00437 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 00438 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 00439 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 00440 /* @brief Has flash cache control in FMC module. */ 00441 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 00442 /* @brief Has flash cache control in MCM module. */ 00443 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 00444 /* @brief Has flash cache control in MSCM module. */ 00445 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 00446 /* @brief P-Flash start address. */ 00447 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 00448 /* @brief P-Flash block count. */ 00449 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 00450 /* @brief P-Flash block size. */ 00451 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) 00452 /* @brief P-Flash sector size. */ 00453 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 00454 /* @brief P-Flash write unit size. */ 00455 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 00456 /* @brief P-Flash data path width. */ 00457 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 00458 /* @brief P-Flash block swap feature. */ 00459 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 00460 /* @brief Has FlexNVM memory. */ 00461 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 00462 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 00463 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 00464 /* @brief FlexNVM block count. */ 00465 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 00466 /* @brief FlexNVM block size. */ 00467 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 00468 /* @brief FlexNVM sector size. */ 00469 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 00470 /* @brief FlexNVM write unit size. */ 00471 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 00472 /* @brief FlexNVM data path width. */ 00473 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 00474 /* @brief Has FlexRAM memory. */ 00475 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 00476 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 00477 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 00478 /* @brief FlexRAM size. */ 00479 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 00480 /* @brief Has 0x00 Read 1s Block command. */ 00481 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 00482 /* @brief Has 0x01 Read 1s Section command. */ 00483 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 00484 /* @brief Has 0x02 Program Check command. */ 00485 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 00486 /* @brief Has 0x03 Read Resource command. */ 00487 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 00488 /* @brief Has 0x06 Program Longword command. */ 00489 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 00490 /* @brief Has 0x07 Program Phrase command. */ 00491 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 00492 /* @brief Has 0x08 Erase Flash Block command. */ 00493 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 00494 /* @brief Has 0x09 Erase Flash Sector command. */ 00495 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 00496 /* @brief Has 0x0B Program Section command. */ 00497 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 00498 /* @brief Has 0x40 Read 1s All Blocks command. */ 00499 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 00500 /* @brief Has 0x41 Read Once command. */ 00501 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 00502 /* @brief Has 0x43 Program Once command. */ 00503 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 00504 /* @brief Has 0x44 Erase All Blocks command. */ 00505 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 00506 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 00507 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 00508 /* @brief Has 0x46 Swap Control command. */ 00509 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 00510 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 00511 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 00512 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 00513 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 00514 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 00515 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 00516 /* @brief Has 0x80 Program Partition command. */ 00517 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 00518 /* @brief Has 0x81 Set FlexRAM Function command. */ 00519 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 00520 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 00521 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 00522 /* @brief P-Flash Erase sector command address alignment. */ 00523 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 00524 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 00525 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 00526 /* @brief P-Flash Read resource command address alignment. */ 00527 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 00528 /* @brief P-Flash Program check command address alignment. */ 00529 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 00530 /* @brief P-Flash Program check command address alignment. */ 00531 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 00532 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 00533 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 00534 /* @brief FlexNVM Erase sector command address alignment. */ 00535 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 00536 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 00537 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 00538 /* @brief FlexNVM Read resource command address alignment. */ 00539 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 00540 /* @brief FlexNVM Program check command address alignment. */ 00541 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 00542 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00543 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 00544 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00545 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 00546 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00547 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 00548 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00549 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 00550 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00551 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 00552 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00553 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 00554 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00555 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 00556 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00557 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 00558 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00559 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 00560 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00561 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 00562 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00563 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 00564 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00565 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 00566 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00567 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 00568 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00569 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 00570 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00571 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 00572 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00573 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 00574 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00575 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 00576 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00577 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 00578 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00579 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 00580 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00581 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 00582 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00583 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 00584 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00585 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 00586 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00587 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 00588 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00589 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 00590 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00591 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 00592 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00593 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 00594 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00595 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 00596 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00597 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 00598 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00599 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 00600 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00601 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 00602 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00603 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 00604 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00605 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 00606 #elif defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z128VMC4) 00607 /* @brief Is of type FTFA. */ 00608 #define FSL_FEATURE_FLASH_IS_FTFA (1) 00609 /* @brief Is of type FTFE. */ 00610 #define FSL_FEATURE_FLASH_IS_FTFE (0) 00611 /* @brief Is of type FTFL. */ 00612 #define FSL_FEATURE_FLASH_IS_FTFL (0) 00613 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 00614 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 00615 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 00616 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 00617 /* @brief Has EEPROM region protection (register FEPROT). */ 00618 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 00619 /* @brief Has data flash region protection (register FDPROT). */ 00620 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 00621 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 00622 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 00623 /* @brief Has flash cache control in FMC module. */ 00624 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 00625 /* @brief Has flash cache control in MCM module. */ 00626 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 00627 /* @brief Has flash cache control in MSCM module. */ 00628 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 00629 /* @brief P-Flash start address. */ 00630 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 00631 /* @brief P-Flash block count. */ 00632 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) 00633 /* @brief P-Flash block size. */ 00634 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) 00635 /* @brief P-Flash sector size. */ 00636 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 00637 /* @brief P-Flash write unit size. */ 00638 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 00639 /* @brief P-Flash data path width. */ 00640 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 00641 /* @brief P-Flash block swap feature. */ 00642 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 00643 /* @brief Has FlexNVM memory. */ 00644 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 00645 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 00646 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 00647 /* @brief FlexNVM block count. */ 00648 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 00649 /* @brief FlexNVM block size. */ 00650 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 00651 /* @brief FlexNVM sector size. */ 00652 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 00653 /* @brief FlexNVM write unit size. */ 00654 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 00655 /* @brief FlexNVM data path width. */ 00656 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 00657 /* @brief Has FlexRAM memory. */ 00658 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 00659 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 00660 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 00661 /* @brief FlexRAM size. */ 00662 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 00663 /* @brief Has 0x00 Read 1s Block command. */ 00664 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 00665 /* @brief Has 0x01 Read 1s Section command. */ 00666 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 00667 /* @brief Has 0x02 Program Check command. */ 00668 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 00669 /* @brief Has 0x03 Read Resource command. */ 00670 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 00671 /* @brief Has 0x06 Program Longword command. */ 00672 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 00673 /* @brief Has 0x07 Program Phrase command. */ 00674 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 00675 /* @brief Has 0x08 Erase Flash Block command. */ 00676 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 00677 /* @brief Has 0x09 Erase Flash Sector command. */ 00678 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 00679 /* @brief Has 0x0B Program Section command. */ 00680 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 00681 /* @brief Has 0x40 Read 1s All Blocks command. */ 00682 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 00683 /* @brief Has 0x41 Read Once command. */ 00684 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 00685 /* @brief Has 0x43 Program Once command. */ 00686 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 00687 /* @brief Has 0x44 Erase All Blocks command. */ 00688 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 00689 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 00690 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 00691 /* @brief Has 0x46 Swap Control command. */ 00692 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 00693 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 00694 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 00695 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 00696 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 00697 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 00698 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 00699 /* @brief Has 0x80 Program Partition command. */ 00700 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 00701 /* @brief Has 0x81 Set FlexRAM Function command. */ 00702 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 00703 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 00704 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 00705 /* @brief P-Flash Erase sector command address alignment. */ 00706 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 00707 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 00708 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 00709 /* @brief P-Flash Read resource command address alignment. */ 00710 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 00711 /* @brief P-Flash Program check command address alignment. */ 00712 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 00713 /* @brief P-Flash Program check command address alignment. */ 00714 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 00715 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 00716 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 00717 /* @brief FlexNVM Erase sector command address alignment. */ 00718 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 00719 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 00720 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 00721 /* @brief FlexNVM Read resource command address alignment. */ 00722 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 00723 /* @brief FlexNVM Program check command address alignment. */ 00724 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 00725 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00726 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 00727 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00728 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 00729 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00730 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 00731 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00732 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 00733 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00734 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 00735 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00736 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 00737 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00738 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 00739 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00740 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 00741 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00742 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 00743 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00744 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 00745 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00746 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 00747 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00748 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 00749 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00750 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 00751 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00752 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 00753 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00754 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 00755 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00756 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 00757 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00758 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 00759 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00760 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 00761 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00762 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 00763 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00764 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 00765 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00766 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 00767 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00768 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 00769 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00770 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 00771 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00772 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 00773 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00774 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 00775 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00776 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 00777 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00778 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 00779 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00780 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 00781 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00782 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 00783 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00784 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 00785 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00786 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 00787 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00788 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 00789 #elif defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL26Z256VMP4) 00790 /* @brief Is of type FTFA. */ 00791 #define FSL_FEATURE_FLASH_IS_FTFA (1) 00792 /* @brief Is of type FTFE. */ 00793 #define FSL_FEATURE_FLASH_IS_FTFE (0) 00794 /* @brief Is of type FTFL. */ 00795 #define FSL_FEATURE_FLASH_IS_FTFL (0) 00796 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 00797 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 00798 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 00799 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 00800 /* @brief Has EEPROM region protection (register FEPROT). */ 00801 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 00802 /* @brief Has data flash region protection (register FDPROT). */ 00803 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 00804 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 00805 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 00806 /* @brief Has flash cache control in FMC module. */ 00807 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 00808 /* @brief Has flash cache control in MCM module. */ 00809 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 00810 /* @brief Has flash cache control in MSCM module. */ 00811 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 00812 /* @brief P-Flash start address. */ 00813 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 00814 /* @brief P-Flash block count. */ 00815 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) 00816 /* @brief P-Flash block size. */ 00817 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) 00818 /* @brief P-Flash sector size. */ 00819 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 00820 /* @brief P-Flash write unit size. */ 00821 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 00822 /* @brief P-Flash data path width. */ 00823 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 00824 /* @brief P-Flash block swap feature. */ 00825 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 00826 /* @brief Has FlexNVM memory. */ 00827 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 00828 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 00829 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 00830 /* @brief FlexNVM block count. */ 00831 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 00832 /* @brief FlexNVM block size. */ 00833 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 00834 /* @brief FlexNVM sector size. */ 00835 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 00836 /* @brief FlexNVM write unit size. */ 00837 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 00838 /* @brief FlexNVM data path width. */ 00839 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 00840 /* @brief Has FlexRAM memory. */ 00841 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 00842 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 00843 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 00844 /* @brief FlexRAM size. */ 00845 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 00846 /* @brief Has 0x00 Read 1s Block command. */ 00847 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 00848 /* @brief Has 0x01 Read 1s Section command. */ 00849 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 00850 /* @brief Has 0x02 Program Check command. */ 00851 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 00852 /* @brief Has 0x03 Read Resource command. */ 00853 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 00854 /* @brief Has 0x06 Program Longword command. */ 00855 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 00856 /* @brief Has 0x07 Program Phrase command. */ 00857 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 00858 /* @brief Has 0x08 Erase Flash Block command. */ 00859 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 00860 /* @brief Has 0x09 Erase Flash Sector command. */ 00861 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 00862 /* @brief Has 0x0B Program Section command. */ 00863 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 00864 /* @brief Has 0x40 Read 1s All Blocks command. */ 00865 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 00866 /* @brief Has 0x41 Read Once command. */ 00867 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 00868 /* @brief Has 0x43 Program Once command. */ 00869 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 00870 /* @brief Has 0x44 Erase All Blocks command. */ 00871 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 00872 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 00873 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 00874 /* @brief Has 0x46 Swap Control command. */ 00875 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 00876 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 00877 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 00878 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 00879 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 00880 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 00881 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 00882 /* @brief Has 0x80 Program Partition command. */ 00883 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 00884 /* @brief Has 0x81 Set FlexRAM Function command. */ 00885 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 00886 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 00887 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 00888 /* @brief P-Flash Erase sector command address alignment. */ 00889 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 00890 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 00891 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 00892 /* @brief P-Flash Read resource command address alignment. */ 00893 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 00894 /* @brief P-Flash Program check command address alignment. */ 00895 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 00896 /* @brief P-Flash Program check command address alignment. */ 00897 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 00898 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 00899 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 00900 /* @brief FlexNVM Erase sector command address alignment. */ 00901 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 00902 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 00903 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 00904 /* @brief FlexNVM Read resource command address alignment. */ 00905 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 00906 /* @brief FlexNVM Program check command address alignment. */ 00907 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 00908 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00909 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 00910 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00911 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 00912 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00913 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 00914 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00915 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 00916 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00917 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 00918 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00919 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 00920 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00921 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 00922 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00923 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 00924 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00925 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 00926 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00927 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 00928 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00929 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 00930 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00931 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 00932 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00933 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 00934 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00935 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 00936 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00937 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 00938 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00939 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 00940 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00941 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 00942 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00943 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 00944 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00945 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 00946 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00947 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 00948 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00949 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 00950 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00951 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 00952 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00953 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 00954 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00955 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 00956 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00957 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 00958 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00959 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 00960 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00961 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 00962 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00963 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 00964 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00965 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 00966 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00967 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 00968 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00969 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 00970 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00971 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 00972 #elif defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4) 00973 /* @brief Is of type FTFA. */ 00974 #define FSL_FEATURE_FLASH_IS_FTFA (1) 00975 /* @brief Is of type FTFE. */ 00976 #define FSL_FEATURE_FLASH_IS_FTFE (0) 00977 /* @brief Is of type FTFL. */ 00978 #define FSL_FEATURE_FLASH_IS_FTFL (0) 00979 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 00980 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 00981 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 00982 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 00983 /* @brief Has EEPROM region protection (register FEPROT). */ 00984 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 00985 /* @brief Has data flash region protection (register FDPROT). */ 00986 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 00987 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 00988 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 00989 /* @brief Has flash cache control in FMC module. */ 00990 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 00991 /* @brief Has flash cache control in MCM module. */ 00992 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 00993 /* @brief Has flash cache control in MSCM module. */ 00994 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 00995 /* @brief P-Flash start address. */ 00996 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 00997 /* @brief P-Flash block count. */ 00998 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 00999 /* @brief P-Flash block size. */ 01000 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) 01001 /* @brief P-Flash sector size. */ 01002 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 01003 /* @brief P-Flash write unit size. */ 01004 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 01005 /* @brief P-Flash data path width. */ 01006 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 01007 /* @brief P-Flash block swap feature. */ 01008 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 01009 /* @brief Has FlexNVM memory. */ 01010 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 01011 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 01012 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 01013 /* @brief FlexNVM block count. */ 01014 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 01015 /* @brief FlexNVM block size. */ 01016 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 01017 /* @brief FlexNVM sector size. */ 01018 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 01019 /* @brief FlexNVM write unit size. */ 01020 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 01021 /* @brief FlexNVM data path width. */ 01022 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 01023 /* @brief Has FlexRAM memory. */ 01024 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 01025 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 01026 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 01027 /* @brief FlexRAM size. */ 01028 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 01029 /* @brief Has 0x00 Read 1s Block command. */ 01030 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 01031 /* @brief Has 0x01 Read 1s Section command. */ 01032 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 01033 /* @brief Has 0x02 Program Check command. */ 01034 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 01035 /* @brief Has 0x03 Read Resource command. */ 01036 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 01037 /* @brief Has 0x06 Program Longword command. */ 01038 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 01039 /* @brief Has 0x07 Program Phrase command. */ 01040 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 01041 /* @brief Has 0x08 Erase Flash Block command. */ 01042 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 01043 /* @brief Has 0x09 Erase Flash Sector command. */ 01044 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 01045 /* @brief Has 0x0B Program Section command. */ 01046 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 01047 /* @brief Has 0x40 Read 1s All Blocks command. */ 01048 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 01049 /* @brief Has 0x41 Read Once command. */ 01050 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 01051 /* @brief Has 0x43 Program Once command. */ 01052 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 01053 /* @brief Has 0x44 Erase All Blocks command. */ 01054 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 01055 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 01056 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 01057 /* @brief Has 0x46 Swap Control command. */ 01058 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 01059 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 01060 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 01061 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 01062 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 01063 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 01064 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 01065 /* @brief Has 0x80 Program Partition command. */ 01066 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 01067 /* @brief Has 0x81 Set FlexRAM Function command. */ 01068 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 01069 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 01070 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 01071 /* @brief P-Flash Erase sector command address alignment. */ 01072 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 01073 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 01074 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 01075 /* @brief P-Flash Read resource command address alignment. */ 01076 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 01077 /* @brief P-Flash Program check command address alignment. */ 01078 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 01079 /* @brief P-Flash Program check command address alignment. */ 01080 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 01081 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 01082 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 01083 /* @brief FlexNVM Erase sector command address alignment. */ 01084 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 01085 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 01086 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 01087 /* @brief FlexNVM Read resource command address alignment. */ 01088 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 01089 /* @brief FlexNVM Program check command address alignment. */ 01090 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 01091 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01092 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 01093 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01094 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 01095 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01096 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 01097 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01098 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 01099 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01100 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 01101 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01102 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 01103 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01104 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 01105 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01106 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 01107 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01108 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 01109 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01110 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 01111 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01112 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 01113 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01114 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 01115 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01116 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 01117 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01118 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 01119 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01120 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 01121 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01122 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 01123 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01124 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 01125 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01126 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 01127 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01128 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 01129 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01130 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 01131 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01132 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 01133 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01134 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 01135 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01136 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 01137 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01138 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 01139 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01140 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 01141 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01142 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 01143 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01144 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 01145 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01146 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 01147 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01148 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 01149 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01150 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 01151 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01152 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 01153 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01154 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 01155 #elif defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4) 01156 /* @brief Is of type FTFA. */ 01157 #define FSL_FEATURE_FLASH_IS_FTFA (1) 01158 /* @brief Is of type FTFE. */ 01159 #define FSL_FEATURE_FLASH_IS_FTFE (0) 01160 /* @brief Is of type FTFL. */ 01161 #define FSL_FEATURE_FLASH_IS_FTFL (0) 01162 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 01163 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 01164 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 01165 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 01166 /* @brief Has EEPROM region protection (register FEPROT). */ 01167 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 01168 /* @brief Has data flash region protection (register FDPROT). */ 01169 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 01170 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 01171 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 01172 /* @brief Has flash cache control in FMC module. */ 01173 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 01174 /* @brief Has flash cache control in MCM module. */ 01175 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 01176 /* @brief Has flash cache control in MSCM module. */ 01177 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 01178 /* @brief P-Flash start address. */ 01179 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 01180 /* @brief P-Flash block count. */ 01181 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 01182 /* @brief P-Flash block size. */ 01183 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) 01184 /* @brief P-Flash sector size. */ 01185 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 01186 /* @brief P-Flash write unit size. */ 01187 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 01188 /* @brief P-Flash data path width. */ 01189 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 01190 /* @brief P-Flash block swap feature. */ 01191 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 01192 /* @brief Has FlexNVM memory. */ 01193 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 01194 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 01195 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 01196 /* @brief FlexNVM block count. */ 01197 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 01198 /* @brief FlexNVM block size. */ 01199 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 01200 /* @brief FlexNVM sector size. */ 01201 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 01202 /* @brief FlexNVM write unit size. */ 01203 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 01204 /* @brief FlexNVM data path width. */ 01205 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 01206 /* @brief Has FlexRAM memory. */ 01207 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 01208 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 01209 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 01210 /* @brief FlexRAM size. */ 01211 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 01212 /* @brief Has 0x00 Read 1s Block command. */ 01213 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 01214 /* @brief Has 0x01 Read 1s Section command. */ 01215 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 01216 /* @brief Has 0x02 Program Check command. */ 01217 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 01218 /* @brief Has 0x03 Read Resource command. */ 01219 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 01220 /* @brief Has 0x06 Program Longword command. */ 01221 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 01222 /* @brief Has 0x07 Program Phrase command. */ 01223 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 01224 /* @brief Has 0x08 Erase Flash Block command. */ 01225 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 01226 /* @brief Has 0x09 Erase Flash Sector command. */ 01227 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 01228 /* @brief Has 0x0B Program Section command. */ 01229 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 01230 /* @brief Has 0x40 Read 1s All Blocks command. */ 01231 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 01232 /* @brief Has 0x41 Read Once command. */ 01233 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 01234 /* @brief Has 0x43 Program Once command. */ 01235 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 01236 /* @brief Has 0x44 Erase All Blocks command. */ 01237 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 01238 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 01239 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 01240 /* @brief Has 0x46 Swap Control command. */ 01241 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 01242 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 01243 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 01244 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 01245 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 01246 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 01247 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 01248 /* @brief Has 0x80 Program Partition command. */ 01249 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 01250 /* @brief Has 0x81 Set FlexRAM Function command. */ 01251 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 01252 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 01253 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 01254 /* @brief P-Flash Erase sector command address alignment. */ 01255 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 01256 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 01257 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 01258 /* @brief P-Flash Read resource command address alignment. */ 01259 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 01260 /* @brief P-Flash Program check command address alignment. */ 01261 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 01262 /* @brief P-Flash Program check command address alignment. */ 01263 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 01264 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 01265 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 01266 /* @brief FlexNVM Erase sector command address alignment. */ 01267 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 01268 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 01269 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 01270 /* @brief FlexNVM Read resource command address alignment. */ 01271 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 01272 /* @brief FlexNVM Program check command address alignment. */ 01273 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 01274 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01275 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 01276 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01277 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 01278 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01279 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 01280 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01281 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 01282 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01283 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 01284 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01285 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 01286 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01287 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 01288 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01289 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 01290 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01291 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 01292 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01293 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 01294 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01295 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 01296 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01297 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 01298 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01299 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 01300 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01301 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 01302 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01303 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 01304 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01305 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 01306 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01307 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 01308 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01309 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 01310 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01311 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 01312 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01313 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 01314 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01315 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 01316 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01317 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 01318 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01319 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 01320 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01321 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 01322 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01323 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 01324 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01325 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 01326 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01327 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 01328 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01329 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 01330 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01331 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 01332 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01333 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 01334 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01335 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 01336 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01337 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 01338 #endif /* defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) */ 01339 01340 /* GPIO module features */ 01341 01342 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ 01343 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) 01344 /* @brief Has port input disable register (PIDR). */ 01345 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) 01346 /* @brief Has dedicated interrupt vector. */ 01347 #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) 01348 01349 /* I2C module features */ 01350 01351 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 01352 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 01353 /* @brief Maximum supported baud rate in kilobit per second. */ 01354 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100) 01355 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 01356 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1) 01357 /* @brief Has DMA support (register bit C1[DMAEN]). */ 01358 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 01359 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 01360 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 01361 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 01362 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 01363 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 01364 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 01365 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 01366 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 01367 /* @brief Has control of the drive capability of the I2C pins. */ 01368 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 01369 /* @brief Has double buffering support (register S2). */ 01370 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 01371 /* @brief Has double buffer enable. */ 01372 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 01373 01374 /* SAI module features */ 01375 01376 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 01377 #define FSL_FEATURE_SAI_FIFO_COUNT (1) 01378 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 01379 #define FSL_FEATURE_SAI_CHANNEL_COUNT (1) 01380 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 01381 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2) 01382 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 01383 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) 01384 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 01385 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) 01386 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 01387 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) 01388 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 01389 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) 01390 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 01391 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 01392 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 01393 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) 01394 /* @brief Ihe interrupt source number */ 01395 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) 01396 /* @brief Has register of MCR. */ 01397 #define FSL_FEATURE_SAI_HAS_MCR (1) 01398 /* @brief Has register of MDR */ 01399 #define FSL_FEATURE_SAI_HAS_MDR (1) 01400 01401 /* LLWU module features */ 01402 01403 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 01404 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 01405 /* @brief Has pins 8-15 connected to LLWU device. */ 01406 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 01407 /* @brief Maximum number of internal modules connected to LLWU device. */ 01408 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 01409 /* @brief Number of digital filters. */ 01410 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 01411 /* @brief Has MF register. */ 01412 #define FSL_FEATURE_LLWU_HAS_MF (0) 01413 /* @brief Has PF register. */ 01414 #define FSL_FEATURE_LLWU_HAS_PF (0) 01415 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 01416 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 01417 /* @brief Has external pin 0 connected to LLWU device. */ 01418 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) 01419 /* @brief Index of port of external pin. */ 01420 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) 01421 /* @brief Number of external pin port on specified port. */ 01422 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) 01423 /* @brief Has external pin 1 connected to LLWU device. */ 01424 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 01425 /* @brief Index of port of external pin. */ 01426 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 01427 /* @brief Number of external pin port on specified port. */ 01428 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 01429 /* @brief Has external pin 2 connected to LLWU device. */ 01430 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 01431 /* @brief Index of port of external pin. */ 01432 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 01433 /* @brief Number of external pin port on specified port. */ 01434 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 01435 /* @brief Has external pin 3 connected to LLWU device. */ 01436 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0) 01437 /* @brief Index of port of external pin. */ 01438 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0) 01439 /* @brief Number of external pin port on specified port. */ 01440 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0) 01441 /* @brief Has external pin 4 connected to LLWU device. */ 01442 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) 01443 /* @brief Index of port of external pin. */ 01444 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) 01445 /* @brief Number of external pin port on specified port. */ 01446 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 01447 /* @brief Has external pin 5 connected to LLWU device. */ 01448 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 01449 /* @brief Index of port of external pin. */ 01450 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 01451 /* @brief Number of external pin port on specified port. */ 01452 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 01453 /* @brief Has external pin 6 connected to LLWU device. */ 01454 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 01455 /* @brief Index of port of external pin. */ 01456 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 01457 /* @brief Number of external pin port on specified port. */ 01458 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 01459 /* @brief Has external pin 7 connected to LLWU device. */ 01460 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 01461 /* @brief Index of port of external pin. */ 01462 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 01463 /* @brief Number of external pin port on specified port. */ 01464 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 01465 /* @brief Has external pin 8 connected to LLWU device. */ 01466 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 01467 /* @brief Index of port of external pin. */ 01468 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 01469 /* @brief Number of external pin port on specified port. */ 01470 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 01471 /* @brief Has external pin 9 connected to LLWU device. */ 01472 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 01473 /* @brief Index of port of external pin. */ 01474 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 01475 /* @brief Number of external pin port on specified port. */ 01476 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 01477 /* @brief Has external pin 10 connected to LLWU device. */ 01478 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 01479 /* @brief Index of port of external pin. */ 01480 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 01481 /* @brief Number of external pin port on specified port. */ 01482 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 01483 /* @brief Has external pin 11 connected to LLWU device. */ 01484 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) 01485 /* @brief Index of port of external pin. */ 01486 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) 01487 /* @brief Number of external pin port on specified port. */ 01488 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 01489 /* @brief Has external pin 12 connected to LLWU device. */ 01490 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) 01491 /* @brief Index of port of external pin. */ 01492 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) 01493 /* @brief Number of external pin port on specified port. */ 01494 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 01495 /* @brief Has external pin 13 connected to LLWU device. */ 01496 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0) 01497 /* @brief Index of port of external pin. */ 01498 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0) 01499 /* @brief Number of external pin port on specified port. */ 01500 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0) 01501 /* @brief Has external pin 14 connected to LLWU device. */ 01502 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 01503 /* @brief Index of port of external pin. */ 01504 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 01505 /* @brief Number of external pin port on specified port. */ 01506 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 01507 /* @brief Has external pin 15 connected to LLWU device. */ 01508 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 01509 /* @brief Index of port of external pin. */ 01510 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 01511 /* @brief Number of external pin port on specified port. */ 01512 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 01513 /* @brief Has external pin 16 connected to LLWU device. */ 01514 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 01515 /* @brief Index of port of external pin. */ 01516 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 01517 /* @brief Number of external pin port on specified port. */ 01518 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 01519 /* @brief Has external pin 17 connected to LLWU device. */ 01520 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 01521 /* @brief Index of port of external pin. */ 01522 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 01523 /* @brief Number of external pin port on specified port. */ 01524 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 01525 /* @brief Has external pin 18 connected to LLWU device. */ 01526 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 01527 /* @brief Index of port of external pin. */ 01528 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 01529 /* @brief Number of external pin port on specified port. */ 01530 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 01531 /* @brief Has external pin 19 connected to LLWU device. */ 01532 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 01533 /* @brief Index of port of external pin. */ 01534 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 01535 /* @brief Number of external pin port on specified port. */ 01536 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 01537 /* @brief Has external pin 20 connected to LLWU device. */ 01538 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 01539 /* @brief Index of port of external pin. */ 01540 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 01541 /* @brief Number of external pin port on specified port. */ 01542 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 01543 /* @brief Has external pin 21 connected to LLWU device. */ 01544 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 01545 /* @brief Index of port of external pin. */ 01546 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 01547 /* @brief Number of external pin port on specified port. */ 01548 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 01549 /* @brief Has external pin 22 connected to LLWU device. */ 01550 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 01551 /* @brief Index of port of external pin. */ 01552 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 01553 /* @brief Number of external pin port on specified port. */ 01554 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 01555 /* @brief Has external pin 23 connected to LLWU device. */ 01556 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 01557 /* @brief Index of port of external pin. */ 01558 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 01559 /* @brief Number of external pin port on specified port. */ 01560 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 01561 /* @brief Has external pin 24 connected to LLWU device. */ 01562 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 01563 /* @brief Index of port of external pin. */ 01564 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 01565 /* @brief Number of external pin port on specified port. */ 01566 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 01567 /* @brief Has external pin 25 connected to LLWU device. */ 01568 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 01569 /* @brief Index of port of external pin. */ 01570 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 01571 /* @brief Number of external pin port on specified port. */ 01572 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 01573 /* @brief Has external pin 26 connected to LLWU device. */ 01574 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 01575 /* @brief Index of port of external pin. */ 01576 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 01577 /* @brief Number of external pin port on specified port. */ 01578 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 01579 /* @brief Has external pin 27 connected to LLWU device. */ 01580 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 01581 /* @brief Index of port of external pin. */ 01582 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 01583 /* @brief Number of external pin port on specified port. */ 01584 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 01585 /* @brief Has external pin 28 connected to LLWU device. */ 01586 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 01587 /* @brief Index of port of external pin. */ 01588 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 01589 /* @brief Number of external pin port on specified port. */ 01590 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 01591 /* @brief Has external pin 29 connected to LLWU device. */ 01592 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 01593 /* @brief Index of port of external pin. */ 01594 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 01595 /* @brief Number of external pin port on specified port. */ 01596 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 01597 /* @brief Has external pin 30 connected to LLWU device. */ 01598 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 01599 /* @brief Index of port of external pin. */ 01600 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 01601 /* @brief Number of external pin port on specified port. */ 01602 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 01603 /* @brief Has external pin 31 connected to LLWU device. */ 01604 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 01605 /* @brief Index of port of external pin. */ 01606 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 01607 /* @brief Number of external pin port on specified port. */ 01608 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 01609 /* @brief Has internal module 0 connected to LLWU device. */ 01610 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 01611 /* @brief Has internal module 1 connected to LLWU device. */ 01612 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 01613 /* @brief Has internal module 2 connected to LLWU device. */ 01614 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0) 01615 /* @brief Has internal module 3 connected to LLWU device. */ 01616 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 01617 /* @brief Has internal module 4 connected to LLWU device. */ 01618 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 01619 /* @brief Has internal module 5 connected to LLWU device. */ 01620 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 01621 /* @brief Has internal module 6 connected to LLWU device. */ 01622 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 01623 /* @brief Has internal module 7 connected to LLWU device. */ 01624 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 01625 /* @brief Has Version ID Register (LLWU_VERID). */ 01626 #define FSL_FEATURE_LLWU_HAS_VERID (0) 01627 /* @brief Has Parameter Register (LLWU_PARAM). */ 01628 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 01629 /* @brief Width of registers of the LLWU. */ 01630 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 01631 /* @brief Has DMA Enable register (LLWU_DE). */ 01632 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 01633 01634 /* LPTMR module features */ 01635 01636 /* @brief Has shared interrupt handler with another LPTMR module. */ 01637 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 01638 01639 /* MCG module features */ 01640 01641 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 01642 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 01643 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 01644 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) 01645 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 01646 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) 01647 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 01648 #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) 01649 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 01650 #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) 01651 /* @brief The PLL clock is divided by 2 before VCO divider. */ 01652 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 01653 /* @brief FRDIV supports 1280. */ 01654 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 01655 /* @brief FRDIV supports 1536. */ 01656 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 01657 /* @brief MCGFFCLK divider. */ 01658 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 01659 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 01660 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 01661 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 01662 #define FSL_FEATURE_MCG_HAS_RTC_32K (0) 01663 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 01664 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 01665 /* @brief Has 48MHz internal oscillator. */ 01666 #define FSL_FEATURE_MCG_HAS_IRC_48M (0) 01667 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 01668 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 01669 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 01670 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 01671 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 01672 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 01673 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 01674 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 01675 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 01676 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 01677 /* @brief TBD */ 01678 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 01679 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ 01680 #define FSL_FEATURE_MCG_HAS_PLL (1) 01681 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 01682 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 01683 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 01684 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 01685 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 01686 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) 01687 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 01688 #define FSL_FEATURE_MCG_HAS_FLL (1) 01689 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 01690 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 01691 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 01692 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 01693 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 01694 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 01695 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 01696 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 01697 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 01698 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 01699 /* @brief Has external clock monitor (register bit C6[CME]). */ 01700 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 01701 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 01702 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 01703 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 01704 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 01705 /* @brief Has PEI mode or PBI mode. */ 01706 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 01707 /* @brief Reset clock mode is BLPI. */ 01708 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 01709 01710 /* interrupt module features */ 01711 01712 /* @brief Lowest interrupt request number. */ 01713 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 01714 /* @brief Highest interrupt request number. */ 01715 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) 01716 01717 /* OSC module features */ 01718 01719 /* @brief Has OSC1 external oscillator. */ 01720 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 01721 /* @brief Has OSC0 external oscillator. */ 01722 #define FSL_FEATURE_OSC_HAS_OSC0 (1) 01723 /* @brief Has OSC external oscillator (without index). */ 01724 #define FSL_FEATURE_OSC_HAS_OSC (0) 01725 /* @brief Number of OSC external oscillators. */ 01726 #define FSL_FEATURE_OSC_OSC_COUNT (1) 01727 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 01728 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 01729 01730 /* PIT module features */ 01731 01732 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 01733 #define FSL_FEATURE_PIT_TIMER_COUNT (2) 01734 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 01735 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 01736 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 01737 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 01738 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 01739 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) 01740 01741 /* PMC module features */ 01742 01743 /* @brief Has Bandgap Enable In VLPx Operation support. */ 01744 #define FSL_FEATURE_PMC_HAS_BGEN (1) 01745 /* @brief Has Bandgap Buffer Enable. */ 01746 #define FSL_FEATURE_PMC_HAS_BGBE (1) 01747 /* @brief Has Bandgap Buffer Drive Select. */ 01748 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 01749 /* @brief Has Low-Voltage Detect Voltage Select support. */ 01750 #define FSL_FEATURE_PMC_HAS_LVDV (1) 01751 /* @brief Has Low-Voltage Warning Voltage Select support. */ 01752 #define FSL_FEATURE_PMC_HAS_LVWV (1) 01753 /* @brief Has LPO. */ 01754 #define FSL_FEATURE_PMC_HAS_LPO (0) 01755 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 01756 #define FSL_FEATURE_PMC_HAS_VLPO (0) 01757 /* @brief Has acknowledge isolation support. */ 01758 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 01759 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 01760 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 01761 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 01762 #define FSL_FEATURE_PMC_HAS_REGONS (1) 01763 /* @brief Has PMC_HVDSC1. */ 01764 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 01765 /* @brief Has PMC_PARAM. */ 01766 #define FSL_FEATURE_PMC_HAS_PARAM (0) 01767 /* @brief Has PMC_VERID. */ 01768 #define FSL_FEATURE_PMC_HAS_VERID (0) 01769 01770 /* PORT module features */ 01771 01772 /* @brief Has control lock (register bit PCR[LK]). */ 01773 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) 01774 /* @brief Has open drain control (register bit PCR[ODE]). */ 01775 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 01776 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 01777 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) 01778 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 01779 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 01780 /* @brief Has pull resistor selection available. */ 01781 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 01782 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 01783 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 01784 /* @brief Has slew rate control (register bit PCR[SRE]). */ 01785 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 01786 /* @brief Has passive filter (register bit field PCR[PFE]). */ 01787 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 01788 /* @brief Has drive strength control (register bit PCR[DSE]). */ 01789 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 01790 /* @brief Has separate drive strength register (HDRVE). */ 01791 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 01792 /* @brief Has glitch filter (register IOFLT). */ 01793 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 01794 /* @brief Defines width of PCR[MUX] field. */ 01795 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 01796 /* @brief Has dedicated interrupt vector. */ 01797 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 01798 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 01799 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 01800 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 01801 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 01802 01803 /* RCM module features */ 01804 01805 /* @brief Has Loss-of-Lock Reset support. */ 01806 #define FSL_FEATURE_RCM_HAS_LOL (1) 01807 /* @brief Has Loss-of-Clock Reset support. */ 01808 #define FSL_FEATURE_RCM_HAS_LOC (1) 01809 /* @brief Has JTAG generated Reset support. */ 01810 #define FSL_FEATURE_RCM_HAS_JTAG (0) 01811 /* @brief Has EzPort generated Reset support. */ 01812 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 01813 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 01814 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 01815 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 01816 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 01817 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 01818 #define FSL_FEATURE_RCM_HAS_SSRS (0) 01819 /* @brief Has Version ID Register (RCM_VERID). */ 01820 #define FSL_FEATURE_RCM_HAS_VERID (0) 01821 /* @brief Has Parameter Register (RCM_PARAM). */ 01822 #define FSL_FEATURE_RCM_HAS_PARAM (0) 01823 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 01824 #define FSL_FEATURE_RCM_HAS_SRIE (0) 01825 /* @brief Width of registers of the RCM. */ 01826 #define FSL_FEATURE_RCM_REG_WIDTH (8) 01827 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 01828 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 01829 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 01830 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 01831 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 01832 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 01833 01834 /* RTC module features */ 01835 01836 #if defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) || \ 01837 defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VFM4) || \ 01838 defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4) 01839 /* @brief Has wakeup pin. */ 01840 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) 01841 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 01842 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 01843 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 01844 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 01845 /* @brief Has read/write access control (registers WAR and RAR). */ 01846 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) 01847 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 01848 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 01849 /* @brief Has RTC_CLKIN available. */ 01850 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) 01851 /* @brief Has prescaler adjust for LPO. */ 01852 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 01853 /* @brief Has Clock Pin Enable field. */ 01854 #define FSL_FEATURE_RTC_HAS_CPE (0) 01855 /* @brief Has Timer Seconds Interrupt Configuration field. */ 01856 #define FSL_FEATURE_RTC_HAS_TSIC (0) 01857 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 01858 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 01859 #elif defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLL4) || \ 01860 defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL26Z256VMP4) 01861 /* @brief Has wakeup pin. */ 01862 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 01863 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 01864 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 01865 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 01866 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 01867 /* @brief Has read/write access control (registers WAR and RAR). */ 01868 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) 01869 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 01870 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 01871 /* @brief Has RTC_CLKIN available. */ 01872 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) 01873 /* @brief Has prescaler adjust for LPO. */ 01874 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 01875 /* @brief Has Clock Pin Enable field. */ 01876 #define FSL_FEATURE_RTC_HAS_CPE (0) 01877 /* @brief Has Timer Seconds Interrupt Configuration field. */ 01878 #define FSL_FEATURE_RTC_HAS_TSIC (0) 01879 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 01880 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 01881 #endif /* defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) || \ 01882 defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VFM4) || \ 01883 defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4) */ 01884 01885 /* SIM module features */ 01886 01887 /* @brief Has USB FS divider. */ 01888 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 01889 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 01890 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1) 01891 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 01892 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) 01893 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 01894 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 01895 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 01896 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 01897 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 01898 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 01899 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 01900 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) 01901 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 01902 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) 01903 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 01904 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 01905 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 01906 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 01907 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 01908 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 01909 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 01910 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 01911 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 01912 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 01913 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 01914 #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) 01915 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 01916 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 01917 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 01918 #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) 01919 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 01920 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (1) 01921 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 01922 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (1) 01923 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 01924 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1) 01925 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 01926 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 01927 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 01928 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 01929 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 01930 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 01931 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 01932 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 01933 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 01934 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 01935 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 01936 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 01937 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 01938 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 01939 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 01940 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 01941 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 01942 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 01943 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 01944 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 01945 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 01946 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) 01947 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 01948 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 01949 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 01950 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 01951 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 01952 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1) 01953 /* @brief Has FTM module(s) configuration. */ 01954 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) 01955 /* @brief Number of FTM modules. */ 01956 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) 01957 /* @brief Number of FTM triggers with selectable source. */ 01958 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) 01959 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 01960 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) 01961 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 01962 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 01963 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 01964 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) 01965 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 01966 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) 01967 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 01968 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 01969 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 01970 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 01971 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 01972 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) 01973 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 01974 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) 01975 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 01976 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) 01977 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 01978 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 01979 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 01980 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 01981 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 01982 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 01983 /* @brief Has TPM module(s) configuration. */ 01984 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) 01985 /* @brief The highest TPM module index. */ 01986 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) 01987 /* @brief Has TPM module with index 0. */ 01988 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) 01989 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 01990 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) 01991 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 01992 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) 01993 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 01994 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) 01995 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 01996 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) 01997 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 01998 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) 01999 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 02000 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) 02001 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 02002 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) 02003 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 02004 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 02005 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 02006 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 02007 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 02008 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 02009 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 02010 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 02011 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 02012 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 02013 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 02014 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 02015 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 02016 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 02017 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 02018 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 02019 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 02020 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) 02021 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 02022 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 02023 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 02024 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 02025 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 02026 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 02027 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 02028 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 02029 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 02030 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 02031 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 02032 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 02033 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 02034 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) 02035 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 02036 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) 02037 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 02038 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) 02039 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 02040 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) 02041 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 02042 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) 02043 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 02044 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) 02045 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 02046 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 02047 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 02048 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 02049 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 02050 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 02051 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 02052 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 02053 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 02054 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 02055 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 02056 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 02057 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 02058 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 02059 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 02060 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 02061 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 02062 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) 02063 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 02064 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 02065 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 02066 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 02067 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 02068 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) 02069 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 02070 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 02071 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 02072 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 02073 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 02074 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 02075 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 02076 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 02077 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 02078 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 02079 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 02080 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 02081 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 02082 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 02083 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 02084 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 02085 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 02086 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 02087 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 02088 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 02089 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 02090 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 02091 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 02092 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 02093 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 02094 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 02095 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 02096 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) 02097 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 02098 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 02099 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 02100 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 02101 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 02102 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 02103 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 02104 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 02105 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 02106 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 02107 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 02108 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 02109 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 02110 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 02111 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 02112 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) 02113 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 02114 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 02115 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 02116 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 02117 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 02118 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 02119 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 02120 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 02121 /* @brief Has miscellanious control register (register MCR). */ 02122 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 02123 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 02124 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) 02125 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 02126 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 02127 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 02128 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 02129 02130 /* SMC module features */ 02131 02132 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 02133 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 02134 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 02135 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 02136 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 02137 #define FSL_FEATURE_SMC_HAS_PORPO (1) 02138 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 02139 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 02140 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 02141 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 02142 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 02143 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 02144 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 02145 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) 02146 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 02147 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 02148 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 02149 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 02150 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 02151 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 02152 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 02153 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 02154 /* @brief Has stop submode. */ 02155 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 02156 /* @brief Has stop submode 0(VLLS0). */ 02157 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 02158 /* @brief Has stop submode 2(VLLS2). */ 02159 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) 02160 /* @brief Has SMC_PARAM. */ 02161 #define FSL_FEATURE_SMC_HAS_PARAM (0) 02162 /* @brief Has SMC_VERID. */ 02163 #define FSL_FEATURE_SMC_HAS_VERID (0) 02164 02165 /* SPI module features */ 02166 02167 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 02168 #define FSL_FEATURE_SPI_HAS_FIFO (1) 02169 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */ 02170 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) 02171 /* @brief Has separate DMA RX and TX requests. */ 02172 #define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 02173 /* @brief Receive/transmit FIFO size in number of 16-bit communication items. */ 02174 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \ 02175 ((x) == SPI0 ? (0) : \ 02176 ((x) == SPI1 ? (4) : (-1))) 02177 /* @brief Maximum transfer data width in bits. */ 02178 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) 02179 /* @brief The data register name has postfix (L as low and H as high). */ 02180 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1) 02181 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 02182 #define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 02183 /* @brief Has 16-bit data transfer support. */ 02184 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (1) 02185 02186 /* SysTick module features */ 02187 02188 /* @brief Systick has external reference clock. */ 02189 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) 02190 /* @brief Systick external reference clock is core clock divided by this value. */ 02191 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) 02192 02193 /* TPM module features */ 02194 02195 /* @brief Bus clock is the source clock for the module. */ 02196 #define FSL_FEATURE_TPM_BUS_CLOCK (0) 02197 /* @brief Number of channels. */ 02198 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ 02199 ((x) == TPM0 ? (6) : \ 02200 ((x) == TPM1 ? (2) : \ 02201 ((x) == TPM2 ? (2) : (-1)))) 02202 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 02203 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 02204 /* @brief Has TPM_PARAM. */ 02205 #define FSL_FEATURE_TPM_HAS_PARAM (0) 02206 /* @brief Has TPM_VERID. */ 02207 #define FSL_FEATURE_TPM_HAS_VERID (0) 02208 /* @brief Has TPM_GLOBAL. */ 02209 #define FSL_FEATURE_TPM_HAS_GLOBAL (0) 02210 /* @brief Has TPM_TRIG. */ 02211 #define FSL_FEATURE_TPM_HAS_TRIG (0) 02212 /* @brief Has counter pause on trigger. */ 02213 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (0) 02214 /* @brief Has external trigger selection. */ 02215 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (0) 02216 /* @brief Has TPM_COMBINE. */ 02217 #define FSL_FEATURE_TPM_HAS_COMBINE (0) 02218 /* @brief Has TPM_POL. */ 02219 #define FSL_FEATURE_TPM_HAS_POL (0) 02220 /* @brief Has TPM_FILTER. */ 02221 #define FSL_FEATURE_TPM_HAS_FILTER (0) 02222 /* @brief Has TPM_QDCTRL. */ 02223 #define FSL_FEATURE_TPM_HAS_QDCTRL (0) 02224 02225 /* TSI module features */ 02226 02227 /* @brief TSI module version. */ 02228 #define FSL_FEATURE_TSI_VERSION (4) 02229 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ 02230 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) 02231 /* @brief Number of TSI channels. */ 02232 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16) 02233 02234 /* LPSCI module features */ 02235 02236 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 02237 #define FSL_FEATURE_LPSCI_HAS_IRQ_EXTENDED_FUNCTIONS (1) 02238 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 02239 #define FSL_FEATURE_LPSCI_HAS_LOW_POWER_UART_SUPPORT (1) 02240 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 02241 #define FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) 02242 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 02243 #define FSL_FEATURE_LPSCI_HAS_FIFO (0) 02244 /* @brief Hardware flow control (RTS, CTS) is supported. */ 02245 #define FSL_FEATURE_LPSCI_HAS_MODEM_SUPPORT (0) 02246 /* @brief Infrared (modulation) is supported. */ 02247 #define FSL_FEATURE_LPSCI_HAS_IR_SUPPORT (0) 02248 /* @brief 2 bits long stop bit is available. */ 02249 #define FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT (1) 02250 /* @brief If 10-bit mode is supported. */ 02251 #define FSL_FEATURE_LPSCI_HAS_10BIT_DATA_SUPPORT (1) 02252 /* @brief Baud rate fine adjustment is available. */ 02253 #define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 02254 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 02255 #define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 02256 /* @brief Baud rate oversampling is available. */ 02257 #define FSL_FEATURE_LPSCI_HAS_RX_RESYNC_SUPPORT (1) 02258 /* @brief Baud rate oversampling is available. */ 02259 #define FSL_FEATURE_LPSCI_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 02260 /* @brief Peripheral type. */ 02261 #define FSL_FEATURE_LPSCI_IS_SCI (1) 02262 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 02263 #define FSL_FEATURE_LPSCI_FIFO_SIZE (0) 02264 /* @brief Maximal data width without parity bit. */ 02265 #define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_NO_PARITY (10) 02266 /* @brief Maximal data width with parity bit. */ 02267 #define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_PARITY (9) 02268 /* @brief Supports two match addresses to filter incoming frames. */ 02269 #define FSL_FEATURE_LPSCI_HAS_ADDRESS_MATCHING (1) 02270 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 02271 #define FSL_FEATURE_LPSCI_HAS_DMA_ENABLE (1) 02272 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 02273 #define FSL_FEATURE_LPSCI_HAS_DMA_SELECT (0) 02274 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 02275 #define FSL_FEATURE_LPSCI_HAS_BIT_ORDER_SELECT (1) 02276 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 02277 #define FSL_FEATURE_LPSCI_HAS_SMART_CARD_SUPPORT (0) 02278 /* @brief Has improved smart card (ISO7816 protocol) support. */ 02279 #define FSL_FEATURE_LPSCI_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 02280 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 02281 #define FSL_FEATURE_LPSCI_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 02282 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 02283 #define FSL_FEATURE_LPSCI_HAS_32BIT_REGISTERS (0) 02284 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 02285 #define FSL_FEATURE_LPSCI_HAS_LIN_BREAK_DETECT (1) 02286 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 02287 #define FSL_FEATURE_LPSCI_HAS_WAIT_MODE_OPERATION (0) 02288 /* @brief Has separate DMA RX and TX requests. */ 02289 #define FSL_FEATURE_LPSCI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 02290 02291 /* UART module features */ 02292 02293 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 02294 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 02295 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 02296 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 02297 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 02298 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) 02299 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 02300 #define FSL_FEATURE_UART_HAS_FIFO (0) 02301 /* @brief Hardware flow control (RTS, CTS) is supported. */ 02302 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) 02303 /* @brief Infrared (modulation) is supported. */ 02304 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) 02305 /* @brief 2 bits long stop bit is available. */ 02306 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 02307 /* @brief If 10-bit mode is supported. */ 02308 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) 02309 /* @brief Baud rate fine adjustment is available. */ 02310 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 02311 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 02312 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 02313 /* @brief Baud rate oversampling is available. */ 02314 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1) 02315 /* @brief Baud rate oversampling is available. */ 02316 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 02317 /* @brief Peripheral type. */ 02318 #define FSL_FEATURE_UART_IS_SCI (1) 02319 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 02320 #define FSL_FEATURE_UART_FIFO_SIZE (0) 02321 /* @brief Maximal data width without parity bit. */ 02322 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) 02323 /* @brief Maximal data width with parity bit. */ 02324 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (8) 02325 /* @brief Supports two match addresses to filter incoming frames. */ 02326 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (0) 02327 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 02328 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 02329 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 02330 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 02331 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 02332 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (0) 02333 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 02334 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) 02335 /* @brief Has improved smart card (ISO7816 protocol) support. */ 02336 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 02337 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 02338 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 02339 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 02340 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 02341 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 02342 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 02343 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 02344 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 02345 /* @brief Has separate DMA RX and TX requests. */ 02346 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 02347 02348 /* USB module features */ 02349 02350 /* @brief HOST mode enabled */ 02351 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) 02352 /* @brief OTG mode enabled */ 02353 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) 02354 /* @brief Size of the USB dedicated RAM */ 02355 #define FSL_FEATURE_USB_KHCI_USB_RAM (0) 02356 /* @brief Has KEEP_ALIVE_CTRL register */ 02357 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) 02358 /* @brief Has the Dynamic SOF threshold compare support */ 02359 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) 02360 /* @brief Has the VBUS detect support */ 02361 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) 02362 /* @brief Has the IRC48M module clock support */ 02363 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0) 02364 /* @brief Number of endpoints supported */ 02365 #define FSL_FEATURE_USB_ENDPT_COUNT (16) 02366 02367 #endif /* _MKL26Z4_FEATURES_H_ */ 02368
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