MK26F18_features.h

00001 /*
00002 ** ###################################################################
00003 **     Version:             rev. 1.6, 2015-06-08
00004 **     Build:               b180801
00005 **
00006 **     Abstract:
00007 **         Chip specific module features.
00008 **
00009 **     Copyright 2016 Freescale Semiconductor, Inc.
00010 **     Copyright 2016-2018 NXP
00011 **
00012 **     SPDX-License-Identifier: BSD-3-Clause
00013 **
00014 **     http:                 www.nxp.com
00015 **     mail:                 support@nxp.com
00016 **
00017 **     Revisions:
00018 **     - rev. 1.0 (2014-12-04)
00019 **         Initial version.
00020 **     - rev. 1.1 (2015-01-21)
00021 **         Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
00022 **     - rev. 1.2 (2015-02-19)
00023 **         Renamed interrupt vector LLW to LLWU.
00024 **     - rev. 1.3 (2015-05-19)
00025 **         FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
00026 **         Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
00027 **         Added features for PDB and PORT.
00028 **     - rev. 1.4 (2015-05-25)
00029 **         Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
00030 **     - rev. 1.5 (2015-05-27)
00031 **         Several USB features added.
00032 **     - rev. 1.6 (2015-06-08)
00033 **         FTM features BUS_CLOCK and FAST_CLOCK removed.
00034 **
00035 ** ###################################################################
00036 */
00037 
00038 #ifndef _MK26F18_FEATURES_H_
00039 #define _MK26F18_FEATURES_H_
00040 
00041 /* SOC module features */
00042 
00043 /* @brief ADC16 availability on the SoC. */
00044 #define FSL_FEATURE_SOC_ADC16_COUNT (2)
00045 /* @brief AIPS availability on the SoC. */
00046 #define FSL_FEATURE_SOC_AIPS_COUNT (2)
00047 /* @brief AXBS availability on the SoC. */
00048 #define FSL_FEATURE_SOC_AXBS_COUNT (1)
00049 /* @brief FLEXCAN availability on the SoC. */
00050 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
00051 /* @brief MMCAU availability on the SoC. */
00052 #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
00053 /* @brief CMP availability on the SoC. */
00054 #define FSL_FEATURE_SOC_CMP_COUNT (4)
00055 /* @brief CMT availability on the SoC. */
00056 #define FSL_FEATURE_SOC_CMT_COUNT (1)
00057 /* @brief CRC availability on the SoC. */
00058 #define FSL_FEATURE_SOC_CRC_COUNT (1)
00059 /* @brief DAC availability on the SoC. */
00060 #define FSL_FEATURE_SOC_DAC_COUNT (2)
00061 /* @brief EDMA availability on the SoC. */
00062 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
00063 /* @brief DMAMUX availability on the SoC. */
00064 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
00065 /* @brief DSPI availability on the SoC. */
00066 #define FSL_FEATURE_SOC_DSPI_COUNT (3)
00067 /* @brief EWM availability on the SoC. */
00068 #define FSL_FEATURE_SOC_EWM_COUNT (1)
00069 /* @brief FB availability on the SoC. */
00070 #define FSL_FEATURE_SOC_FB_COUNT (1)
00071 /* @brief FMC availability on the SoC. */
00072 #define FSL_FEATURE_SOC_FMC_COUNT (1)
00073 /* @brief FTFE availability on the SoC. */
00074 #define FSL_FEATURE_SOC_FTFE_COUNT (1)
00075 /* @brief FTM availability on the SoC. */
00076 #define FSL_FEATURE_SOC_FTM_COUNT (4)
00077 /* @brief GPIO availability on the SoC. */
00078 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
00079 /* @brief I2C availability on the SoC. */
00080 #define FSL_FEATURE_SOC_I2C_COUNT (4)
00081 /* @brief I2S availability on the SoC. */
00082 #define FSL_FEATURE_SOC_I2S_COUNT (1)
00083 /* @brief LLWU availability on the SoC. */
00084 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
00085 /* @brief LMEM availability on the SoC. */
00086 #define FSL_FEATURE_SOC_LMEM_COUNT (1)
00087 /* @brief LPTMR availability on the SoC. */
00088 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
00089 /* @brief LPUART availability on the SoC. */
00090 #define FSL_FEATURE_SOC_LPUART_COUNT (1)
00091 /* @brief MCG availability on the SoC. */
00092 #define FSL_FEATURE_SOC_MCG_COUNT (1)
00093 /* @brief MCM availability on the SoC. */
00094 #define FSL_FEATURE_SOC_MCM_COUNT (1)
00095 /* @brief SYSMPU availability on the SoC. */
00096 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
00097 /* @brief OSC availability on the SoC. */
00098 #define FSL_FEATURE_SOC_OSC_COUNT (1)
00099 /* @brief PDB availability on the SoC. */
00100 #define FSL_FEATURE_SOC_PDB_COUNT (1)
00101 /* @brief PIT availability on the SoC. */
00102 #define FSL_FEATURE_SOC_PIT_COUNT (1)
00103 /* @brief PMC availability on the SoC. */
00104 #define FSL_FEATURE_SOC_PMC_COUNT (1)
00105 /* @brief PORT availability on the SoC. */
00106 #define FSL_FEATURE_SOC_PORT_COUNT (5)
00107 /* @brief RCM availability on the SoC. */
00108 #define FSL_FEATURE_SOC_RCM_COUNT (1)
00109 /* @brief RFSYS availability on the SoC. */
00110 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
00111 /* @brief RFVBAT availability on the SoC. */
00112 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
00113 /* @brief RNG availability on the SoC. */
00114 #define FSL_FEATURE_SOC_RNG_COUNT (1)
00115 /* @brief RTC availability on the SoC. */
00116 #define FSL_FEATURE_SOC_RTC_COUNT (1)
00117 /* @brief SDHC availability on the SoC. */
00118 #define FSL_FEATURE_SOC_SDHC_COUNT (1)
00119 /* @brief SDRAM availability on the SoC. */
00120 #define FSL_FEATURE_SOC_SDRAM_COUNT (1)
00121 /* @brief SIM availability on the SoC. */
00122 #define FSL_FEATURE_SOC_SIM_COUNT (1)
00123 /* @brief SMC availability on the SoC. */
00124 #define FSL_FEATURE_SOC_SMC_COUNT (1)
00125 /* @brief TPM availability on the SoC. */
00126 #define FSL_FEATURE_SOC_TPM_COUNT (2)
00127 /* @brief TSI availability on the SoC. */
00128 #define FSL_FEATURE_SOC_TSI_COUNT (1)
00129 /* @brief UART availability on the SoC. */
00130 #define FSL_FEATURE_SOC_UART_COUNT (5)
00131 /* @brief USB availability on the SoC. */
00132 #define FSL_FEATURE_SOC_USB_COUNT (1)
00133 /* @brief USBDCD availability on the SoC. */
00134 #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
00135 /* @brief USBHS availability on the SoC. */
00136 #define FSL_FEATURE_SOC_USBHS_COUNT (1)
00137 /* @brief USBHSDCD availability on the SoC. */
00138 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1)
00139 /* @brief USBPHY availability on the SoC. */
00140 #define FSL_FEATURE_SOC_USBPHY_COUNT (1)
00141 /* @brief VREF availability on the SoC. */
00142 #define FSL_FEATURE_SOC_VREF_COUNT (1)
00143 /* @brief WDOG availability on the SoC. */
00144 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
00145 
00146 /* ADC16 module features */
00147 
00148 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
00149 #define FSL_FEATURE_ADC16_HAS_PGA (0)
00150 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
00151 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
00152 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
00153 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
00154 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
00155 #define FSL_FEATURE_ADC16_HAS_DMA (1)
00156 /* @brief Has differential mode (bitfield SC1x[DIFF]). */
00157 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
00158 /* @brief Has FIFO (bit SC4[AFDEP]). */
00159 #define FSL_FEATURE_ADC16_HAS_FIFO (0)
00160 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
00161 #define FSL_FEATURE_ADC16_FIFO_SIZE (0)
00162 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
00163 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
00164 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
00165 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
00166 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
00167 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
00168 /* @brief Has HW averaging (bit SC3[AVGE]). */
00169 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
00170 /* @brief Has offset correction (register OFS). */
00171 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
00172 /* @brief Maximum ADC resolution. */
00173 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
00174 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
00175 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
00176 
00177 /* FLEXCAN module features */
00178 
00179 /* @brief Message buffer size */
00180 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16)
00181 /* @brief Has doze mode support (register bit field MCR[DOZE]). */
00182 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
00183 /* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
00184 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
00185 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
00186 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
00187 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
00188 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
00189 /* @brief Instance has extended bit timing register (register CBT). */
00190 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0)
00191 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
00192 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
00193 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
00194 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0)
00195 /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
00196 #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
00197 /* @brief Has bitfield name BUF31TO0M. */
00198 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0)
00199 /* @brief Number of interrupt vectors. */
00200 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
00201 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
00202 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
00203 
00204 /* CMP module features */
00205 
00206 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
00207 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
00208 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */
00209 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
00210 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
00211 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
00212 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
00213 #define FSL_FEATURE_CMP_HAS_DMA (1)
00214 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
00215 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
00216 /* @brief Has DAC Test function in CMP (register DACTEST). */
00217 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
00218 
00219 /* CRC module features */
00220 
00221 /* @brief Has data register with name CRC */
00222 #define FSL_FEATURE_CRC_HAS_CRC_REG (0)
00223 
00224 /* DAC module features */
00225 
00226 /* @brief Define the size of hardware buffer */
00227 #define FSL_FEATURE_DAC_BUFFER_SIZE (16)
00228 /* @brief Define whether the buffer supports watermark event detection or not. */
00229 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
00230 /* @brief Define whether the buffer supports watermark selection detection or not. */
00231 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
00232 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
00233 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
00234 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
00235 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
00236 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
00237 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
00238 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
00239 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
00240 /* @brief Define whether FIFO buffer mode is available or not. */
00241 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
00242 /* @brief Define whether swing buffer mode is available or not.. */
00243 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
00244 
00245 /* EDMA module features */
00246 
00247 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
00248 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
00249 /* @brief Total number of DMA channels on all modules. */
00250 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 32)
00251 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
00252 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2)
00253 /* @brief Has DMA_Error interrupt vector. */
00254 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
00255 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
00256 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
00257 
00258 /* DMAMUX module features */
00259 
00260 /* @brief Number of DMA channels (related to number of register CHCFGn). */
00261 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
00262 /* @brief Total number of DMA channels on all modules. */
00263 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32)
00264 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
00265 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
00266 
00267 /* EWM module features */
00268 
00269 /* @brief Has clock select (register CLKCTRL). */
00270 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT  (0)
00271 /* @brief Has clock prescaler (register CLKPRESCALER). */
00272 #define FSL_FEATURE_EWM_HAS_PRESCALER  (0)
00273 
00274 /* FLEXBUS module features */
00275 
00276 /* No feature definitions */
00277 
00278 /* FLASH module features */
00279 
00280 /* @brief Is of type FTFA. */
00281 #define FSL_FEATURE_FLASH_IS_FTFA (0)
00282 /* @brief Is of type FTFE. */
00283 #define FSL_FEATURE_FLASH_IS_FTFE (1)
00284 /* @brief Is of type FTFL. */
00285 #define FSL_FEATURE_FLASH_IS_FTFL (0)
00286 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
00287 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
00288 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
00289 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
00290 /* @brief Has EEPROM region protection (register FEPROT). */
00291 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
00292 /* @brief Has data flash region protection (register FDPROT). */
00293 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
00294 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
00295 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
00296 /* @brief Has flash cache control in FMC module. */
00297 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
00298 /* @brief Has flash cache control in MCM module. */
00299 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
00300 /* @brief Has flash cache control in MSCM module. */
00301 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
00302 /* @brief Has prefetch speculation control in flash, such as kv5x. */
00303 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
00304 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
00305 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
00306 /* @brief P-Flash start address. */
00307 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
00308 /* @brief P-Flash block count. */
00309 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (4)
00310 /* @brief P-Flash block size. */
00311 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
00312 /* @brief P-Flash sector size. */
00313 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
00314 /* @brief P-Flash write unit size. */
00315 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
00316 /* @brief P-Flash data path width. */
00317 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
00318 /* @brief P-Flash block swap feature. */
00319 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
00320 /* @brief P-Flash protection region count. */
00321 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
00322 /* @brief Has FlexNVM memory. */
00323 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
00324 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
00325 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
00326 /* @brief FlexNVM block count. */
00327 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
00328 /* @brief FlexNVM block size. */
00329 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
00330 /* @brief FlexNVM sector size. */
00331 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
00332 /* @brief FlexNVM write unit size. */
00333 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
00334 /* @brief FlexNVM data path width. */
00335 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
00336 /* @brief Has FlexRAM memory. */
00337 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
00338 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
00339 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
00340 /* @brief FlexRAM size. */
00341 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
00342 /* @brief Has 0x00 Read 1s Block command. */
00343 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
00344 /* @brief Has 0x01 Read 1s Section command. */
00345 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
00346 /* @brief Has 0x02 Program Check command. */
00347 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
00348 /* @brief Has 0x03 Read Resource command. */
00349 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
00350 /* @brief Has 0x06 Program Longword command. */
00351 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
00352 /* @brief Has 0x07 Program Phrase command. */
00353 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
00354 /* @brief Has 0x08 Erase Flash Block command. */
00355 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
00356 /* @brief Has 0x09 Erase Flash Sector command. */
00357 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
00358 /* @brief Has 0x0B Program Section command. */
00359 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
00360 /* @brief Has 0x40 Read 1s All Blocks command. */
00361 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
00362 /* @brief Has 0x41 Read Once command. */
00363 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
00364 /* @brief Has 0x43 Program Once command. */
00365 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
00366 /* @brief Has 0x44 Erase All Blocks command. */
00367 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
00368 /* @brief Has 0x45 Verify Backdoor Access Key command. */
00369 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
00370 /* @brief Has 0x46 Swap Control command. */
00371 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
00372 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
00373 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
00374 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
00375 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
00376 /* @brief Has 0x4B Erase All Execute-only Segments command. */
00377 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
00378 /* @brief Has 0x80 Program Partition command. */
00379 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
00380 /* @brief Has 0x81 Set FlexRAM Function command. */
00381 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
00382 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
00383 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
00384 /* @brief P-Flash Erase sector command address alignment. */
00385 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
00386 /* @brief P-Flash Rrogram/Verify section command address alignment. */
00387 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
00388 /* @brief P-Flash Read resource command address alignment. */
00389 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
00390 /* @brief P-Flash Program check command address alignment. */
00391 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
00392 /* @brief P-Flash Program check command address alignment. */
00393 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
00394 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
00395 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
00396 /* @brief FlexNVM Erase sector command address alignment. */
00397 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
00398 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
00399 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
00400 /* @brief FlexNVM Read resource command address alignment. */
00401 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
00402 /* @brief FlexNVM Program check command address alignment. */
00403 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
00404 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00405 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
00406 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00407 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
00408 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00409 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
00410 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00411 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
00412 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00413 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
00414 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00415 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
00416 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00417 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
00418 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00419 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
00420 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00421 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
00422 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00423 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
00424 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00425 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
00426 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00427 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
00428 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00429 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
00430 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00431 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
00432 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00433 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
00434 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
00435 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
00436 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00437 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
00438 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00439 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
00440 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00441 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
00442 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00443 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
00444 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00445 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
00446 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00447 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
00448 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00449 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
00450 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00451 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
00452 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00453 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
00454 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00455 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
00456 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00457 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
00458 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00459 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
00460 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00461 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
00462 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00463 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
00464 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00465 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
00466 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
00467 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
00468 
00469 /* FTM module features */
00470 
00471 /* @brief Number of channels. */
00472 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
00473     ((x) == FTM0 ? (8) : \
00474     ((x) == FTM1 ? (2) : \
00475     ((x) == FTM2 ? (2) : \
00476     ((x) == FTM3 ? (8) : (-1)))))
00477 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
00478 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
00479 /* @brief Has extended deadtime value. */
00480 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0)
00481 /* @brief Enable pwm output for the module. */
00482 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
00483 /* @brief Has half-cycle reload for the module. */
00484 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0)
00485 /* @brief Has reload interrupt. */
00486 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0)
00487 /* @brief Has reload initialization trigger. */
00488 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
00489 /* @brief Has DMA support, bitfield CnSC[DMA]. */
00490 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1)
00491 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */
00492 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0)
00493 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */
00494 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0)
00495 /* @brief Has no QDCTRL. */
00496 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0)
00497 
00498 /* GPIO module features */
00499 
00500 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
00501 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
00502 /* @brief Has port input disable register (PIDR). */
00503 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
00504 /* @brief Has dedicated interrupt vector. */
00505 #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
00506 
00507 /* I2C module features */
00508 
00509 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
00510 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
00511 /* @brief Maximum supported baud rate in kilobit per second. */
00512 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
00513 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
00514 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
00515 /* @brief Has DMA support (register bit C1[DMAEN]). */
00516 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
00517 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
00518 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
00519 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
00520 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
00521 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
00522 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
00523 /* @brief Maximum width of the glitch filter in number of bus clocks. */
00524 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
00525 /* @brief Has control of the drive capability of the I2C pins. */
00526 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
00527 /* @brief Has double buffering support (register S2). */
00528 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
00529 /* @brief Has double buffer enable. */
00530 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
00531 
00532 /* SAI module features */
00533 
00534 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
00535 #define FSL_FEATURE_SAI_FIFO_COUNT (8)
00536 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
00537 #define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
00538 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
00539 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
00540 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
00541 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
00542 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
00543 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
00544 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
00545 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
00546 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
00547 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
00548 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
00549 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
00550 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
00551 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
00552 /* @brief Ihe interrupt source number */
00553 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
00554 /* @brief Has register of MCR. */
00555 #define FSL_FEATURE_SAI_HAS_MCR (1)
00556 /* @brief Has register of MDR */
00557 #define FSL_FEATURE_SAI_HAS_MDR (1)
00558 
00559 /* LLWU module features */
00560 
00561 #if defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VMI18)
00562     /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
00563     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32)
00564     /* @brief Has pins 8-15 connected to LLWU device. */
00565     #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
00566     /* @brief Maximum number of internal modules connected to LLWU device. */
00567     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
00568     /* @brief Number of digital filters. */
00569     #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
00570     /* @brief Has MF register. */
00571     #define FSL_FEATURE_LLWU_HAS_MF (1)
00572     /* @brief Has PF register. */
00573     #define FSL_FEATURE_LLWU_HAS_PF (1)
00574     /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
00575     #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
00576     /* @brief Has no internal module wakeup flag register. */
00577     #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
00578     /* @brief Has external pin 0 connected to LLWU device. */
00579     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
00580     /* @brief Index of port of external pin. */
00581     #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
00582     /* @brief Number of external pin port on specified port. */
00583     #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
00584     /* @brief Has external pin 1 connected to LLWU device. */
00585     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
00586     /* @brief Index of port of external pin. */
00587     #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
00588     /* @brief Number of external pin port on specified port. */
00589     #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
00590     /* @brief Has external pin 2 connected to LLWU device. */
00591     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
00592     /* @brief Index of port of external pin. */
00593     #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
00594     /* @brief Number of external pin port on specified port. */
00595     #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
00596     /* @brief Has external pin 3 connected to LLWU device. */
00597     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
00598     /* @brief Index of port of external pin. */
00599     #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
00600     /* @brief Number of external pin port on specified port. */
00601     #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
00602     /* @brief Has external pin 4 connected to LLWU device. */
00603     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
00604     /* @brief Index of port of external pin. */
00605     #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
00606     /* @brief Number of external pin port on specified port. */
00607     #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
00608     /* @brief Has external pin 5 connected to LLWU device. */
00609     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
00610     /* @brief Index of port of external pin. */
00611     #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
00612     /* @brief Number of external pin port on specified port. */
00613     #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
00614     /* @brief Has external pin 6 connected to LLWU device. */
00615     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
00616     /* @brief Index of port of external pin. */
00617     #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
00618     /* @brief Number of external pin port on specified port. */
00619     #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
00620     /* @brief Has external pin 7 connected to LLWU device. */
00621     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
00622     /* @brief Index of port of external pin. */
00623     #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
00624     /* @brief Number of external pin port on specified port. */
00625     #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
00626     /* @brief Has external pin 8 connected to LLWU device. */
00627     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
00628     /* @brief Index of port of external pin. */
00629     #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
00630     /* @brief Number of external pin port on specified port. */
00631     #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
00632     /* @brief Has external pin 9 connected to LLWU device. */
00633     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
00634     /* @brief Index of port of external pin. */
00635     #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
00636     /* @brief Number of external pin port on specified port. */
00637     #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
00638     /* @brief Has external pin 10 connected to LLWU device. */
00639     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
00640     /* @brief Index of port of external pin. */
00641     #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
00642     /* @brief Number of external pin port on specified port. */
00643     #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
00644     /* @brief Has external pin 11 connected to LLWU device. */
00645     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
00646     /* @brief Index of port of external pin. */
00647     #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
00648     /* @brief Number of external pin port on specified port. */
00649     #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
00650     /* @brief Has external pin 12 connected to LLWU device. */
00651     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
00652     /* @brief Index of port of external pin. */
00653     #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
00654     /* @brief Number of external pin port on specified port. */
00655     #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
00656     /* @brief Has external pin 13 connected to LLWU device. */
00657     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
00658     /* @brief Index of port of external pin. */
00659     #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
00660     /* @brief Number of external pin port on specified port. */
00661     #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
00662     /* @brief Has external pin 14 connected to LLWU device. */
00663     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
00664     /* @brief Index of port of external pin. */
00665     #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
00666     /* @brief Number of external pin port on specified port. */
00667     #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
00668     /* @brief Has external pin 15 connected to LLWU device. */
00669     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
00670     /* @brief Index of port of external pin. */
00671     #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
00672     /* @brief Number of external pin port on specified port. */
00673     #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
00674     /* @brief Has external pin 16 connected to LLWU device. */
00675     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
00676     /* @brief Index of port of external pin. */
00677     #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX)
00678     /* @brief Number of external pin port on specified port. */
00679     #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6)
00680     /* @brief Has external pin 17 connected to LLWU device. */
00681     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
00682     /* @brief Index of port of external pin. */
00683     #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX)
00684     /* @brief Number of external pin port on specified port. */
00685     #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9)
00686     /* @brief Has external pin 18 connected to LLWU device. */
00687     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
00688     /* @brief Index of port of external pin. */
00689     #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX)
00690     /* @brief Number of external pin port on specified port. */
00691     #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10)
00692     /* @brief Has external pin 19 connected to LLWU device. */
00693     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1)
00694     /* @brief Index of port of external pin. */
00695     #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX)
00696     /* @brief Number of external pin port on specified port. */
00697     #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17)
00698     /* @brief Has external pin 20 connected to LLWU device. */
00699     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1)
00700     /* @brief Index of port of external pin. */
00701     #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX)
00702     /* @brief Number of external pin port on specified port. */
00703     #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18)
00704     /* @brief Has external pin 21 connected to LLWU device. */
00705     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1)
00706     /* @brief Index of port of external pin. */
00707     #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX)
00708     /* @brief Number of external pin port on specified port. */
00709     #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25)
00710     /* @brief Has external pin 22 connected to LLWU device. */
00711     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
00712     /* @brief Index of port of external pin. */
00713     #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX)
00714     /* @brief Number of external pin port on specified port. */
00715     #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10)
00716     /* @brief Has external pin 23 connected to LLWU device. */
00717     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
00718     /* @brief Index of port of external pin. */
00719     #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX)
00720     /* @brief Number of external pin port on specified port. */
00721     #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11)
00722     /* @brief Has external pin 24 connected to LLWU device. */
00723     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
00724     /* @brief Index of port of external pin. */
00725     #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX)
00726     /* @brief Number of external pin port on specified port. */
00727     #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8)
00728     /* @brief Has external pin 25 connected to LLWU device. */
00729     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
00730     /* @brief Index of port of external pin. */
00731     #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX)
00732     /* @brief Number of external pin port on specified port. */
00733     #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11)
00734     /* @brief Has external pin 26 connected to LLWU device. */
00735     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
00736     /* @brief Index of port of external pin. */
00737     #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
00738     /* @brief Number of external pin port on specified port. */
00739     #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
00740     /* @brief Has external pin 27 connected to LLWU device. */
00741     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
00742     /* @brief Index of port of external pin. */
00743     #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
00744     /* @brief Number of external pin port on specified port. */
00745     #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
00746     /* @brief Has external pin 28 connected to LLWU device. */
00747     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
00748     /* @brief Index of port of external pin. */
00749     #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
00750     /* @brief Number of external pin port on specified port. */
00751     #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
00752     /* @brief Has external pin 29 connected to LLWU device. */
00753     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (1)
00754     /* @brief Index of port of external pin. */
00755     #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
00756     /* @brief Number of external pin port on specified port. */
00757     #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
00758     /* @brief Has external pin 30 connected to LLWU device. */
00759     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (1)
00760     /* @brief Index of port of external pin. */
00761     #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
00762     /* @brief Number of external pin port on specified port. */
00763     #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
00764     /* @brief Has external pin 31 connected to LLWU device. */
00765     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (1)
00766     /* @brief Index of port of external pin. */
00767     #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
00768     /* @brief Number of external pin port on specified port. */
00769     #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
00770     /* @brief Has internal module 0 connected to LLWU device. */
00771     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
00772     /* @brief Has internal module 1 connected to LLWU device. */
00773     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
00774     /* @brief Has internal module 2 connected to LLWU device. */
00775     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
00776     /* @brief Has internal module 3 connected to LLWU device. */
00777     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
00778     /* @brief Has internal module 4 connected to LLWU device. */
00779     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
00780     /* @brief Has internal module 5 connected to LLWU device. */
00781     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
00782     /* @brief Has internal module 6 connected to LLWU device. */
00783     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
00784     /* @brief Has internal module 7 connected to LLWU device. */
00785     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
00786     /* @brief Has Version ID Register (LLWU_VERID). */
00787     #define FSL_FEATURE_LLWU_HAS_VERID (0)
00788     /* @brief Has Parameter Register (LLWU_PARAM). */
00789     #define FSL_FEATURE_LLWU_HAS_PARAM (0)
00790     /* @brief Width of registers of the LLWU. */
00791     #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
00792     /* @brief Has DMA Enable register (LLWU_DE). */
00793     #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
00794 #elif defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18)
00795     /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
00796     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32)
00797     /* @brief Has pins 8-15 connected to LLWU device. */
00798     #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
00799     /* @brief Maximum number of internal modules connected to LLWU device. */
00800     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
00801     /* @brief Number of digital filters. */
00802     #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
00803     /* @brief Has MF register. */
00804     #define FSL_FEATURE_LLWU_HAS_MF (1)
00805     /* @brief Has PF register. */
00806     #define FSL_FEATURE_LLWU_HAS_PF (1)
00807     /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
00808     #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
00809     /* @brief Has no internal module wakeup flag register. */
00810     #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
00811     /* @brief Has external pin 0 connected to LLWU device. */
00812     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
00813     /* @brief Index of port of external pin. */
00814     #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
00815     /* @brief Number of external pin port on specified port. */
00816     #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
00817     /* @brief Has external pin 1 connected to LLWU device. */
00818     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
00819     /* @brief Index of port of external pin. */
00820     #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
00821     /* @brief Number of external pin port on specified port. */
00822     #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
00823     /* @brief Has external pin 2 connected to LLWU device. */
00824     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
00825     /* @brief Index of port of external pin. */
00826     #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
00827     /* @brief Number of external pin port on specified port. */
00828     #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
00829     /* @brief Has external pin 3 connected to LLWU device. */
00830     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
00831     /* @brief Index of port of external pin. */
00832     #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
00833     /* @brief Number of external pin port on specified port. */
00834     #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
00835     /* @brief Has external pin 4 connected to LLWU device. */
00836     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
00837     /* @brief Index of port of external pin. */
00838     #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
00839     /* @brief Number of external pin port on specified port. */
00840     #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
00841     /* @brief Has external pin 5 connected to LLWU device. */
00842     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
00843     /* @brief Index of port of external pin. */
00844     #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
00845     /* @brief Number of external pin port on specified port. */
00846     #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
00847     /* @brief Has external pin 6 connected to LLWU device. */
00848     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
00849     /* @brief Index of port of external pin. */
00850     #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
00851     /* @brief Number of external pin port on specified port. */
00852     #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
00853     /* @brief Has external pin 7 connected to LLWU device. */
00854     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
00855     /* @brief Index of port of external pin. */
00856     #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
00857     /* @brief Number of external pin port on specified port. */
00858     #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
00859     /* @brief Has external pin 8 connected to LLWU device. */
00860     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
00861     /* @brief Index of port of external pin. */
00862     #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
00863     /* @brief Number of external pin port on specified port. */
00864     #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
00865     /* @brief Has external pin 9 connected to LLWU device. */
00866     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
00867     /* @brief Index of port of external pin. */
00868     #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
00869     /* @brief Number of external pin port on specified port. */
00870     #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
00871     /* @brief Has external pin 10 connected to LLWU device. */
00872     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
00873     /* @brief Index of port of external pin. */
00874     #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
00875     /* @brief Number of external pin port on specified port. */
00876     #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
00877     /* @brief Has external pin 11 connected to LLWU device. */
00878     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
00879     /* @brief Index of port of external pin. */
00880     #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
00881     /* @brief Number of external pin port on specified port. */
00882     #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
00883     /* @brief Has external pin 12 connected to LLWU device. */
00884     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
00885     /* @brief Index of port of external pin. */
00886     #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
00887     /* @brief Number of external pin port on specified port. */
00888     #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
00889     /* @brief Has external pin 13 connected to LLWU device. */
00890     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
00891     /* @brief Index of port of external pin. */
00892     #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
00893     /* @brief Number of external pin port on specified port. */
00894     #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
00895     /* @brief Has external pin 14 connected to LLWU device. */
00896     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
00897     /* @brief Index of port of external pin. */
00898     #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
00899     /* @brief Number of external pin port on specified port. */
00900     #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
00901     /* @brief Has external pin 15 connected to LLWU device. */
00902     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
00903     /* @brief Index of port of external pin. */
00904     #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
00905     /* @brief Number of external pin port on specified port. */
00906     #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
00907     /* @brief Has external pin 16 connected to LLWU device. */
00908     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
00909     /* @brief Index of port of external pin. */
00910     #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX)
00911     /* @brief Number of external pin port on specified port. */
00912     #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6)
00913     /* @brief Has external pin 17 connected to LLWU device. */
00914     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
00915     /* @brief Index of port of external pin. */
00916     #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX)
00917     /* @brief Number of external pin port on specified port. */
00918     #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9)
00919     /* @brief Has external pin 18 connected to LLWU device. */
00920     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
00921     /* @brief Index of port of external pin. */
00922     #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX)
00923     /* @brief Number of external pin port on specified port. */
00924     #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10)
00925     /* @brief Has external pin 19 connected to LLWU device. */
00926     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
00927     /* @brief Index of port of external pin. */
00928     #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
00929     /* @brief Number of external pin port on specified port. */
00930     #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
00931     /* @brief Has external pin 20 connected to LLWU device. */
00932     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
00933     /* @brief Index of port of external pin. */
00934     #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
00935     /* @brief Number of external pin port on specified port. */
00936     #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
00937     /* @brief Has external pin 21 connected to LLWU device. */
00938     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1)
00939     /* @brief Index of port of external pin. */
00940     #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX)
00941     /* @brief Number of external pin port on specified port. */
00942     #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25)
00943     /* @brief Has external pin 22 connected to LLWU device. */
00944     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
00945     /* @brief Index of port of external pin. */
00946     #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX)
00947     /* @brief Number of external pin port on specified port. */
00948     #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10)
00949     /* @brief Has external pin 23 connected to LLWU device. */
00950     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
00951     /* @brief Index of port of external pin. */
00952     #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX)
00953     /* @brief Number of external pin port on specified port. */
00954     #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11)
00955     /* @brief Has external pin 24 connected to LLWU device. */
00956     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
00957     /* @brief Index of port of external pin. */
00958     #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX)
00959     /* @brief Number of external pin port on specified port. */
00960     #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8)
00961     /* @brief Has external pin 25 connected to LLWU device. */
00962     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
00963     /* @brief Index of port of external pin. */
00964     #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX)
00965     /* @brief Number of external pin port on specified port. */
00966     #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11)
00967     /* @brief Has external pin 26 connected to LLWU device. */
00968     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
00969     /* @brief Index of port of external pin. */
00970     #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
00971     /* @brief Number of external pin port on specified port. */
00972     #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
00973     /* @brief Has external pin 27 connected to LLWU device. */
00974     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
00975     /* @brief Index of port of external pin. */
00976     #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
00977     /* @brief Number of external pin port on specified port. */
00978     #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
00979     /* @brief Has external pin 28 connected to LLWU device. */
00980     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
00981     /* @brief Index of port of external pin. */
00982     #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
00983     /* @brief Number of external pin port on specified port. */
00984     #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
00985     /* @brief Has external pin 29 connected to LLWU device. */
00986     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (1)
00987     /* @brief Index of port of external pin. */
00988     #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
00989     /* @brief Number of external pin port on specified port. */
00990     #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
00991     /* @brief Has external pin 30 connected to LLWU device. */
00992     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (1)
00993     /* @brief Index of port of external pin. */
00994     #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
00995     /* @brief Number of external pin port on specified port. */
00996     #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
00997     /* @brief Has external pin 31 connected to LLWU device. */
00998     #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (1)
00999     /* @brief Index of port of external pin. */
01000     #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
01001     /* @brief Number of external pin port on specified port. */
01002     #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
01003     /* @brief Has internal module 0 connected to LLWU device. */
01004     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
01005     /* @brief Has internal module 1 connected to LLWU device. */
01006     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
01007     /* @brief Has internal module 2 connected to LLWU device. */
01008     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
01009     /* @brief Has internal module 3 connected to LLWU device. */
01010     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
01011     /* @brief Has internal module 4 connected to LLWU device. */
01012     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
01013     /* @brief Has internal module 5 connected to LLWU device. */
01014     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
01015     /* @brief Has internal module 6 connected to LLWU device. */
01016     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
01017     /* @brief Has internal module 7 connected to LLWU device. */
01018     #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
01019     /* @brief Has Version ID Register (LLWU_VERID). */
01020     #define FSL_FEATURE_LLWU_HAS_VERID (0)
01021     /* @brief Has Parameter Register (LLWU_PARAM). */
01022     #define FSL_FEATURE_LLWU_HAS_PARAM (0)
01023     /* @brief Width of registers of the LLWU. */
01024     #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
01025     /* @brief Has DMA Enable register (LLWU_DE). */
01026     #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
01027 #endif /* defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VMI18) */
01028 
01029 /* LMEM module features */
01030 
01031 /* @brief Has process identifier support. */
01032 #define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0)
01033 /* @brief Has L1 cache. */
01034 #define FSL_FEATURE_HAS_L1CACHE (1)
01035 /* @brief L1 ICACHE line size in byte. */
01036 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (16)
01037 /* @brief L1 DCACHE line size in byte. */
01038 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (16)
01039 
01040 /* LPTMR module features */
01041 
01042 /* @brief Has shared interrupt handler with another LPTMR module. */
01043 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
01044 /* @brief Whether LPTMR counter is 32 bits width. */
01045 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
01046 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
01047 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
01048 
01049 /* LPUART module features */
01050 
01051 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */
01052 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0)
01053 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
01054 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
01055 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
01056 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
01057 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
01058 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
01059 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
01060 #define FSL_FEATURE_LPUART_HAS_FIFO (0)
01061 /* @brief Has 32-bit register MODIR */
01062 #define FSL_FEATURE_LPUART_HAS_MODIR (1)
01063 /* @brief Hardware flow control (RTS, CTS) is supported. */
01064 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
01065 /* @brief Infrared (modulation) is supported. */
01066 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
01067 /* @brief 2 bits long stop bit is available. */
01068 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
01069 /* @brief If 10-bit mode is supported. */
01070 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
01071 /* @brief If 7-bit mode is supported. */
01072 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
01073 /* @brief Baud rate fine adjustment is available. */
01074 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
01075 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
01076 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
01077 /* @brief Baud rate oversampling is available. */
01078 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
01079 /* @brief Baud rate oversampling is available. */
01080 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
01081 /* @brief Peripheral type. */
01082 #define FSL_FEATURE_LPUART_IS_SCI (1)
01083 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
01084 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0)
01085 /* @brief Maximal data width without parity bit. */
01086 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
01087 /* @brief Maximal data width with parity bit. */
01088 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
01089 /* @brief Supports two match addresses to filter incoming frames. */
01090 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
01091 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
01092 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
01093 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
01094 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
01095 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
01096 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
01097 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
01098 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
01099 /* @brief Has improved smart card (ISO7816 protocol) support. */
01100 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
01101 /* @brief Has local operation network (CEA709.1-B protocol) support. */
01102 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
01103 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
01104 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
01105 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
01106 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
01107 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
01108 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
01109 /* @brief Has separate DMA RX and TX requests. */
01110 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
01111 /* @brief Has separate RX and TX interrupts. */
01112 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
01113 /* @brief Has LPAURT_PARAM. */
01114 #define FSL_FEATURE_LPUART_HAS_PARAM (0)
01115 /* @brief Has LPUART_VERID. */
01116 #define FSL_FEATURE_LPUART_HAS_VERID (0)
01117 /* @brief Has LPUART_GLOBAL. */
01118 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
01119 /* @brief Has LPUART_PINCFG. */
01120 #define FSL_FEATURE_LPUART_HAS_PINCFG (0)
01121 
01122 /* MCG module features */
01123 
01124 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
01125 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
01126 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
01127 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (7)
01128 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
01129 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16)
01130 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */
01131 #define FSL_FEATURE_MCG_PLL_REF_MIN (8000000)
01132 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */
01133 #define FSL_FEATURE_MCG_PLL_REF_MAX (16000000)
01134 /* @brief The PLL clock is divided by 2 before VCO divider. */
01135 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (1)
01136 /* @brief FRDIV supports 1280. */
01137 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
01138 /* @brief FRDIV supports 1536. */
01139 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
01140 /* @brief MCGFFCLK divider. */
01141 #define FSL_FEATURE_MCG_FFCLK_DIV (1)
01142 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
01143 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
01144 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
01145 #define FSL_FEATURE_MCG_HAS_RTC_32K (1)
01146 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
01147 #define FSL_FEATURE_MCG_HAS_PLL1 (0)
01148 /* @brief Has 48MHz internal oscillator. */
01149 #define FSL_FEATURE_MCG_HAS_IRC_48M (1)
01150 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
01151 #define FSL_FEATURE_MCG_HAS_OSC1 (0)
01152 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
01153 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
01154 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
01155 #define FSL_FEATURE_MCG_HAS_LOLRE (1)
01156 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
01157 #define FSL_FEATURE_MCG_USE_OSCSEL (1)
01158 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
01159 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
01160 /* @brief TBD */
01161 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
01162 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
01163 #define FSL_FEATURE_MCG_HAS_PLL (1)
01164 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
01165 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
01166 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
01167 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
01168 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
01169 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
01170 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
01171 #define FSL_FEATURE_MCG_HAS_FLL (1)
01172 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
01173 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1)
01174 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
01175 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
01176 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
01177 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
01178 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
01179 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1)
01180 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
01181 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
01182 /* @brief Has external clock monitor (register bit C6[CME]). */
01183 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
01184 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
01185 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
01186 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
01187 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
01188 /* @brief Has PEI mode or PBI mode. */
01189 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
01190 /* @brief Reset clock mode is BLPI. */
01191 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
01192 
01193 /* interrupt module features */
01194 
01195 /* @brief Lowest interrupt request number. */
01196 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
01197 /* @brief Highest interrupt request number. */
01198 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (99)
01199 
01200 /* OSC module features */
01201 
01202 /* @brief Has OSC1 external oscillator. */
01203 #define FSL_FEATURE_OSC_HAS_OSC1 (0)
01204 /* @brief Has OSC0 external oscillator. */
01205 #define FSL_FEATURE_OSC_HAS_OSC0 (0)
01206 /* @brief Has OSC external oscillator (without index). */
01207 #define FSL_FEATURE_OSC_HAS_OSC (1)
01208 /* @brief Number of OSC external oscillators. */
01209 #define FSL_FEATURE_OSC_OSC_COUNT (1)
01210 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
01211 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1)
01212 
01213 /* PDB module features */
01214 
01215 /* @brief Define the count of supporting ADC pre-trigger for each channel. */
01216 #define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
01217 /* @brief Has DAC support. */
01218 #define FSL_FEATURE_PDB_HAS_DAC (1)
01219 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
01220 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
01221 
01222 /* PIT module features */
01223 
01224 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
01225 #define FSL_FEATURE_PIT_TIMER_COUNT (4)
01226 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
01227 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
01228 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
01229 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
01230 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
01231 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
01232 /* @brief Has timer enable control. */
01233 #define FSL_FEATURE_PIT_HAS_MDIS (1)
01234 
01235 /* PMC module features */
01236 
01237 /* @brief Has Bandgap Enable In VLPx Operation support. */
01238 #define FSL_FEATURE_PMC_HAS_BGEN (1)
01239 /* @brief Has Bandgap Buffer Enable. */
01240 #define FSL_FEATURE_PMC_HAS_BGBE (1)
01241 /* @brief Has Bandgap Buffer Drive Select. */
01242 #define FSL_FEATURE_PMC_HAS_BGBDS (0)
01243 /* @brief Has Low-Voltage Detect Voltage Select support. */
01244 #define FSL_FEATURE_PMC_HAS_LVDV (1)
01245 /* @brief Has Low-Voltage Warning Voltage Select support. */
01246 #define FSL_FEATURE_PMC_HAS_LVWV (1)
01247 /* @brief Has LPO. */
01248 #define FSL_FEATURE_PMC_HAS_LPO (0)
01249 /* @brief Has VLPx option PMC_REGSC[VLPO]. */
01250 #define FSL_FEATURE_PMC_HAS_VLPO (0)
01251 /* @brief Has acknowledge isolation support. */
01252 #define FSL_FEATURE_PMC_HAS_ACKISO (1)
01253 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
01254 #define FSL_FEATURE_PMC_HAS_REGFPM (0)
01255 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
01256 #define FSL_FEATURE_PMC_HAS_REGONS (1)
01257 /* @brief Has PMC_HVDSC1. */
01258 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
01259 /* @brief Has PMC_PARAM. */
01260 #define FSL_FEATURE_PMC_HAS_PARAM (0)
01261 /* @brief Has PMC_VERID. */
01262 #define FSL_FEATURE_PMC_HAS_VERID (0)
01263 
01264 /* PORT module features */
01265 
01266 /* @brief Has control lock (register bit PCR[LK]). */
01267 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
01268 /* @brief Has open drain control (register bit PCR[ODE]). */
01269 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
01270 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
01271 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
01272 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
01273 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
01274 /* @brief Has pull resistor selection available. */
01275 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
01276 /* @brief Has pull resistor enable (register bit PCR[PE]). */
01277 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
01278 /* @brief Has slew rate control (register bit PCR[SRE]). */
01279 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
01280 /* @brief Has passive filter (register bit field PCR[PFE]). */
01281 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
01282 /* @brief Has drive strength control (register bit PCR[DSE]). */
01283 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
01284 /* @brief Has separate drive strength register (HDRVE). */
01285 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
01286 /* @brief Has glitch filter (register IOFLT). */
01287 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
01288 /* @brief Defines width of PCR[MUX] field. */
01289 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
01290 /* @brief Has dedicated interrupt vector. */
01291 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
01292 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
01293 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
01294 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
01295 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
01296 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
01297 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
01298 
01299 /* RCM module features */
01300 
01301 /* @brief Has Loss-of-Lock Reset support. */
01302 #define FSL_FEATURE_RCM_HAS_LOL (1)
01303 /* @brief Has Loss-of-Clock Reset support. */
01304 #define FSL_FEATURE_RCM_HAS_LOC (1)
01305 /* @brief Has JTAG generated Reset support. */
01306 #define FSL_FEATURE_RCM_HAS_JTAG (1)
01307 /* @brief Has EzPort generated Reset support. */
01308 #define FSL_FEATURE_RCM_HAS_EZPORT (1)
01309 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
01310 #define FSL_FEATURE_RCM_HAS_EZPMS (1)
01311 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
01312 #define FSL_FEATURE_RCM_HAS_BOOTROM (0)
01313 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
01314 #define FSL_FEATURE_RCM_HAS_SSRS (1)
01315 /* @brief Has Version ID Register (RCM_VERID). */
01316 #define FSL_FEATURE_RCM_HAS_VERID (0)
01317 /* @brief Has Parameter Register (RCM_PARAM). */
01318 #define FSL_FEATURE_RCM_HAS_PARAM (0)
01319 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
01320 #define FSL_FEATURE_RCM_HAS_SRIE (0)
01321 /* @brief Width of registers of the RCM. */
01322 #define FSL_FEATURE_RCM_REG_WIDTH (8)
01323 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
01324 #define FSL_FEATURE_RCM_HAS_CORE1 (0)
01325 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
01326 #define FSL_FEATURE_RCM_HAS_MDM_AP (1)
01327 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
01328 #define FSL_FEATURE_RCM_HAS_WAKEUP (1)
01329 
01330 /* RTC module features */
01331 
01332 /* @brief Has wakeup pin. */
01333 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
01334 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
01335 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
01336 /* @brief Has low power features (registers MER, MCLR and MCHR). */
01337 #define FSL_FEATURE_RTC_HAS_MONOTONIC (1)
01338 /* @brief Has read/write access control (registers WAR and RAR). */
01339 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
01340 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
01341 #define FSL_FEATURE_RTC_HAS_SECURITY (1)
01342 /* @brief Has RTC_CLKIN available. */
01343 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
01344 /* @brief Has prescaler adjust for LPO. */
01345 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
01346 /* @brief Has Clock Pin Enable field. */
01347 #define FSL_FEATURE_RTC_HAS_CPE (0)
01348 /* @brief Has Timer Seconds Interrupt Configuration field. */
01349 #define FSL_FEATURE_RTC_HAS_TSIC (0)
01350 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
01351 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
01352 /* @brief Has Tamper Interrupt Register (register TIR). */
01353 #define FSL_FEATURE_RTC_HAS_TIR (0)
01354 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
01355 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
01356 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
01357 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
01358 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
01359 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
01360 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
01361 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
01362 /* @brief Has Tamper Detect Register (register TDR). */
01363 #define FSL_FEATURE_RTC_HAS_TDR (0)
01364 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
01365 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
01366 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
01367 #define FSL_FEATURE_RTC_HAS_TDR_STF (0)
01368 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
01369 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
01370 /* @brief Has Tamper Time Seconds Register (register TTSR). */
01371 #define FSL_FEATURE_RTC_HAS_TTSR (1)
01372 /* @brief Has Pin Configuration Register (register PCR). */
01373 #define FSL_FEATURE_RTC_HAS_PCR (0)
01374 
01375 /* SDHC module features */
01376 
01377 /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
01378 #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (0)
01379 /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
01380 #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
01381 /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
01382 #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
01383 
01384 /* SIM module features */
01385 
01386 /* @brief Has USB FS divider. */
01387 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
01388 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
01389 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
01390 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
01391 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
01392 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
01393 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
01394 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
01395 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
01396 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
01397 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
01398 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
01399 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
01400 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
01401 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
01402 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
01403 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (1)
01404 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
01405 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
01406 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
01407 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
01408 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
01409 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
01410 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
01411 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
01412 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
01413 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
01414 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
01415 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1)
01416 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
01417 #define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
01418 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
01419 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
01420 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
01421 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
01422 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
01423 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
01424 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
01425 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
01426 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
01427 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
01428 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
01429 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
01430 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
01431 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
01432 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
01433 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
01434 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
01435 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
01436 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
01437 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
01438 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
01439 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
01440 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
01441 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
01442 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
01443 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
01444 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
01445 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
01446 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
01447 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
01448 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
01449 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
01450 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
01451 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
01452 /* @brief Has FTM module(s) configuration. */
01453 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
01454 /* @brief Number of FTM modules. */
01455 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
01456 /* @brief Number of FTM triggers with selectable source. */
01457 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
01458 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
01459 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
01460 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
01461 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
01462 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
01463 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
01464 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
01465 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
01466 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
01467 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
01468 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
01469 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
01470 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
01471 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4)
01472 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
01473 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
01474 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
01475 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
01476 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
01477 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
01478 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
01479 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
01480 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
01481 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
01482 /* @brief Has TPM module(s) configuration. */
01483 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
01484 /* @brief The highest TPM module index. */
01485 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
01486 /* @brief Has TPM module with index 0. */
01487 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
01488 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
01489 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
01490 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
01491 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
01492 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
01493 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
01494 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
01495 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
01496 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
01497 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
01498 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
01499 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
01500 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
01501 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
01502 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
01503 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
01504 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
01505 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
01506 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
01507 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
01508 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
01509 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
01510 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
01511 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
01512 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
01513 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
01514 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
01515 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
01516 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
01517 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
01518 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
01519 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
01520 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
01521 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
01522 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
01523 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
01524 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
01525 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1)
01526 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
01527 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
01528 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
01529 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
01530 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
01531 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
01532 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
01533 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
01534 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
01535 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
01536 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
01537 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
01538 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
01539 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
01540 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
01541 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
01542 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
01543 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1)
01544 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
01545 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
01546 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
01547 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
01548 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
01549 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
01550 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
01551 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
01552 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
01553 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
01554 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
01555 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
01556 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
01557 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
01558 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
01559 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
01560 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
01561 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
01562 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
01563 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
01564 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
01565 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
01566 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
01567 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
01568 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
01569 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
01570 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
01571 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
01572 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
01573 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
01574 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
01575 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
01576 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
01577 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1)
01578 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
01579 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
01580 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
01581 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1)
01582 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
01583 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
01584 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
01585 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
01586 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
01587 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
01588 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
01589 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
01590 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
01591 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
01592 /* @brief Has device die ID (register bit field SDID[DIEID]). */
01593 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
01594 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
01595 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
01596 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
01597 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
01598 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
01599 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
01600 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
01601 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
01602 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
01603 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
01604 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
01605 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
01606 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
01607 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
01608 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
01609 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
01610 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
01611 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
01612 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
01613 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
01614 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
01615 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
01616 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
01617 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
01618 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
01619 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1)
01620 /* @brief Has miscellanious control register (register MCR). */
01621 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
01622 /* @brief Has COP watchdog (registers COPC and SRVCOP). */
01623 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
01624 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
01625 #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
01626 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
01627 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
01628 
01629 /* SMC module features */
01630 
01631 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
01632 #define FSL_FEATURE_SMC_HAS_PSTOPO (1)
01633 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
01634 #define FSL_FEATURE_SMC_HAS_LPOPO (0)
01635 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
01636 #define FSL_FEATURE_SMC_HAS_PORPO (1)
01637 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
01638 #define FSL_FEATURE_SMC_HAS_LPWUI (0)
01639 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
01640 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
01641 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
01642 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
01643 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
01644 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
01645 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
01646 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1)
01647 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
01648 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
01649 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
01650 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
01651 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
01652 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
01653 /* @brief Has stop submode. */
01654 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
01655 /* @brief Has stop submode 0(VLLS0). */
01656 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
01657 /* @brief Has stop submode 1(VLLS1). */
01658 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1)
01659 /* @brief Has stop submode 2(VLLS2). */
01660 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
01661 /* @brief Has SMC_PARAM. */
01662 #define FSL_FEATURE_SMC_HAS_PARAM (0)
01663 /* @brief Has SMC_VERID. */
01664 #define FSL_FEATURE_SMC_HAS_VERID (0)
01665 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
01666 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
01667 /* @brief Has tamper reset (register bit SRS[TAMPER]). */
01668 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
01669 /* @brief Has security violation reset (register bit SRS[SECVIO]). */
01670 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
01671 
01672 /* DSPI module features */
01673 
01674 /* @brief Receive/transmit FIFO size in number of items. */
01675 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
01676     ((x) == SPI0 ? (4) : \
01677     ((x) == SPI1 ? (1) : \
01678     ((x) == SPI2 ? (1) : (-1))))
01679 /* @brief Maximum transfer data width in bits. */
01680 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
01681 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
01682 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
01683 /* @brief Number of chip select pins. */
01684 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
01685 /* @brief Number of CTAR registers. */
01686 #define FSL_FEATURE_DSPI_CTAR_COUNT (2)
01687 /* @brief Has chip select strobe capability on the PCS5 pin. */
01688 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
01689 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
01690 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
01691 /* @brief Has 16-bit data transfer support. */
01692 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
01693 /* @brief Has separate DMA RX and TX requests. */
01694 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
01695 
01696 /* SYSMPU module features */
01697 
01698 /* @brief Specifies number of descriptors available. */
01699 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12)
01700 /* @brief Has process identifier support. */
01701 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1)
01702 /* @brief Total number of MPU slave. */
01703 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5)
01704 /* @brief Total number of MPU master. */
01705 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (7)
01706 
01707 /* SysTick module features */
01708 
01709 /* @brief Systick has external reference clock. */
01710 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
01711 /* @brief Systick external reference clock is core clock divided by this value. */
01712 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
01713 
01714 /* TPM module features */
01715 
01716 /* @brief Bus clock is the source clock for the module. */
01717 #define FSL_FEATURE_TPM_BUS_CLOCK (0)
01718 /* @brief Number of channels. */
01719 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) (2)
01720 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
01721 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
01722 /* @brief Has TPM_PARAM. */
01723 #define FSL_FEATURE_TPM_HAS_PARAM (0)
01724 /* @brief Has TPM_VERID. */
01725 #define FSL_FEATURE_TPM_HAS_VERID (0)
01726 /* @brief Has TPM_GLOBAL. */
01727 #define FSL_FEATURE_TPM_HAS_GLOBAL (0)
01728 /* @brief Has TPM_TRIG. */
01729 #define FSL_FEATURE_TPM_HAS_TRIG (0)
01730 /* @brief Has counter pause on trigger. */
01731 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
01732 /* @brief Has external trigger selection. */
01733 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
01734 /* @brief Has TPM_COMBINE register. */
01735 #define FSL_FEATURE_TPM_HAS_COMBINE (1)
01736 /* @brief Whether COMBINE register has effect. */
01737 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1)
01738 /* @brief Has TPM_POL. */
01739 #define FSL_FEATURE_TPM_HAS_POL (1)
01740 /* @brief Has TPM_FILTER register. */
01741 #define FSL_FEATURE_TPM_HAS_FILTER (1)
01742 /* @brief Whether FILTER register has effect. */
01743 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1)
01744 /* @brief Has TPM_QDCTRL register. */
01745 #define FSL_FEATURE_TPM_HAS_QDCTRL (1)
01746 /* @brief Whether QDCTRL register has effect. */
01747 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1)
01748 
01749 /* TSI module features */
01750 
01751 /* @brief TSI module version. */
01752 #define FSL_FEATURE_TSI_VERSION (4)
01753 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
01754 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (1)
01755 /* @brief Number of TSI channels. */
01756 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
01757 
01758 /* UART module features */
01759 
01760 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
01761 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
01762 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
01763 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
01764 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
01765 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
01766 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
01767 #define FSL_FEATURE_UART_HAS_FIFO (1)
01768 /* @brief Hardware flow control (RTS, CTS) is supported. */
01769 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
01770 /* @brief Infrared (modulation) is supported. */
01771 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
01772 /* @brief 2 bits long stop bit is available. */
01773 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
01774 /* @brief If 10-bit mode is supported. */
01775 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
01776 /* @brief Baud rate fine adjustment is available. */
01777 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
01778 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
01779 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
01780 /* @brief Baud rate oversampling is available. */
01781 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
01782 /* @brief Baud rate oversampling is available. */
01783 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
01784 /* @brief Peripheral type. */
01785 #define FSL_FEATURE_UART_IS_SCI (0)
01786 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
01787 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
01788     ((x) == UART0 ? (8) : \
01789     ((x) == UART1 ? (8) : \
01790     ((x) == UART2 ? (1) : \
01791     ((x) == UART3 ? (1) : \
01792     ((x) == UART4 ? (1) : (-1))))))
01793 /* @brief Maximal data width without parity bit. */
01794 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
01795 /* @brief Maximal data width with parity bit. */
01796 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
01797 /* @brief Supports two match addresses to filter incoming frames. */
01798 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
01799 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
01800 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
01801 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
01802 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
01803 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
01804 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
01805 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
01806 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
01807 /* @brief Has improved smart card (ISO7816 protocol) support. */
01808 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
01809 /* @brief Has local operation network (CEA709.1-B protocol) support. */
01810 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
01811 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
01812 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
01813 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
01814 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
01815 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
01816 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
01817 /* @brief Has separate DMA RX and TX requests. */
01818 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
01819     ((x) == UART0 ? (1) : \
01820     ((x) == UART1 ? (1) : \
01821     ((x) == UART2 ? (1) : \
01822     ((x) == UART3 ? (1) : \
01823     ((x) == UART4 ? (0) : (-1))))))
01824 
01825 /* USB module features */
01826 
01827 /* @brief KHCI module instance count */
01828 #define FSL_FEATURE_USB_KHCI_COUNT (1)
01829 /* @brief HOST mode enabled */
01830 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
01831 /* @brief OTG mode enabled */
01832 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
01833 /* @brief Size of the USB dedicated RAM */
01834 #define FSL_FEATURE_USB_KHCI_USB_RAM (0)
01835 /* @brief Has KEEP_ALIVE_CTRL register */
01836 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
01837 /* @brief Has the Dynamic SOF threshold compare support */
01838 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
01839 /* @brief Has the VBUS detect support */
01840 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
01841 /* @brief Has the IRC48M module clock support */
01842 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
01843 /* @brief Number of endpoints supported */
01844 #define FSL_FEATURE_USB_ENDPT_COUNT (16)
01845 /* @brief Has STALL_IL/OL_DIS registers */
01846 #define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0)
01847 /* @brief Has STALL_IH/OH_DIS registers */
01848 #define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0)
01849 
01850 /* USBHS module features */
01851 
01852 /* @brief EHCI module instance count */
01853 #define FSL_FEATURE_USBHS_EHCI_COUNT (1)
01854 /* @brief Number of endpoints supported */
01855 #define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
01856 
01857 /* VREF module features */
01858 
01859 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */
01860 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
01861 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
01862 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
01863 /* @brief If high/low buffer mode supported */
01864 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
01865 /* @brief Module has also low reference (registers VREFL/VREFH) */
01866 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
01867 /* @brief Has VREF_TRM4. */
01868 #define FSL_FEATURE_VREF_HAS_TRM4 (0)
01869 
01870 /* WDOG module features */
01871 
01872 /* @brief Watchdog is available. */
01873 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
01874 /* @brief Has Wait mode support. */
01875 #define FSL_FEATURE_WDOG_HAS_WAITEN (1)
01876 
01877 #endif /* _MK26F18_FEATURES_H_ */
01878