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MK20D5_features.h
00001 /* 00002 ** ################################################################### 00003 ** Version: rev. 2.7, 2015-06-08 00004 ** Build: b151210 00005 ** 00006 ** Abstract: 00007 ** Chip specific module features. 00008 ** 00009 ** Copyright (c) 2015 Freescale Semiconductor, Inc. 00010 ** All rights reserved. 00011 ** 00012 ** Redistribution and use in source and binary forms, with or without modification, 00013 ** are permitted provided that the following conditions are met: 00014 ** 00015 ** o Redistributions of source code must retain the above copyright notice, this list 00016 ** of conditions and the following disclaimer. 00017 ** 00018 ** o Redistributions in binary form must reproduce the above copyright notice, this 00019 ** list of conditions and the following disclaimer in the documentation and/or 00020 ** other materials provided with the distribution. 00021 ** 00022 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00023 ** contributors may be used to endorse or promote products derived from this 00024 ** software without specific prior written permission. 00025 ** 00026 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00027 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00028 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00029 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00030 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00031 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00032 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00033 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00034 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00035 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00036 ** 00037 ** http: www.freescale.com 00038 ** mail: support@freescale.com 00039 ** 00040 ** Revisions: 00041 ** - rev. 1.0 (2011-12-15) 00042 ** Initial version 00043 ** - rev. 2.0 (2012-03-19) 00044 ** PDB Peripheral register structure updated. 00045 ** DMA Registers and bits for unsupported DMA channels removed. 00046 ** - rev. 2.1 (2013-06-24) 00047 ** NV_FOPT register - NMI_DIS bit added. 00048 ** - rev. 2.2 (2014-01-30) 00049 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. 00050 ** - rev. 2.3 (2015-01-21) 00051 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 00052 ** - rev. 2.4 (2015-05-19) 00053 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 00054 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 00055 ** Added features for PDB and PORT. 00056 ** - rev. 2.5 (2015-05-25) 00057 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 00058 ** - rev. 2.6 (2015-05-27) 00059 ** Several USB features added. 00060 ** - rev. 2.7 (2015-06-08) 00061 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 00062 ** 00063 ** ################################################################### 00064 */ 00065 00066 #ifndef _MK20D5_FEATURES_H_ 00067 #define _MK20D5_FEATURES_H_ 00068 00069 /* SOC module features */ 00070 00071 #if defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ 00072 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) 00073 /* @brief ACMP availability on the SoC. */ 00074 #define FSL_FEATURE_SOC_ACMP_COUNT (0) 00075 /* @brief ADC16 availability on the SoC. */ 00076 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 00077 /* @brief ADC12 availability on the SoC. */ 00078 #define FSL_FEATURE_SOC_ADC12_COUNT (0) 00079 /* @brief AFE availability on the SoC. */ 00080 #define FSL_FEATURE_SOC_AFE_COUNT (0) 00081 /* @brief AIPS availability on the SoC. */ 00082 #define FSL_FEATURE_SOC_AIPS_COUNT (0) 00083 /* @brief AOI availability on the SoC. */ 00084 #define FSL_FEATURE_SOC_AOI_COUNT (0) 00085 /* @brief AXBS availability on the SoC. */ 00086 #define FSL_FEATURE_SOC_AXBS_COUNT (0) 00087 /* @brief ASMC availability on the SoC. */ 00088 #define FSL_FEATURE_SOC_ASMC_COUNT (0) 00089 /* @brief CADC availability on the SoC. */ 00090 #define FSL_FEATURE_SOC_CADC_COUNT (0) 00091 /* @brief FLEXCAN availability on the SoC. */ 00092 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) 00093 /* @brief MMCAU availability on the SoC. */ 00094 #define FSL_FEATURE_SOC_MMCAU_COUNT (0) 00095 /* @brief CMP availability on the SoC. */ 00096 #define FSL_FEATURE_SOC_CMP_COUNT (2) 00097 /* @brief CMT availability on the SoC. */ 00098 #define FSL_FEATURE_SOC_CMT_COUNT (1) 00099 /* @brief CNC availability on the SoC. */ 00100 #define FSL_FEATURE_SOC_CNC_COUNT (0) 00101 /* @brief CRC availability on the SoC. */ 00102 #define FSL_FEATURE_SOC_CRC_COUNT (1) 00103 /* @brief DAC availability on the SoC. */ 00104 #define FSL_FEATURE_SOC_DAC_COUNT (0) 00105 /* @brief DAC32 availability on the SoC. */ 00106 #define FSL_FEATURE_SOC_DAC32_COUNT (0) 00107 /* @brief DCDC availability on the SoC. */ 00108 #define FSL_FEATURE_SOC_DCDC_COUNT (0) 00109 /* @brief DDR availability on the SoC. */ 00110 #define FSL_FEATURE_SOC_DDR_COUNT (0) 00111 /* @brief DMA availability on the SoC. */ 00112 #define FSL_FEATURE_SOC_DMA_COUNT (0) 00113 /* @brief DMAMUX availability on the SoC. */ 00114 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 00115 /* @brief DRY availability on the SoC. */ 00116 #define FSL_FEATURE_SOC_DRY_COUNT (0) 00117 /* @brief DSPI availability on the SoC. */ 00118 #define FSL_FEATURE_SOC_DSPI_COUNT (1) 00119 /* @brief EDMA availability on the SoC. */ 00120 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 00121 /* @brief EMVSIM availability on the SoC. */ 00122 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) 00123 /* @brief ENC availability on the SoC. */ 00124 #define FSL_FEATURE_SOC_ENC_COUNT (0) 00125 /* @brief ENET availability on the SoC. */ 00126 #define FSL_FEATURE_SOC_ENET_COUNT (0) 00127 /* @brief EWM availability on the SoC. */ 00128 #define FSL_FEATURE_SOC_EWM_COUNT (1) 00129 /* @brief FB availability on the SoC. */ 00130 #define FSL_FEATURE_SOC_FB_COUNT (0) 00131 /* @brief FGPIO availability on the SoC. */ 00132 #define FSL_FEATURE_SOC_FGPIO_COUNT (0) 00133 /* @brief FLEXIO availability on the SoC. */ 00134 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) 00135 /* @brief FMC availability on the SoC. */ 00136 #define FSL_FEATURE_SOC_FMC_COUNT (1) 00137 /* @brief FSKDT availability on the SoC. */ 00138 #define FSL_FEATURE_SOC_FSKDT_COUNT (0) 00139 /* @brief FTFA availability on the SoC. */ 00140 #define FSL_FEATURE_SOC_FTFA_COUNT (0) 00141 /* @brief FTFE availability on the SoC. */ 00142 #define FSL_FEATURE_SOC_FTFE_COUNT (0) 00143 /* @brief FTFL availability on the SoC. */ 00144 #define FSL_FEATURE_SOC_FTFL_COUNT (1) 00145 /* @brief FTM availability on the SoC. */ 00146 #define FSL_FEATURE_SOC_FTM_COUNT (2) 00147 /* @brief FTMRA availability on the SoC. */ 00148 #define FSL_FEATURE_SOC_FTMRA_COUNT (0) 00149 /* @brief FTMRE availability on the SoC. */ 00150 #define FSL_FEATURE_SOC_FTMRE_COUNT (0) 00151 /* @brief FTMRH availability on the SoC. */ 00152 #define FSL_FEATURE_SOC_FTMRH_COUNT (0) 00153 /* @brief GPIO availability on the SoC. */ 00154 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 00155 /* @brief HSADC availability on the SoC. */ 00156 #define FSL_FEATURE_SOC_HSADC_COUNT (0) 00157 /* @brief I2C availability on the SoC. */ 00158 #define FSL_FEATURE_SOC_I2C_COUNT (1) 00159 /* @brief I2S availability on the SoC. */ 00160 #define FSL_FEATURE_SOC_I2S_COUNT (1) 00161 /* @brief ICS availability on the SoC. */ 00162 #define FSL_FEATURE_SOC_ICS_COUNT (0) 00163 /* @brief IRQ availability on the SoC. */ 00164 #define FSL_FEATURE_SOC_IRQ_COUNT (0) 00165 /* @brief INTMUX availability on the SoC. */ 00166 #define FSL_FEATURE_SOC_INTMUX_COUNT (0) 00167 /* @brief KBI availability on the SoC. */ 00168 #define FSL_FEATURE_SOC_KBI_COUNT (0) 00169 /* @brief SLCD availability on the SoC. */ 00170 #define FSL_FEATURE_SOC_SLCD_COUNT (0) 00171 /* @brief LCDC availability on the SoC. */ 00172 #define FSL_FEATURE_SOC_LCDC_COUNT (0) 00173 /* @brief LDO availability on the SoC. */ 00174 #define FSL_FEATURE_SOC_LDO_COUNT (0) 00175 /* @brief LLWU availability on the SoC. */ 00176 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 00177 /* @brief LMEM availability on the SoC. */ 00178 #define FSL_FEATURE_SOC_LMEM_COUNT (0) 00179 /* @brief LPSCI availability on the SoC. */ 00180 #define FSL_FEATURE_SOC_LPSCI_COUNT (0) 00181 /* @brief LPTMR availability on the SoC. */ 00182 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 00183 /* @brief LPTPM availability on the SoC. */ 00184 #define FSL_FEATURE_SOC_LPTPM_COUNT (0) 00185 /* @brief LPUART availability on the SoC. */ 00186 #define FSL_FEATURE_SOC_LPUART_COUNT (0) 00187 /* @brief LTC availability on the SoC. */ 00188 #define FSL_FEATURE_SOC_LTC_COUNT (0) 00189 /* @brief LPI2C availability on the SoC. */ 00190 #define FSL_FEATURE_SOC_LPI2C_COUNT (0) 00191 /* @brief LPSPI availability on the SoC. */ 00192 #define FSL_FEATURE_SOC_LPSPI_COUNT (0) 00193 /* @brief LPIT availability on the SoC. */ 00194 #define FSL_FEATURE_SOC_LPIT_COUNT (0) 00195 /* @brief MC availability on the SoC. */ 00196 #define FSL_FEATURE_SOC_MC_COUNT (0) 00197 /* @brief MCG availability on the SoC. */ 00198 #define FSL_FEATURE_SOC_MCG_COUNT (1) 00199 /* @brief MCGLITE availability on the SoC. */ 00200 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) 00201 /* @brief MCM availability on the SoC. */ 00202 #define FSL_FEATURE_SOC_MCM_COUNT (0) 00203 /* @brief MMAU availability on the SoC. */ 00204 #define FSL_FEATURE_SOC_MMAU_COUNT (0) 00205 /* @brief MMDVSQ availability on the SoC. */ 00206 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) 00207 /* @brief MPU availability on the SoC. */ 00208 #define FSL_FEATURE_SOC_MPU_COUNT (0) 00209 /* @brief MSCAN availability on the SoC. */ 00210 #define FSL_FEATURE_SOC_MSCAN_COUNT (0) 00211 /* @brief MSCM availability on the SoC. */ 00212 #define FSL_FEATURE_SOC_MSCM_COUNT (0) 00213 /* @brief MTB availability on the SoC. */ 00214 #define FSL_FEATURE_SOC_MTB_COUNT (0) 00215 /* @brief MTBDWT availability on the SoC. */ 00216 #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) 00217 /* @brief MU availability on the SoC. */ 00218 #define FSL_FEATURE_SOC_MU_COUNT (0) 00219 /* @brief NFC availability on the SoC. */ 00220 #define FSL_FEATURE_SOC_NFC_COUNT (0) 00221 /* @brief OPAMP availability on the SoC. */ 00222 #define FSL_FEATURE_SOC_OPAMP_COUNT (0) 00223 /* @brief OSC availability on the SoC. */ 00224 #define FSL_FEATURE_SOC_OSC_COUNT (1) 00225 /* @brief OSC32 availability on the SoC. */ 00226 #define FSL_FEATURE_SOC_OSC32_COUNT (0) 00227 /* @brief OTFAD availability on the SoC. */ 00228 #define FSL_FEATURE_SOC_OTFAD_COUNT (0) 00229 /* @brief PDB availability on the SoC. */ 00230 #define FSL_FEATURE_SOC_PDB_COUNT (1) 00231 /* @brief PGA availability on the SoC. */ 00232 #define FSL_FEATURE_SOC_PGA_COUNT (0) 00233 /* @brief PIT availability on the SoC. */ 00234 #define FSL_FEATURE_SOC_PIT_COUNT (1) 00235 /* @brief PMC availability on the SoC. */ 00236 #define FSL_FEATURE_SOC_PMC_COUNT (1) 00237 /* @brief PORT availability on the SoC. */ 00238 #define FSL_FEATURE_SOC_PORT_COUNT (5) 00239 /* @brief PWM availability on the SoC. */ 00240 #define FSL_FEATURE_SOC_PWM_COUNT (0) 00241 /* @brief PWT availability on the SoC. */ 00242 #define FSL_FEATURE_SOC_PWT_COUNT (0) 00243 /* @brief PCC availability on the SoC. */ 00244 #define FSL_FEATURE_SOC_PCC_COUNT (0) 00245 /* @brief QuadSPI availability on the SoC. */ 00246 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) 00247 /* @brief RCM availability on the SoC. */ 00248 #define FSL_FEATURE_SOC_RCM_COUNT (1) 00249 /* @brief RFSYS availability on the SoC. */ 00250 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 00251 /* @brief RFVBAT availability on the SoC. */ 00252 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 00253 /* @brief RNG availability on the SoC. */ 00254 #define FSL_FEATURE_SOC_RNG_COUNT (0) 00255 /* @brief RNGB availability on the SoC. */ 00256 #define FSL_FEATURE_SOC_RNGB_COUNT (0) 00257 /* @brief ROM availability on the SoC. */ 00258 #define FSL_FEATURE_SOC_ROM_COUNT (0) 00259 /* @brief RSIM availability on the SoC. */ 00260 #define FSL_FEATURE_SOC_RSIM_COUNT (0) 00261 /* @brief RTC availability on the SoC. */ 00262 #define FSL_FEATURE_SOC_RTC_COUNT (1) 00263 /* @brief SCI availability on the SoC. */ 00264 #define FSL_FEATURE_SOC_SCI_COUNT (0) 00265 /* @brief SDHC availability on the SoC. */ 00266 #define FSL_FEATURE_SOC_SDHC_COUNT (0) 00267 /* @brief SDRAM availability on the SoC. */ 00268 #define FSL_FEATURE_SOC_SDRAM_COUNT (0) 00269 /* @brief SIM availability on the SoC. */ 00270 #define FSL_FEATURE_SOC_SIM_COUNT (1) 00271 /* @brief SMC availability on the SoC. */ 00272 #define FSL_FEATURE_SOC_SMC_COUNT (1) 00273 /* @brief SPI availability on the SoC. */ 00274 #define FSL_FEATURE_SOC_SPI_COUNT (0) 00275 /* @brief SCG availability on the SoC. */ 00276 #define FSL_FEATURE_SOC_SCG_COUNT (0) 00277 /* @brief SEMA42 availability on the SoC. */ 00278 #define FSL_FEATURE_SOC_SEMA42_COUNT (0) 00279 /* @brief TMR availability on the SoC. */ 00280 #define FSL_FEATURE_SOC_TMR_COUNT (0) 00281 /* @brief TPM availability on the SoC. */ 00282 #define FSL_FEATURE_SOC_TPM_COUNT (0) 00283 /* @brief TRIAMP availability on the SoC. */ 00284 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) 00285 /* @brief TRNG availability on the SoC. */ 00286 #define FSL_FEATURE_SOC_TRNG_COUNT (0) 00287 /* @brief TSI availability on the SoC. */ 00288 #define FSL_FEATURE_SOC_TSI_COUNT (1) 00289 /* @brief TRGMUX availability on the SoC. */ 00290 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) 00291 /* @brief TSTMR availability on the SoC. */ 00292 #define FSL_FEATURE_SOC_TSTMR_COUNT (0) 00293 /* @brief UART availability on the SoC. */ 00294 #define FSL_FEATURE_SOC_UART_COUNT (3) 00295 /* @brief USB availability on the SoC. */ 00296 #define FSL_FEATURE_SOC_USB_COUNT (1) 00297 /* @brief USBDCD availability on the SoC. */ 00298 #define FSL_FEATURE_SOC_USBDCD_COUNT (1) 00299 /* @brief USBHSDCD availability on the SoC. */ 00300 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) 00301 /* @brief USBPHY availability on the SoC. */ 00302 #define FSL_FEATURE_SOC_USBPHY_COUNT (0) 00303 /* @brief VREF availability on the SoC. */ 00304 #define FSL_FEATURE_SOC_VREF_COUNT (0) 00305 /* @brief WDOG availability on the SoC. */ 00306 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 00307 /* @brief XBAR availability on the SoC. */ 00308 #define FSL_FEATURE_SOC_XBAR_COUNT (0) 00309 /* @brief XBARA availability on the SoC. */ 00310 #define FSL_FEATURE_SOC_XBARA_COUNT (0) 00311 /* @brief XBARB availability on the SoC. */ 00312 #define FSL_FEATURE_SOC_XBARB_COUNT (0) 00313 /* @brief XCVR availability on the SoC. */ 00314 #define FSL_FEATURE_SOC_XCVR_COUNT (0) 00315 /* @brief XRDC availability on the SoC. */ 00316 #define FSL_FEATURE_SOC_XRDC_COUNT (0) 00317 /* @brief ZLL availability on the SoC. */ 00318 #define FSL_FEATURE_SOC_ZLL_COUNT (0) 00319 #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ 00320 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ 00321 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ 00322 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ 00323 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ 00324 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) 00325 /* @brief ACMP availability on the SoC. */ 00326 #define FSL_FEATURE_SOC_ACMP_COUNT (0) 00327 /* @brief ADC16 availability on the SoC. */ 00328 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 00329 /* @brief ADC12 availability on the SoC. */ 00330 #define FSL_FEATURE_SOC_ADC12_COUNT (0) 00331 /* @brief AFE availability on the SoC. */ 00332 #define FSL_FEATURE_SOC_AFE_COUNT (0) 00333 /* @brief AIPS availability on the SoC. */ 00334 #define FSL_FEATURE_SOC_AIPS_COUNT (0) 00335 /* @brief AOI availability on the SoC. */ 00336 #define FSL_FEATURE_SOC_AOI_COUNT (0) 00337 /* @brief AXBS availability on the SoC. */ 00338 #define FSL_FEATURE_SOC_AXBS_COUNT (0) 00339 /* @brief ASMC availability on the SoC. */ 00340 #define FSL_FEATURE_SOC_ASMC_COUNT (0) 00341 /* @brief CADC availability on the SoC. */ 00342 #define FSL_FEATURE_SOC_CADC_COUNT (0) 00343 /* @brief FLEXCAN availability on the SoC. */ 00344 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) 00345 /* @brief MMCAU availability on the SoC. */ 00346 #define FSL_FEATURE_SOC_MMCAU_COUNT (0) 00347 /* @brief CMP availability on the SoC. */ 00348 #define FSL_FEATURE_SOC_CMP_COUNT (2) 00349 /* @brief CMT availability on the SoC. */ 00350 #define FSL_FEATURE_SOC_CMT_COUNT (1) 00351 /* @brief CNC availability on the SoC. */ 00352 #define FSL_FEATURE_SOC_CNC_COUNT (0) 00353 /* @brief CRC availability on the SoC. */ 00354 #define FSL_FEATURE_SOC_CRC_COUNT (1) 00355 /* @brief DAC availability on the SoC. */ 00356 #define FSL_FEATURE_SOC_DAC_COUNT (0) 00357 /* @brief DAC32 availability on the SoC. */ 00358 #define FSL_FEATURE_SOC_DAC32_COUNT (0) 00359 /* @brief DCDC availability on the SoC. */ 00360 #define FSL_FEATURE_SOC_DCDC_COUNT (0) 00361 /* @brief DDR availability on the SoC. */ 00362 #define FSL_FEATURE_SOC_DDR_COUNT (0) 00363 /* @brief DMA availability on the SoC. */ 00364 #define FSL_FEATURE_SOC_DMA_COUNT (0) 00365 /* @brief DMAMUX availability on the SoC. */ 00366 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 00367 /* @brief DRY availability on the SoC. */ 00368 #define FSL_FEATURE_SOC_DRY_COUNT (0) 00369 /* @brief DSPI availability on the SoC. */ 00370 #define FSL_FEATURE_SOC_DSPI_COUNT (1) 00371 /* @brief EDMA availability on the SoC. */ 00372 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 00373 /* @brief EMVSIM availability on the SoC. */ 00374 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) 00375 /* @brief ENC availability on the SoC. */ 00376 #define FSL_FEATURE_SOC_ENC_COUNT (0) 00377 /* @brief ENET availability on the SoC. */ 00378 #define FSL_FEATURE_SOC_ENET_COUNT (0) 00379 /* @brief EWM availability on the SoC. */ 00380 #define FSL_FEATURE_SOC_EWM_COUNT (1) 00381 /* @brief FB availability on the SoC. */ 00382 #define FSL_FEATURE_SOC_FB_COUNT (0) 00383 /* @brief FGPIO availability on the SoC. */ 00384 #define FSL_FEATURE_SOC_FGPIO_COUNT (0) 00385 /* @brief FLEXIO availability on the SoC. */ 00386 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) 00387 /* @brief FMC availability on the SoC. */ 00388 #define FSL_FEATURE_SOC_FMC_COUNT (1) 00389 /* @brief FSKDT availability on the SoC. */ 00390 #define FSL_FEATURE_SOC_FSKDT_COUNT (0) 00391 /* @brief FTFA availability on the SoC. */ 00392 #define FSL_FEATURE_SOC_FTFA_COUNT (0) 00393 /* @brief FTFE availability on the SoC. */ 00394 #define FSL_FEATURE_SOC_FTFE_COUNT (0) 00395 /* @brief FTFL availability on the SoC. */ 00396 #define FSL_FEATURE_SOC_FTFL_COUNT (1) 00397 /* @brief FTM availability on the SoC. */ 00398 #define FSL_FEATURE_SOC_FTM_COUNT (2) 00399 /* @brief FTMRA availability on the SoC. */ 00400 #define FSL_FEATURE_SOC_FTMRA_COUNT (0) 00401 /* @brief FTMRE availability on the SoC. */ 00402 #define FSL_FEATURE_SOC_FTMRE_COUNT (0) 00403 /* @brief FTMRH availability on the SoC. */ 00404 #define FSL_FEATURE_SOC_FTMRH_COUNT (0) 00405 /* @brief GPIO availability on the SoC. */ 00406 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 00407 /* @brief HSADC availability on the SoC. */ 00408 #define FSL_FEATURE_SOC_HSADC_COUNT (0) 00409 /* @brief I2C availability on the SoC. */ 00410 #define FSL_FEATURE_SOC_I2C_COUNT (1) 00411 /* @brief I2S availability on the SoC. */ 00412 #define FSL_FEATURE_SOC_I2S_COUNT (1) 00413 /* @brief ICS availability on the SoC. */ 00414 #define FSL_FEATURE_SOC_ICS_COUNT (0) 00415 /* @brief IRQ availability on the SoC. */ 00416 #define FSL_FEATURE_SOC_IRQ_COUNT (0) 00417 /* @brief INTMUX availability on the SoC. */ 00418 #define FSL_FEATURE_SOC_INTMUX_COUNT (0) 00419 /* @brief KBI availability on the SoC. */ 00420 #define FSL_FEATURE_SOC_KBI_COUNT (0) 00421 /* @brief SLCD availability on the SoC. */ 00422 #define FSL_FEATURE_SOC_SLCD_COUNT (0) 00423 /* @brief LCDC availability on the SoC. */ 00424 #define FSL_FEATURE_SOC_LCDC_COUNT (0) 00425 /* @brief LDO availability on the SoC. */ 00426 #define FSL_FEATURE_SOC_LDO_COUNT (0) 00427 /* @brief LLWU availability on the SoC. */ 00428 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 00429 /* @brief LMEM availability on the SoC. */ 00430 #define FSL_FEATURE_SOC_LMEM_COUNT (0) 00431 /* @brief LPSCI availability on the SoC. */ 00432 #define FSL_FEATURE_SOC_LPSCI_COUNT (0) 00433 /* @brief LPTMR availability on the SoC. */ 00434 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 00435 /* @brief LPTPM availability on the SoC. */ 00436 #define FSL_FEATURE_SOC_LPTPM_COUNT (0) 00437 /* @brief LPUART availability on the SoC. */ 00438 #define FSL_FEATURE_SOC_LPUART_COUNT (0) 00439 /* @brief LTC availability on the SoC. */ 00440 #define FSL_FEATURE_SOC_LTC_COUNT (0) 00441 /* @brief LPI2C availability on the SoC. */ 00442 #define FSL_FEATURE_SOC_LPI2C_COUNT (0) 00443 /* @brief LPSPI availability on the SoC. */ 00444 #define FSL_FEATURE_SOC_LPSPI_COUNT (0) 00445 /* @brief LPIT availability on the SoC. */ 00446 #define FSL_FEATURE_SOC_LPIT_COUNT (0) 00447 /* @brief MC availability on the SoC. */ 00448 #define FSL_FEATURE_SOC_MC_COUNT (0) 00449 /* @brief MCG availability on the SoC. */ 00450 #define FSL_FEATURE_SOC_MCG_COUNT (1) 00451 /* @brief MCGLITE availability on the SoC. */ 00452 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) 00453 /* @brief MCM availability on the SoC. */ 00454 #define FSL_FEATURE_SOC_MCM_COUNT (0) 00455 /* @brief MMAU availability on the SoC. */ 00456 #define FSL_FEATURE_SOC_MMAU_COUNT (0) 00457 /* @brief MMDVSQ availability on the SoC. */ 00458 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) 00459 /* @brief MPU availability on the SoC. */ 00460 #define FSL_FEATURE_SOC_MPU_COUNT (0) 00461 /* @brief MSCAN availability on the SoC. */ 00462 #define FSL_FEATURE_SOC_MSCAN_COUNT (0) 00463 /* @brief MSCM availability on the SoC. */ 00464 #define FSL_FEATURE_SOC_MSCM_COUNT (0) 00465 /* @brief MTB availability on the SoC. */ 00466 #define FSL_FEATURE_SOC_MTB_COUNT (0) 00467 /* @brief MTBDWT availability on the SoC. */ 00468 #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) 00469 /* @brief MU availability on the SoC. */ 00470 #define FSL_FEATURE_SOC_MU_COUNT (0) 00471 /* @brief NFC availability on the SoC. */ 00472 #define FSL_FEATURE_SOC_NFC_COUNT (0) 00473 /* @brief OPAMP availability on the SoC. */ 00474 #define FSL_FEATURE_SOC_OPAMP_COUNT (0) 00475 /* @brief OSC availability on the SoC. */ 00476 #define FSL_FEATURE_SOC_OSC_COUNT (1) 00477 /* @brief OSC32 availability on the SoC. */ 00478 #define FSL_FEATURE_SOC_OSC32_COUNT (0) 00479 /* @brief OTFAD availability on the SoC. */ 00480 #define FSL_FEATURE_SOC_OTFAD_COUNT (0) 00481 /* @brief PDB availability on the SoC. */ 00482 #define FSL_FEATURE_SOC_PDB_COUNT (1) 00483 /* @brief PGA availability on the SoC. */ 00484 #define FSL_FEATURE_SOC_PGA_COUNT (0) 00485 /* @brief PIT availability on the SoC. */ 00486 #define FSL_FEATURE_SOC_PIT_COUNT (1) 00487 /* @brief PMC availability on the SoC. */ 00488 #define FSL_FEATURE_SOC_PMC_COUNT (1) 00489 /* @brief PORT availability on the SoC. */ 00490 #define FSL_FEATURE_SOC_PORT_COUNT (5) 00491 /* @brief PWM availability on the SoC. */ 00492 #define FSL_FEATURE_SOC_PWM_COUNT (0) 00493 /* @brief PWT availability on the SoC. */ 00494 #define FSL_FEATURE_SOC_PWT_COUNT (0) 00495 /* @brief PCC availability on the SoC. */ 00496 #define FSL_FEATURE_SOC_PCC_COUNT (0) 00497 /* @brief QuadSPI availability on the SoC. */ 00498 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) 00499 /* @brief RCM availability on the SoC. */ 00500 #define FSL_FEATURE_SOC_RCM_COUNT (1) 00501 /* @brief RFSYS availability on the SoC. */ 00502 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 00503 /* @brief RFVBAT availability on the SoC. */ 00504 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 00505 /* @brief RNG availability on the SoC. */ 00506 #define FSL_FEATURE_SOC_RNG_COUNT (0) 00507 /* @brief RNGB availability on the SoC. */ 00508 #define FSL_FEATURE_SOC_RNGB_COUNT (0) 00509 /* @brief ROM availability on the SoC. */ 00510 #define FSL_FEATURE_SOC_ROM_COUNT (0) 00511 /* @brief RSIM availability on the SoC. */ 00512 #define FSL_FEATURE_SOC_RSIM_COUNT (0) 00513 /* @brief RTC availability on the SoC. */ 00514 #define FSL_FEATURE_SOC_RTC_COUNT (1) 00515 /* @brief SCI availability on the SoC. */ 00516 #define FSL_FEATURE_SOC_SCI_COUNT (0) 00517 /* @brief SDHC availability on the SoC. */ 00518 #define FSL_FEATURE_SOC_SDHC_COUNT (0) 00519 /* @brief SDRAM availability on the SoC. */ 00520 #define FSL_FEATURE_SOC_SDRAM_COUNT (0) 00521 /* @brief SIM availability on the SoC. */ 00522 #define FSL_FEATURE_SOC_SIM_COUNT (1) 00523 /* @brief SMC availability on the SoC. */ 00524 #define FSL_FEATURE_SOC_SMC_COUNT (1) 00525 /* @brief SPI availability on the SoC. */ 00526 #define FSL_FEATURE_SOC_SPI_COUNT (0) 00527 /* @brief SCG availability on the SoC. */ 00528 #define FSL_FEATURE_SOC_SCG_COUNT (0) 00529 /* @brief SEMA42 availability on the SoC. */ 00530 #define FSL_FEATURE_SOC_SEMA42_COUNT (0) 00531 /* @brief TMR availability on the SoC. */ 00532 #define FSL_FEATURE_SOC_TMR_COUNT (0) 00533 /* @brief TPM availability on the SoC. */ 00534 #define FSL_FEATURE_SOC_TPM_COUNT (0) 00535 /* @brief TRIAMP availability on the SoC. */ 00536 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) 00537 /* @brief TRNG availability on the SoC. */ 00538 #define FSL_FEATURE_SOC_TRNG_COUNT (0) 00539 /* @brief TSI availability on the SoC. */ 00540 #define FSL_FEATURE_SOC_TSI_COUNT (1) 00541 /* @brief TRGMUX availability on the SoC. */ 00542 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) 00543 /* @brief TSTMR availability on the SoC. */ 00544 #define FSL_FEATURE_SOC_TSTMR_COUNT (0) 00545 /* @brief UART availability on the SoC. */ 00546 #define FSL_FEATURE_SOC_UART_COUNT (3) 00547 /* @brief USB availability on the SoC. */ 00548 #define FSL_FEATURE_SOC_USB_COUNT (1) 00549 /* @brief USBDCD availability on the SoC. */ 00550 #define FSL_FEATURE_SOC_USBDCD_COUNT (1) 00551 /* @brief USBHSDCD availability on the SoC. */ 00552 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) 00553 /* @brief USBPHY availability on the SoC. */ 00554 #define FSL_FEATURE_SOC_USBPHY_COUNT (0) 00555 /* @brief VREF availability on the SoC. */ 00556 #define FSL_FEATURE_SOC_VREF_COUNT (1) 00557 /* @brief WDOG availability on the SoC. */ 00558 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 00559 /* @brief XBAR availability on the SoC. */ 00560 #define FSL_FEATURE_SOC_XBAR_COUNT (0) 00561 /* @brief XBARA availability on the SoC. */ 00562 #define FSL_FEATURE_SOC_XBARA_COUNT (0) 00563 /* @brief XBARB availability on the SoC. */ 00564 #define FSL_FEATURE_SOC_XBARB_COUNT (0) 00565 /* @brief XCVR availability on the SoC. */ 00566 #define FSL_FEATURE_SOC_XCVR_COUNT (0) 00567 /* @brief XRDC availability on the SoC. */ 00568 #define FSL_FEATURE_SOC_XRDC_COUNT (0) 00569 /* @brief ZLL availability on the SoC. */ 00570 #define FSL_FEATURE_SOC_ZLL_COUNT (0) 00571 #endif 00572 00573 /* ADC16 module features */ 00574 00575 #if defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ 00576 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) 00577 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 00578 #define FSL_FEATURE_ADC16_HAS_PGA (0) 00579 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 00580 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 00581 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 00582 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 00583 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 00584 #define FSL_FEATURE_ADC16_HAS_DMA (1) 00585 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 00586 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (0) 00587 /* @brief Has FIFO (bit SC4[AFDEP]). */ 00588 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 00589 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 00590 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 00591 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 00592 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 00593 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 00594 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 00595 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 00596 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 00597 /* @brief Has HW averaging (bit SC3[AVGE]). */ 00598 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 00599 /* @brief Has offset correction (register OFS). */ 00600 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 00601 /* @brief Maximum ADC resolution. */ 00602 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 00603 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 00604 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 00605 #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ 00606 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ 00607 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ 00608 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ 00609 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ 00610 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) 00611 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 00612 #define FSL_FEATURE_ADC16_HAS_PGA (0) 00613 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 00614 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 00615 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 00616 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 00617 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 00618 #define FSL_FEATURE_ADC16_HAS_DMA (1) 00619 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 00620 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 00621 /* @brief Has FIFO (bit SC4[AFDEP]). */ 00622 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 00623 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 00624 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 00625 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 00626 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 00627 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 00628 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 00629 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 00630 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 00631 /* @brief Has HW averaging (bit SC3[AVGE]). */ 00632 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 00633 /* @brief Has offset correction (register OFS). */ 00634 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 00635 /* @brief Maximum ADC resolution. */ 00636 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 00637 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 00638 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 00639 #endif /* defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ 00640 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) */ 00641 00642 /* CMP module features */ 00643 00644 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 00645 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) 00646 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 00647 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 00648 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 00649 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 00650 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 00651 #define FSL_FEATURE_CMP_HAS_DMA (1) 00652 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 00653 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 00654 /* @brief Has DAC Test function in CMP (register DACTEST). */ 00655 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 00656 00657 /* CRC module features */ 00658 00659 /* @brief Has data register with name CRC */ 00660 #define FSL_FEATURE_CRC_HAS_CRC_REG (1) 00661 00662 /* EDMA module features */ 00663 00664 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 00665 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) 00666 /* @brief Total number of DMA channels on all modules. */ 00667 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) 00668 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 00669 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 00670 /* @brief Has DMA_Error interrupt vector. */ 00671 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 00672 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 00673 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) 00674 00675 /* DMAMUX module features */ 00676 00677 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 00678 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) 00679 /* @brief Total number of DMA channels on all modules. */ 00680 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) 00681 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 00682 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 00683 00684 /* EWM module features */ 00685 00686 /* @brief Has clock select (register CLKCTRL). */ 00687 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 00688 /* @brief Has clock prescaler (register CLKPRESCALER). */ 00689 #define FSL_FEATURE_EWM_HAS_PRESCALER (0) 00690 00691 /* FLASH module features */ 00692 00693 #if defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DX128VFT5) || \ 00694 defined(CPU_MK20DX128VLF5) 00695 /* @brief Is of type FTFA. */ 00696 #define FSL_FEATURE_FLASH_IS_FTFA (0) 00697 /* @brief Is of type FTFE. */ 00698 #define FSL_FEATURE_FLASH_IS_FTFE (0) 00699 /* @brief Is of type FTFL. */ 00700 #define FSL_FEATURE_FLASH_IS_FTFL (1) 00701 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 00702 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 00703 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 00704 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 00705 /* @brief Has EEPROM region protection (register FEPROT). */ 00706 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 00707 /* @brief Has data flash region protection (register FDPROT). */ 00708 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 00709 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 00710 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 00711 /* @brief Has flash cache control in FMC module. */ 00712 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 00713 /* @brief Has flash cache control in MCM module. */ 00714 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 00715 /* @brief P-Flash start address. */ 00716 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 00717 /* @brief P-Flash block count. */ 00718 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 00719 /* @brief P-Flash block size. */ 00720 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) 00721 /* @brief P-Flash sector size. */ 00722 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 00723 /* @brief P-Flash write unit size. */ 00724 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 00725 /* @brief P-Flash data path width. */ 00726 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 00727 /* @brief P-Flash block swap feature. */ 00728 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 00729 /* @brief Has FlexNVM memory. */ 00730 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) 00731 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 00732 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) 00733 /* @brief FlexNVM block count. */ 00734 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) 00735 /* @brief FlexNVM block size. */ 00736 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (32768) 00737 /* @brief FlexNVM sector size. */ 00738 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (1024) 00739 /* @brief FlexNVM write unit size. */ 00740 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (4) 00741 /* @brief FlexNVM data path width. */ 00742 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (4) 00743 /* @brief Has FlexRAM memory. */ 00744 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 00745 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 00746 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 00747 /* @brief FlexRAM size. */ 00748 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) 00749 /* @brief Has 0x00 Read 1s Block command. */ 00750 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 00751 /* @brief Has 0x01 Read 1s Section command. */ 00752 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 00753 /* @brief Has 0x02 Program Check command. */ 00754 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 00755 /* @brief Has 0x03 Read Resource command. */ 00756 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 00757 /* @brief Has 0x06 Program Longword command. */ 00758 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 00759 /* @brief Has 0x07 Program Phrase command. */ 00760 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 00761 /* @brief Has 0x08 Erase Flash Block command. */ 00762 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 00763 /* @brief Has 0x09 Erase Flash Sector command. */ 00764 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 00765 /* @brief Has 0x0B Program Section command. */ 00766 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 00767 /* @brief Has 0x40 Read 1s All Blocks command. */ 00768 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) 00769 /* @brief Has 0x41 Read Once command. */ 00770 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 00771 /* @brief Has 0x43 Program Once command. */ 00772 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 00773 /* @brief Has 0x44 Erase All Blocks command. */ 00774 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) 00775 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 00776 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 00777 /* @brief Has 0x46 Swap Control command. */ 00778 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 00779 /* @brief Has 0x80 Program Partition command. */ 00780 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) 00781 /* @brief Has 0x81 Set FlexRAM Function command. */ 00782 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) 00783 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 00784 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 00785 /* @brief P-Flash Erase sector command address alignment. */ 00786 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 00787 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 00788 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 00789 /* @brief P-Flash Read resource command address alignment. */ 00790 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 00791 /* @brief P-Flash Program check command address alignment. */ 00792 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 00793 /* @brief P-Flash Program check command address alignment. */ 00794 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 00795 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 00796 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (4) 00797 /* @brief FlexNVM Erase sector command address alignment. */ 00798 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (4) 00799 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 00800 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (4) 00801 /* @brief FlexNVM Read resource command address alignment. */ 00802 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 00803 /* @brief FlexNVM Program check command address alignment. */ 00804 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) 00805 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00806 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00008000) 00807 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00808 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0x00006000) 00809 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00810 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x00004000) 00811 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00812 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00000000) 00813 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00814 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 00815 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00816 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 00817 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00818 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 00819 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00820 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 00821 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00822 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000) 00823 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00824 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0x00002000) 00825 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00826 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000) 00827 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00828 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000) 00829 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00830 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 00831 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00832 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 00833 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00834 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 00835 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00836 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00008000) 00837 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00838 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 00839 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00840 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 00841 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00842 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 00843 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00844 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 00845 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00846 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 00847 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00848 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 00849 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00850 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 00851 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00852 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 00853 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00854 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 00855 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00856 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 00857 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00858 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 00859 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00860 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 00861 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00862 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 00863 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00864 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 00865 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00866 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 00867 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 00868 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 00869 #elif defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DN128VFT5) || \ 00870 defined(CPU_MK20DN128VLF5) 00871 /* @brief Is of type FTFA. */ 00872 #define FSL_FEATURE_FLASH_IS_FTFA (0) 00873 /* @brief Is of type FTFE. */ 00874 #define FSL_FEATURE_FLASH_IS_FTFE (0) 00875 /* @brief Is of type FTFL. */ 00876 #define FSL_FEATURE_FLASH_IS_FTFL (1) 00877 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 00878 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 00879 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 00880 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 00881 /* @brief Has EEPROM region protection (register FEPROT). */ 00882 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 00883 /* @brief Has data flash region protection (register FDPROT). */ 00884 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 00885 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 00886 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 00887 /* @brief Has flash cache control in FMC module. */ 00888 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 00889 /* @brief Has flash cache control in MCM module. */ 00890 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 00891 /* @brief P-Flash start address. */ 00892 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 00893 /* @brief P-Flash block count. */ 00894 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 00895 /* @brief P-Flash block size. */ 00896 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) 00897 /* @brief P-Flash sector size. */ 00898 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 00899 /* @brief P-Flash write unit size. */ 00900 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 00901 /* @brief P-Flash data path width. */ 00902 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 00903 /* @brief P-Flash block swap feature. */ 00904 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 00905 /* @brief Has FlexNVM memory. */ 00906 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 00907 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 00908 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 00909 /* @brief FlexNVM block count. */ 00910 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 00911 /* @brief FlexNVM block size. */ 00912 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 00913 /* @brief FlexNVM sector size. */ 00914 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 00915 /* @brief FlexNVM write unit size. */ 00916 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 00917 /* @brief FlexNVM data path width. */ 00918 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 00919 /* @brief Has FlexRAM memory. */ 00920 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 00921 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 00922 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 00923 /* @brief FlexRAM size. */ 00924 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) 00925 /* @brief Has 0x00 Read 1s Block command. */ 00926 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 00927 /* @brief Has 0x01 Read 1s Section command. */ 00928 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 00929 /* @brief Has 0x02 Program Check command. */ 00930 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 00931 /* @brief Has 0x03 Read Resource command. */ 00932 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 00933 /* @brief Has 0x06 Program Longword command. */ 00934 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 00935 /* @brief Has 0x07 Program Phrase command. */ 00936 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 00937 /* @brief Has 0x08 Erase Flash Block command. */ 00938 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 00939 /* @brief Has 0x09 Erase Flash Sector command. */ 00940 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 00941 /* @brief Has 0x0B Program Section command. */ 00942 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 00943 /* @brief Has 0x40 Read 1s All Blocks command. */ 00944 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) 00945 /* @brief Has 0x41 Read Once command. */ 00946 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 00947 /* @brief Has 0x43 Program Once command. */ 00948 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 00949 /* @brief Has 0x44 Erase All Blocks command. */ 00950 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) 00951 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 00952 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 00953 /* @brief Has 0x46 Swap Control command. */ 00954 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 00955 /* @brief Has 0x80 Program Partition command. */ 00956 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 00957 /* @brief Has 0x81 Set FlexRAM Function command. */ 00958 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 00959 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 00960 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 00961 /* @brief P-Flash Erase sector command address alignment. */ 00962 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 00963 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 00964 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 00965 /* @brief P-Flash Read resource command address alignment. */ 00966 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 00967 /* @brief P-Flash Program check command address alignment. */ 00968 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 00969 /* @brief P-Flash Program check command address alignment. */ 00970 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 00971 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 00972 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 00973 /* @brief FlexNVM Erase sector command address alignment. */ 00974 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 00975 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 00976 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 00977 /* @brief FlexNVM Read resource command address alignment. */ 00978 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 00979 /* @brief FlexNVM Program check command address alignment. */ 00980 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 00981 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00982 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 00983 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00984 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 00985 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00986 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 00987 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00988 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 00989 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00990 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 00991 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00992 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 00993 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00994 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 00995 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00996 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 00997 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 00998 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 00999 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01000 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 01001 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01002 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 01003 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01004 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 01005 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01006 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 01007 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01008 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 01009 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01010 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 01011 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01012 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 01013 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01014 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 01015 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01016 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 01017 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01018 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 01019 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01020 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 01021 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01022 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 01023 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01024 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 01025 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01026 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 01027 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01028 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 01029 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01030 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 01031 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01032 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 01033 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01034 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 01035 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01036 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 01037 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01038 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 01039 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01040 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 01041 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01042 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 01043 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01044 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 01045 #elif defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DX64VFT5) || \ 01046 defined(CPU_MK20DX64VLF5) 01047 /* @brief Is of type FTFA. */ 01048 #define FSL_FEATURE_FLASH_IS_FTFA (0) 01049 /* @brief Is of type FTFE. */ 01050 #define FSL_FEATURE_FLASH_IS_FTFE (0) 01051 /* @brief Is of type FTFL. */ 01052 #define FSL_FEATURE_FLASH_IS_FTFL (1) 01053 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 01054 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 01055 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 01056 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 01057 /* @brief Has EEPROM region protection (register FEPROT). */ 01058 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 01059 /* @brief Has data flash region protection (register FDPROT). */ 01060 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 01061 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 01062 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 01063 /* @brief Has flash cache control in FMC module. */ 01064 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 01065 /* @brief Has flash cache control in MCM module. */ 01066 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 01067 /* @brief P-Flash start address. */ 01068 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 01069 /* @brief P-Flash block count. */ 01070 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 01071 /* @brief P-Flash block size. */ 01072 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) 01073 /* @brief P-Flash sector size. */ 01074 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 01075 /* @brief P-Flash write unit size. */ 01076 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 01077 /* @brief P-Flash data path width. */ 01078 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 01079 /* @brief P-Flash block swap feature. */ 01080 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 01081 /* @brief Has FlexNVM memory. */ 01082 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) 01083 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 01084 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) 01085 /* @brief FlexNVM block count. */ 01086 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) 01087 /* @brief FlexNVM block size. */ 01088 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (32768) 01089 /* @brief FlexNVM sector size. */ 01090 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (1024) 01091 /* @brief FlexNVM write unit size. */ 01092 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (4) 01093 /* @brief FlexNVM data path width. */ 01094 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (4) 01095 /* @brief Has FlexRAM memory. */ 01096 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 01097 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 01098 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 01099 /* @brief FlexRAM size. */ 01100 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) 01101 /* @brief Has 0x00 Read 1s Block command. */ 01102 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 01103 /* @brief Has 0x01 Read 1s Section command. */ 01104 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 01105 /* @brief Has 0x02 Program Check command. */ 01106 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 01107 /* @brief Has 0x03 Read Resource command. */ 01108 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 01109 /* @brief Has 0x06 Program Longword command. */ 01110 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 01111 /* @brief Has 0x07 Program Phrase command. */ 01112 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 01113 /* @brief Has 0x08 Erase Flash Block command. */ 01114 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 01115 /* @brief Has 0x09 Erase Flash Sector command. */ 01116 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 01117 /* @brief Has 0x0B Program Section command. */ 01118 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 01119 /* @brief Has 0x40 Read 1s All Blocks command. */ 01120 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) 01121 /* @brief Has 0x41 Read Once command. */ 01122 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 01123 /* @brief Has 0x43 Program Once command. */ 01124 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 01125 /* @brief Has 0x44 Erase All Blocks command. */ 01126 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) 01127 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 01128 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 01129 /* @brief Has 0x46 Swap Control command. */ 01130 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 01131 /* @brief Has 0x80 Program Partition command. */ 01132 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) 01133 /* @brief Has 0x81 Set FlexRAM Function command. */ 01134 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) 01135 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 01136 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 01137 /* @brief P-Flash Erase sector command address alignment. */ 01138 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 01139 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 01140 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 01141 /* @brief P-Flash Read resource command address alignment. */ 01142 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 01143 /* @brief P-Flash Program check command address alignment. */ 01144 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 01145 /* @brief P-Flash Program check command address alignment. */ 01146 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 01147 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 01148 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (4) 01149 /* @brief FlexNVM Erase sector command address alignment. */ 01150 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (4) 01151 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 01152 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (4) 01153 /* @brief FlexNVM Read resource command address alignment. */ 01154 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 01155 /* @brief FlexNVM Program check command address alignment. */ 01156 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) 01157 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01158 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00008000) 01159 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01160 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0x00006000) 01161 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01162 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x00004000) 01163 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01164 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00000000) 01165 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01166 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 01167 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01168 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 01169 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01170 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 01171 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01172 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 01173 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01174 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000) 01175 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01176 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0x00002000) 01177 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01178 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000) 01179 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01180 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000) 01181 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01182 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 01183 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01184 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 01185 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01186 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 01187 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01188 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00008000) 01189 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01190 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 01191 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01192 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 01193 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01194 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 01195 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01196 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 01197 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01198 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 01199 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01200 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 01201 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01202 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 01203 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01204 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 01205 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01206 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 01207 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01208 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 01209 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01210 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 01211 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01212 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 01213 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01214 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 01215 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01216 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 01217 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01218 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 01219 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01220 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 01221 #elif defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DN64VFT5) || \ 01222 defined(CPU_MK20DN64VLF5) 01223 /* @brief Is of type FTFA. */ 01224 #define FSL_FEATURE_FLASH_IS_FTFA (0) 01225 /* @brief Is of type FTFE. */ 01226 #define FSL_FEATURE_FLASH_IS_FTFE (0) 01227 /* @brief Is of type FTFL. */ 01228 #define FSL_FEATURE_FLASH_IS_FTFL (1) 01229 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 01230 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 01231 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 01232 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 01233 /* @brief Has EEPROM region protection (register FEPROT). */ 01234 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 01235 /* @brief Has data flash region protection (register FDPROT). */ 01236 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 01237 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 01238 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 01239 /* @brief Has flash cache control in FMC module. */ 01240 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 01241 /* @brief Has flash cache control in MCM module. */ 01242 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 01243 /* @brief P-Flash start address. */ 01244 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 01245 /* @brief P-Flash block count. */ 01246 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 01247 /* @brief P-Flash block size. */ 01248 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) 01249 /* @brief P-Flash sector size. */ 01250 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 01251 /* @brief P-Flash write unit size. */ 01252 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 01253 /* @brief P-Flash data path width. */ 01254 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 01255 /* @brief P-Flash block swap feature. */ 01256 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 01257 /* @brief Has FlexNVM memory. */ 01258 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 01259 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 01260 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 01261 /* @brief FlexNVM block count. */ 01262 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 01263 /* @brief FlexNVM block size. */ 01264 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 01265 /* @brief FlexNVM sector size. */ 01266 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 01267 /* @brief FlexNVM write unit size. */ 01268 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 01269 /* @brief FlexNVM data path width. */ 01270 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 01271 /* @brief Has FlexRAM memory. */ 01272 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 01273 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 01274 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 01275 /* @brief FlexRAM size. */ 01276 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) 01277 /* @brief Has 0x00 Read 1s Block command. */ 01278 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 01279 /* @brief Has 0x01 Read 1s Section command. */ 01280 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 01281 /* @brief Has 0x02 Program Check command. */ 01282 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 01283 /* @brief Has 0x03 Read Resource command. */ 01284 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 01285 /* @brief Has 0x06 Program Longword command. */ 01286 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 01287 /* @brief Has 0x07 Program Phrase command. */ 01288 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 01289 /* @brief Has 0x08 Erase Flash Block command. */ 01290 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 01291 /* @brief Has 0x09 Erase Flash Sector command. */ 01292 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 01293 /* @brief Has 0x0B Program Section command. */ 01294 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 01295 /* @brief Has 0x40 Read 1s All Blocks command. */ 01296 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) 01297 /* @brief Has 0x41 Read Once command. */ 01298 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 01299 /* @brief Has 0x43 Program Once command. */ 01300 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 01301 /* @brief Has 0x44 Erase All Blocks command. */ 01302 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) 01303 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 01304 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 01305 /* @brief Has 0x46 Swap Control command. */ 01306 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 01307 /* @brief Has 0x80 Program Partition command. */ 01308 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 01309 /* @brief Has 0x81 Set FlexRAM Function command. */ 01310 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 01311 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 01312 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 01313 /* @brief P-Flash Erase sector command address alignment. */ 01314 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 01315 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 01316 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 01317 /* @brief P-Flash Read resource command address alignment. */ 01318 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 01319 /* @brief P-Flash Program check command address alignment. */ 01320 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 01321 /* @brief P-Flash Program check command address alignment. */ 01322 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 01323 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 01324 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 01325 /* @brief FlexNVM Erase sector command address alignment. */ 01326 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 01327 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 01328 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 01329 /* @brief FlexNVM Read resource command address alignment. */ 01330 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 01331 /* @brief FlexNVM Program check command address alignment. */ 01332 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 01333 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01334 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 01335 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01336 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 01337 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01338 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 01339 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01340 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 01341 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01342 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 01343 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01344 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 01345 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01346 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 01347 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01348 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 01349 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01350 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 01351 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01352 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 01353 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01354 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 01355 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01356 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 01357 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01358 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 01359 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01360 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 01361 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01362 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 01363 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01364 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 01365 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01366 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 01367 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01368 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 01369 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01370 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 01371 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01372 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 01373 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01374 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 01375 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01376 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 01377 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01378 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 01379 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01380 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 01381 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01382 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 01383 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01384 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 01385 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01386 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 01387 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01388 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 01389 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01390 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 01391 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01392 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 01393 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01394 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 01395 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01396 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 01397 #elif defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DX32VFT5) || \ 01398 defined(CPU_MK20DX32VLF5) 01399 /* @brief Is of type FTFA. */ 01400 #define FSL_FEATURE_FLASH_IS_FTFA (0) 01401 /* @brief Is of type FTFE. */ 01402 #define FSL_FEATURE_FLASH_IS_FTFE (0) 01403 /* @brief Is of type FTFL. */ 01404 #define FSL_FEATURE_FLASH_IS_FTFL (1) 01405 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 01406 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 01407 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 01408 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 01409 /* @brief Has EEPROM region protection (register FEPROT). */ 01410 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 01411 /* @brief Has data flash region protection (register FDPROT). */ 01412 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 01413 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 01414 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 01415 /* @brief Has flash cache control in FMC module. */ 01416 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 01417 /* @brief Has flash cache control in MCM module. */ 01418 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 01419 /* @brief P-Flash start address. */ 01420 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 01421 /* @brief P-Flash block count. */ 01422 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 01423 /* @brief P-Flash block size. */ 01424 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) 01425 /* @brief P-Flash sector size. */ 01426 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 01427 /* @brief P-Flash write unit size. */ 01428 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 01429 /* @brief P-Flash data path width. */ 01430 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 01431 /* @brief P-Flash block swap feature. */ 01432 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 01433 /* @brief Has FlexNVM memory. */ 01434 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) 01435 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 01436 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) 01437 /* @brief FlexNVM block count. */ 01438 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) 01439 /* @brief FlexNVM block size. */ 01440 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (32768) 01441 /* @brief FlexNVM sector size. */ 01442 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (1024) 01443 /* @brief FlexNVM write unit size. */ 01444 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (4) 01445 /* @brief FlexNVM data path width. */ 01446 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (4) 01447 /* @brief Has FlexRAM memory. */ 01448 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 01449 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 01450 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 01451 /* @brief FlexRAM size. */ 01452 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) 01453 /* @brief Has 0x00 Read 1s Block command. */ 01454 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 01455 /* @brief Has 0x01 Read 1s Section command. */ 01456 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 01457 /* @brief Has 0x02 Program Check command. */ 01458 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 01459 /* @brief Has 0x03 Read Resource command. */ 01460 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 01461 /* @brief Has 0x06 Program Longword command. */ 01462 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 01463 /* @brief Has 0x07 Program Phrase command. */ 01464 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 01465 /* @brief Has 0x08 Erase Flash Block command. */ 01466 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 01467 /* @brief Has 0x09 Erase Flash Sector command. */ 01468 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 01469 /* @brief Has 0x0B Program Section command. */ 01470 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 01471 /* @brief Has 0x40 Read 1s All Blocks command. */ 01472 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) 01473 /* @brief Has 0x41 Read Once command. */ 01474 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 01475 /* @brief Has 0x43 Program Once command. */ 01476 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 01477 /* @brief Has 0x44 Erase All Blocks command. */ 01478 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) 01479 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 01480 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 01481 /* @brief Has 0x46 Swap Control command. */ 01482 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 01483 /* @brief Has 0x80 Program Partition command. */ 01484 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) 01485 /* @brief Has 0x81 Set FlexRAM Function command. */ 01486 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) 01487 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 01488 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 01489 /* @brief P-Flash Erase sector command address alignment. */ 01490 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 01491 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 01492 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 01493 /* @brief P-Flash Read resource command address alignment. */ 01494 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 01495 /* @brief P-Flash Program check command address alignment. */ 01496 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 01497 /* @brief P-Flash Program check command address alignment. */ 01498 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 01499 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 01500 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (4) 01501 /* @brief FlexNVM Erase sector command address alignment. */ 01502 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (4) 01503 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 01504 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (4) 01505 /* @brief FlexNVM Read resource command address alignment. */ 01506 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 01507 /* @brief FlexNVM Program check command address alignment. */ 01508 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) 01509 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01510 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00008000) 01511 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01512 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0x00006000) 01513 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01514 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x00004000) 01515 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01516 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00000000) 01517 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01518 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 01519 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01520 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 01521 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01522 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 01523 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01524 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 01525 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01526 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000) 01527 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01528 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0x00002000) 01529 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01530 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000) 01531 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01532 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000) 01533 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01534 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 01535 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01536 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 01537 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01538 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 01539 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01540 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00008000) 01541 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01542 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 01543 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01544 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 01545 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01546 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 01547 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01548 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 01549 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01550 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 01551 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01552 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 01553 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01554 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 01555 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01556 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 01557 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01558 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 01559 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01560 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 01561 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01562 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 01563 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01564 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 01565 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01566 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 01567 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01568 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 01569 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01570 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 01571 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01572 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 01573 #elif defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DN32VFT5) || \ 01574 defined(CPU_MK20DN32VLF5) 01575 /* @brief Is of type FTFA. */ 01576 #define FSL_FEATURE_FLASH_IS_FTFA (0) 01577 /* @brief Is of type FTFE. */ 01578 #define FSL_FEATURE_FLASH_IS_FTFE (0) 01579 /* @brief Is of type FTFL. */ 01580 #define FSL_FEATURE_FLASH_IS_FTFL (1) 01581 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 01582 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 01583 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 01584 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 01585 /* @brief Has EEPROM region protection (register FEPROT). */ 01586 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 01587 /* @brief Has data flash region protection (register FDPROT). */ 01588 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 01589 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 01590 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 01591 /* @brief Has flash cache control in FMC module. */ 01592 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 01593 /* @brief Has flash cache control in MCM module. */ 01594 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 01595 /* @brief P-Flash start address. */ 01596 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 01597 /* @brief P-Flash block count. */ 01598 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 01599 /* @brief P-Flash block size. */ 01600 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) 01601 /* @brief P-Flash sector size. */ 01602 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 01603 /* @brief P-Flash write unit size. */ 01604 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 01605 /* @brief P-Flash data path width. */ 01606 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 01607 /* @brief P-Flash block swap feature. */ 01608 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 01609 /* @brief Has FlexNVM memory. */ 01610 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 01611 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 01612 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 01613 /* @brief FlexNVM block count. */ 01614 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 01615 /* @brief FlexNVM block size. */ 01616 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 01617 /* @brief FlexNVM sector size. */ 01618 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 01619 /* @brief FlexNVM write unit size. */ 01620 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 01621 /* @brief FlexNVM data path width. */ 01622 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 01623 /* @brief Has FlexRAM memory. */ 01624 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 01625 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 01626 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 01627 /* @brief FlexRAM size. */ 01628 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) 01629 /* @brief Has 0x00 Read 1s Block command. */ 01630 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 01631 /* @brief Has 0x01 Read 1s Section command. */ 01632 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 01633 /* @brief Has 0x02 Program Check command. */ 01634 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 01635 /* @brief Has 0x03 Read Resource command. */ 01636 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 01637 /* @brief Has 0x06 Program Longword command. */ 01638 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 01639 /* @brief Has 0x07 Program Phrase command. */ 01640 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 01641 /* @brief Has 0x08 Erase Flash Block command. */ 01642 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 01643 /* @brief Has 0x09 Erase Flash Sector command. */ 01644 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 01645 /* @brief Has 0x0B Program Section command. */ 01646 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 01647 /* @brief Has 0x40 Read 1s All Blocks command. */ 01648 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) 01649 /* @brief Has 0x41 Read Once command. */ 01650 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 01651 /* @brief Has 0x43 Program Once command. */ 01652 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 01653 /* @brief Has 0x44 Erase All Blocks command. */ 01654 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) 01655 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 01656 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 01657 /* @brief Has 0x46 Swap Control command. */ 01658 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 01659 /* @brief Has 0x80 Program Partition command. */ 01660 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 01661 /* @brief Has 0x81 Set FlexRAM Function command. */ 01662 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 01663 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 01664 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 01665 /* @brief P-Flash Erase sector command address alignment. */ 01666 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 01667 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 01668 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 01669 /* @brief P-Flash Read resource command address alignment. */ 01670 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 01671 /* @brief P-Flash Program check command address alignment. */ 01672 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 01673 /* @brief P-Flash Program check command address alignment. */ 01674 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 01675 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 01676 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 01677 /* @brief FlexNVM Erase sector command address alignment. */ 01678 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 01679 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 01680 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 01681 /* @brief FlexNVM Read resource command address alignment. */ 01682 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 01683 /* @brief FlexNVM Program check command address alignment. */ 01684 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 01685 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01686 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 01687 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01688 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 01689 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01690 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 01691 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01692 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 01693 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01694 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 01695 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01696 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 01697 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01698 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 01699 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01700 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 01701 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01702 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 01703 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01704 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 01705 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01706 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 01707 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01708 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 01709 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01710 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 01711 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01712 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 01713 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01714 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 01715 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 01716 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 01717 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01718 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 01719 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01720 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 01721 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01722 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 01723 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01724 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 01725 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01726 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 01727 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01728 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 01729 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01730 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 01731 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01732 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 01733 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01734 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 01735 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01736 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 01737 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01738 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 01739 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01740 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 01741 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01742 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 01743 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01744 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 01745 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01746 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 01747 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 01748 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 01749 #endif /* defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DX128VFT5) || \ 01750 defined(CPU_MK20DX128VLF5) */ 01751 01752 /* FTM module features */ 01753 01754 /* @brief Number of channels. */ 01755 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 01756 ((x) == FTM0 ? (8) : \ 01757 ((x) == FTM1 ? (2) : (-1))) 01758 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 01759 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 01760 /* @brief Enable pwm output for the module. */ 01761 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 01762 /* @brief Has half-cycle reload for the module. */ 01763 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 01764 /* @brief Has reload interrupt. */ 01765 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 01766 /* @brief Has reload initialization trigger. */ 01767 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 01768 01769 /* I2C module features */ 01770 01771 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 01772 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 01773 /* @brief Maximum supported baud rate in kilobit per second. */ 01774 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 01775 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 01776 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 01777 /* @brief Has DMA support (register bit C1[DMAEN]). */ 01778 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 01779 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 01780 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (0) 01781 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 01782 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 01783 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 01784 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (0) 01785 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 01786 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) 01787 /* @brief Has control of the drive capability of the I2C pins. */ 01788 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 01789 /* @brief Has double buffering support (register S2). */ 01790 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 01791 01792 /* SAI module features */ 01793 01794 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 01795 #define FSL_FEATURE_SAI_FIFO_COUNT (8) 01796 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 01797 #define FSL_FEATURE_SAI_CHANNEL_COUNT (2) 01798 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 01799 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 01800 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 01801 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) 01802 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 01803 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) 01804 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 01805 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) 01806 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 01807 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) 01808 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 01809 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 01810 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 01811 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) 01812 /* @brief Ihe interrupt source number */ 01813 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) 01814 /* @brief Has register of MCR. */ 01815 #define FSL_FEATURE_SAI_HAS_MCR (1) 01816 /* @brief Has register of MDR */ 01817 #define FSL_FEATURE_SAI_HAS_MDR (1) 01818 01819 /* LLWU module features */ 01820 01821 #if defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ 01822 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) 01823 /* @brief Maximum number of pins connected to LLWU device. */ 01824 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 01825 /* @brief Has pins 8-15 connected to LLWU device. */ 01826 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 01827 /* @brief Maximum number of internal modules connected to LLWU device. */ 01828 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 01829 /* @brief Number of digital filters. */ 01830 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 01831 /* @brief Has MF5 register. */ 01832 #define FSL_FEATURE_LLWU_HAS_MF (0) 01833 /* @brief Has PF register. */ 01834 #define FSL_FEATURE_LLWU_HAS_PF (0) 01835 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 01836 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) 01837 /* @brief Has external pin 0 connected to LLWU device. */ 01838 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) 01839 /* @brief Index of port of external pin. */ 01840 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) 01841 /* @brief Number of external pin port on specified port. */ 01842 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) 01843 /* @brief Has external pin 1 connected to LLWU device. */ 01844 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 01845 /* @brief Index of port of external pin. */ 01846 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 01847 /* @brief Number of external pin port on specified port. */ 01848 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 01849 /* @brief Has external pin 2 connected to LLWU device. */ 01850 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 01851 /* @brief Index of port of external pin. */ 01852 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 01853 /* @brief Number of external pin port on specified port. */ 01854 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 01855 /* @brief Has external pin 3 connected to LLWU device. */ 01856 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 01857 /* @brief Index of port of external pin. */ 01858 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 01859 /* @brief Number of external pin port on specified port. */ 01860 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 01861 /* @brief Has external pin 4 connected to LLWU device. */ 01862 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) 01863 /* @brief Index of port of external pin. */ 01864 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) 01865 /* @brief Number of external pin port on specified port. */ 01866 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 01867 /* @brief Has external pin 5 connected to LLWU device. */ 01868 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 01869 /* @brief Index of port of external pin. */ 01870 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 01871 /* @brief Number of external pin port on specified port. */ 01872 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 01873 /* @brief Has external pin 6 connected to LLWU device. */ 01874 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 01875 /* @brief Index of port of external pin. */ 01876 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 01877 /* @brief Number of external pin port on specified port. */ 01878 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 01879 /* @brief Has external pin 7 connected to LLWU device. */ 01880 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 01881 /* @brief Index of port of external pin. */ 01882 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 01883 /* @brief Number of external pin port on specified port. */ 01884 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 01885 /* @brief Has external pin 8 connected to LLWU device. */ 01886 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 01887 /* @brief Index of port of external pin. */ 01888 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 01889 /* @brief Number of external pin port on specified port. */ 01890 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 01891 /* @brief Has external pin 9 connected to LLWU device. */ 01892 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 01893 /* @brief Index of port of external pin. */ 01894 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 01895 /* @brief Number of external pin port on specified port. */ 01896 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 01897 /* @brief Has external pin 10 connected to LLWU device. */ 01898 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 01899 /* @brief Index of port of external pin. */ 01900 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 01901 /* @brief Number of external pin port on specified port. */ 01902 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 01903 /* @brief Has external pin 11 connected to LLWU device. */ 01904 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) 01905 /* @brief Index of port of external pin. */ 01906 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) 01907 /* @brief Number of external pin port on specified port. */ 01908 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 01909 /* @brief Has external pin 12 connected to LLWU device. */ 01910 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) 01911 /* @brief Index of port of external pin. */ 01912 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) 01913 /* @brief Number of external pin port on specified port. */ 01914 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 01915 /* @brief Has external pin 13 connected to LLWU device. */ 01916 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0) 01917 /* @brief Index of port of external pin. */ 01918 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0) 01919 /* @brief Number of external pin port on specified port. */ 01920 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0) 01921 /* @brief Has external pin 14 connected to LLWU device. */ 01922 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 01923 /* @brief Index of port of external pin. */ 01924 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 01925 /* @brief Number of external pin port on specified port. */ 01926 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 01927 /* @brief Has external pin 15 connected to LLWU device. */ 01928 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 01929 /* @brief Index of port of external pin. */ 01930 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 01931 /* @brief Number of external pin port on specified port. */ 01932 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 01933 /* @brief Has external pin 16 connected to LLWU device. */ 01934 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 01935 /* @brief Index of port of external pin. */ 01936 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 01937 /* @brief Number of external pin port on specified port. */ 01938 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 01939 /* @brief Has external pin 17 connected to LLWU device. */ 01940 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 01941 /* @brief Index of port of external pin. */ 01942 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 01943 /* @brief Number of external pin port on specified port. */ 01944 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 01945 /* @brief Has external pin 18 connected to LLWU device. */ 01946 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 01947 /* @brief Index of port of external pin. */ 01948 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 01949 /* @brief Number of external pin port on specified port. */ 01950 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 01951 /* @brief Has external pin 19 connected to LLWU device. */ 01952 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 01953 /* @brief Index of port of external pin. */ 01954 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 01955 /* @brief Number of external pin port on specified port. */ 01956 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 01957 /* @brief Has external pin 20 connected to LLWU device. */ 01958 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 01959 /* @brief Index of port of external pin. */ 01960 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 01961 /* @brief Number of external pin port on specified port. */ 01962 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 01963 /* @brief Has external pin 21 connected to LLWU device. */ 01964 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 01965 /* @brief Index of port of external pin. */ 01966 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 01967 /* @brief Number of external pin port on specified port. */ 01968 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 01969 /* @brief Has external pin 22 connected to LLWU device. */ 01970 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 01971 /* @brief Index of port of external pin. */ 01972 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 01973 /* @brief Number of external pin port on specified port. */ 01974 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 01975 /* @brief Has external pin 23 connected to LLWU device. */ 01976 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 01977 /* @brief Index of port of external pin. */ 01978 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 01979 /* @brief Number of external pin port on specified port. */ 01980 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 01981 /* @brief Has external pin 24 connected to LLWU device. */ 01982 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 01983 /* @brief Index of port of external pin. */ 01984 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 01985 /* @brief Number of external pin port on specified port. */ 01986 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 01987 /* @brief Has external pin 25 connected to LLWU device. */ 01988 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 01989 /* @brief Index of port of external pin. */ 01990 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 01991 /* @brief Number of external pin port on specified port. */ 01992 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 01993 /* @brief Has external pin 26 connected to LLWU device. */ 01994 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 01995 /* @brief Index of port of external pin. */ 01996 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 01997 /* @brief Number of external pin port on specified port. */ 01998 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 01999 /* @brief Has external pin 27 connected to LLWU device. */ 02000 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 02001 /* @brief Index of port of external pin. */ 02002 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 02003 /* @brief Number of external pin port on specified port. */ 02004 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 02005 /* @brief Has external pin 28 connected to LLWU device. */ 02006 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 02007 /* @brief Index of port of external pin. */ 02008 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 02009 /* @brief Number of external pin port on specified port. */ 02010 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 02011 /* @brief Has external pin 29 connected to LLWU device. */ 02012 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 02013 /* @brief Index of port of external pin. */ 02014 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 02015 /* @brief Number of external pin port on specified port. */ 02016 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 02017 /* @brief Has external pin 30 connected to LLWU device. */ 02018 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 02019 /* @brief Index of port of external pin. */ 02020 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 02021 /* @brief Number of external pin port on specified port. */ 02022 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 02023 /* @brief Has external pin 31 connected to LLWU device. */ 02024 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 02025 /* @brief Index of port of external pin. */ 02026 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 02027 /* @brief Number of external pin port on specified port. */ 02028 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 02029 /* @brief Has internal module 0 connected to LLWU device. */ 02030 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 02031 /* @brief Has internal module 1 connected to LLWU device. */ 02032 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 02033 /* @brief Has internal module 2 connected to LLWU device. */ 02034 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 02035 /* @brief Has internal module 3 connected to LLWU device. */ 02036 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 02037 /* @brief Has internal module 4 connected to LLWU device. */ 02038 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 02039 /* @brief Has internal module 5 connected to LLWU device. */ 02040 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 02041 /* @brief Has internal module 6 connected to LLWU device. */ 02042 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 02043 /* @brief Has internal module 7 connected to LLWU device. */ 02044 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 02045 /* @brief Has Version ID Register (LLWU_VERID). */ 02046 #define FSL_FEATURE_LLWU_HAS_VERID (0) 02047 /* @brief Has Parameter Register (LLWU_PARAM). */ 02048 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 02049 /* @brief Width of registers of the LLWU. */ 02050 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 02051 /* @brief Has DMA Enable register (LLWU_DE). */ 02052 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 02053 #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ 02054 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ 02055 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) 02056 /* @brief Maximum number of pins connected to LLWU device. */ 02057 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 02058 /* @brief Has pins 8-15 connected to LLWU device. */ 02059 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 02060 /* @brief Maximum number of internal modules connected to LLWU device. */ 02061 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 02062 /* @brief Number of digital filters. */ 02063 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 02064 /* @brief Has MF5 register. */ 02065 #define FSL_FEATURE_LLWU_HAS_MF (0) 02066 /* @brief Has PF register. */ 02067 #define FSL_FEATURE_LLWU_HAS_PF (0) 02068 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 02069 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) 02070 /* @brief Has external pin 0 connected to LLWU device. */ 02071 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 02072 /* @brief Index of port of external pin. */ 02073 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 02074 /* @brief Number of external pin port on specified port. */ 02075 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 02076 /* @brief Has external pin 1 connected to LLWU device. */ 02077 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 02078 /* @brief Index of port of external pin. */ 02079 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 02080 /* @brief Number of external pin port on specified port. */ 02081 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 02082 /* @brief Has external pin 2 connected to LLWU device. */ 02083 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 02084 /* @brief Index of port of external pin. */ 02085 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 02086 /* @brief Number of external pin port on specified port. */ 02087 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 02088 /* @brief Has external pin 3 connected to LLWU device. */ 02089 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 02090 /* @brief Index of port of external pin. */ 02091 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 02092 /* @brief Number of external pin port on specified port. */ 02093 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 02094 /* @brief Has external pin 4 connected to LLWU device. */ 02095 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 02096 /* @brief Index of port of external pin. */ 02097 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 02098 /* @brief Number of external pin port on specified port. */ 02099 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 02100 /* @brief Has external pin 5 connected to LLWU device. */ 02101 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 02102 /* @brief Index of port of external pin. */ 02103 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 02104 /* @brief Number of external pin port on specified port. */ 02105 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 02106 /* @brief Has external pin 6 connected to LLWU device. */ 02107 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 02108 /* @brief Index of port of external pin. */ 02109 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 02110 /* @brief Number of external pin port on specified port. */ 02111 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 02112 /* @brief Has external pin 7 connected to LLWU device. */ 02113 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 02114 /* @brief Index of port of external pin. */ 02115 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 02116 /* @brief Number of external pin port on specified port. */ 02117 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 02118 /* @brief Has external pin 8 connected to LLWU device. */ 02119 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 02120 /* @brief Index of port of external pin. */ 02121 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 02122 /* @brief Number of external pin port on specified port. */ 02123 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 02124 /* @brief Has external pin 9 connected to LLWU device. */ 02125 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 02126 /* @brief Index of port of external pin. */ 02127 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 02128 /* @brief Number of external pin port on specified port. */ 02129 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 02130 /* @brief Has external pin 10 connected to LLWU device. */ 02131 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 02132 /* @brief Index of port of external pin. */ 02133 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 02134 /* @brief Number of external pin port on specified port. */ 02135 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 02136 /* @brief Has external pin 11 connected to LLWU device. */ 02137 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 02138 /* @brief Index of port of external pin. */ 02139 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 02140 /* @brief Number of external pin port on specified port. */ 02141 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 02142 /* @brief Has external pin 12 connected to LLWU device. */ 02143 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 02144 /* @brief Index of port of external pin. */ 02145 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 02146 /* @brief Number of external pin port on specified port. */ 02147 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 02148 /* @brief Has external pin 13 connected to LLWU device. */ 02149 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 02150 /* @brief Index of port of external pin. */ 02151 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 02152 /* @brief Number of external pin port on specified port. */ 02153 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 02154 /* @brief Has external pin 14 connected to LLWU device. */ 02155 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 02156 /* @brief Index of port of external pin. */ 02157 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 02158 /* @brief Number of external pin port on specified port. */ 02159 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 02160 /* @brief Has external pin 15 connected to LLWU device. */ 02161 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 02162 /* @brief Index of port of external pin. */ 02163 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 02164 /* @brief Number of external pin port on specified port. */ 02165 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 02166 /* @brief Has external pin 16 connected to LLWU device. */ 02167 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 02168 /* @brief Index of port of external pin. */ 02169 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 02170 /* @brief Number of external pin port on specified port. */ 02171 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 02172 /* @brief Has external pin 17 connected to LLWU device. */ 02173 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 02174 /* @brief Index of port of external pin. */ 02175 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 02176 /* @brief Number of external pin port on specified port. */ 02177 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 02178 /* @brief Has external pin 18 connected to LLWU device. */ 02179 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 02180 /* @brief Index of port of external pin. */ 02181 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 02182 /* @brief Number of external pin port on specified port. */ 02183 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 02184 /* @brief Has external pin 19 connected to LLWU device. */ 02185 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 02186 /* @brief Index of port of external pin. */ 02187 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 02188 /* @brief Number of external pin port on specified port. */ 02189 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 02190 /* @brief Has external pin 20 connected to LLWU device. */ 02191 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 02192 /* @brief Index of port of external pin. */ 02193 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 02194 /* @brief Number of external pin port on specified port. */ 02195 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 02196 /* @brief Has external pin 21 connected to LLWU device. */ 02197 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 02198 /* @brief Index of port of external pin. */ 02199 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 02200 /* @brief Number of external pin port on specified port. */ 02201 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 02202 /* @brief Has external pin 22 connected to LLWU device. */ 02203 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 02204 /* @brief Index of port of external pin. */ 02205 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 02206 /* @brief Number of external pin port on specified port. */ 02207 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 02208 /* @brief Has external pin 23 connected to LLWU device. */ 02209 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 02210 /* @brief Index of port of external pin. */ 02211 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 02212 /* @brief Number of external pin port on specified port. */ 02213 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 02214 /* @brief Has external pin 24 connected to LLWU device. */ 02215 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 02216 /* @brief Index of port of external pin. */ 02217 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 02218 /* @brief Number of external pin port on specified port. */ 02219 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 02220 /* @brief Has external pin 25 connected to LLWU device. */ 02221 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 02222 /* @brief Index of port of external pin. */ 02223 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 02224 /* @brief Number of external pin port on specified port. */ 02225 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 02226 /* @brief Has external pin 26 connected to LLWU device. */ 02227 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 02228 /* @brief Index of port of external pin. */ 02229 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 02230 /* @brief Number of external pin port on specified port. */ 02231 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 02232 /* @brief Has external pin 27 connected to LLWU device. */ 02233 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 02234 /* @brief Index of port of external pin. */ 02235 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 02236 /* @brief Number of external pin port on specified port. */ 02237 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 02238 /* @brief Has external pin 28 connected to LLWU device. */ 02239 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 02240 /* @brief Index of port of external pin. */ 02241 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 02242 /* @brief Number of external pin port on specified port. */ 02243 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 02244 /* @brief Has external pin 29 connected to LLWU device. */ 02245 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 02246 /* @brief Index of port of external pin. */ 02247 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 02248 /* @brief Number of external pin port on specified port. */ 02249 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 02250 /* @brief Has external pin 30 connected to LLWU device. */ 02251 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 02252 /* @brief Index of port of external pin. */ 02253 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 02254 /* @brief Number of external pin port on specified port. */ 02255 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 02256 /* @brief Has external pin 31 connected to LLWU device. */ 02257 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 02258 /* @brief Index of port of external pin. */ 02259 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 02260 /* @brief Number of external pin port on specified port. */ 02261 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 02262 /* @brief Has internal module 0 connected to LLWU device. */ 02263 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 02264 /* @brief Has internal module 1 connected to LLWU device. */ 02265 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 02266 /* @brief Has internal module 2 connected to LLWU device. */ 02267 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 02268 /* @brief Has internal module 3 connected to LLWU device. */ 02269 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 02270 /* @brief Has internal module 4 connected to LLWU device. */ 02271 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 02272 /* @brief Has internal module 5 connected to LLWU device. */ 02273 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 02274 /* @brief Has internal module 6 connected to LLWU device. */ 02275 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 02276 /* @brief Has internal module 7 connected to LLWU device. */ 02277 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 02278 /* @brief Has Version ID Register (LLWU_VERID). */ 02279 #define FSL_FEATURE_LLWU_HAS_VERID (0) 02280 /* @brief Has Parameter Register (LLWU_PARAM). */ 02281 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 02282 /* @brief Width of registers of the LLWU. */ 02283 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 02284 /* @brief Has DMA Enable register (LLWU_DE). */ 02285 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 02286 #elif defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ 02287 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ 02288 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) 02289 /* @brief Maximum number of pins connected to LLWU device. */ 02290 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 02291 /* @brief Has pins 8-15 connected to LLWU device. */ 02292 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 02293 /* @brief Maximum number of internal modules connected to LLWU device. */ 02294 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 02295 /* @brief Number of digital filters. */ 02296 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 02297 /* @brief Has MF5 register. */ 02298 #define FSL_FEATURE_LLWU_HAS_MF (0) 02299 /* @brief Has PF register. */ 02300 #define FSL_FEATURE_LLWU_HAS_PF (0) 02301 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 02302 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) 02303 /* @brief Has external pin 0 connected to LLWU device. */ 02304 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) 02305 /* @brief Index of port of external pin. */ 02306 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) 02307 /* @brief Number of external pin port on specified port. */ 02308 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) 02309 /* @brief Has external pin 1 connected to LLWU device. */ 02310 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 02311 /* @brief Index of port of external pin. */ 02312 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 02313 /* @brief Number of external pin port on specified port. */ 02314 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 02315 /* @brief Has external pin 2 connected to LLWU device. */ 02316 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 02317 /* @brief Index of port of external pin. */ 02318 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 02319 /* @brief Number of external pin port on specified port. */ 02320 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 02321 /* @brief Has external pin 3 connected to LLWU device. */ 02322 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 02323 /* @brief Index of port of external pin. */ 02324 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 02325 /* @brief Number of external pin port on specified port. */ 02326 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 02327 /* @brief Has external pin 4 connected to LLWU device. */ 02328 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) 02329 /* @brief Index of port of external pin. */ 02330 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) 02331 /* @brief Number of external pin port on specified port. */ 02332 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 02333 /* @brief Has external pin 5 connected to LLWU device. */ 02334 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 02335 /* @brief Index of port of external pin. */ 02336 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 02337 /* @brief Number of external pin port on specified port. */ 02338 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 02339 /* @brief Has external pin 6 connected to LLWU device. */ 02340 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 02341 /* @brief Index of port of external pin. */ 02342 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 02343 /* @brief Number of external pin port on specified port. */ 02344 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 02345 /* @brief Has external pin 7 connected to LLWU device. */ 02346 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 02347 /* @brief Index of port of external pin. */ 02348 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 02349 /* @brief Number of external pin port on specified port. */ 02350 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 02351 /* @brief Has external pin 8 connected to LLWU device. */ 02352 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 02353 /* @brief Index of port of external pin. */ 02354 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 02355 /* @brief Number of external pin port on specified port. */ 02356 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 02357 /* @brief Has external pin 9 connected to LLWU device. */ 02358 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 02359 /* @brief Index of port of external pin. */ 02360 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 02361 /* @brief Number of external pin port on specified port. */ 02362 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 02363 /* @brief Has external pin 10 connected to LLWU device. */ 02364 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 02365 /* @brief Index of port of external pin. */ 02366 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 02367 /* @brief Number of external pin port on specified port. */ 02368 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 02369 /* @brief Has external pin 11 connected to LLWU device. */ 02370 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) 02371 /* @brief Index of port of external pin. */ 02372 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) 02373 /* @brief Number of external pin port on specified port. */ 02374 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 02375 /* @brief Has external pin 12 connected to LLWU device. */ 02376 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 02377 /* @brief Index of port of external pin. */ 02378 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 02379 /* @brief Number of external pin port on specified port. */ 02380 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 02381 /* @brief Has external pin 13 connected to LLWU device. */ 02382 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 02383 /* @brief Index of port of external pin. */ 02384 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 02385 /* @brief Number of external pin port on specified port. */ 02386 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 02387 /* @brief Has external pin 14 connected to LLWU device. */ 02388 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 02389 /* @brief Index of port of external pin. */ 02390 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 02391 /* @brief Number of external pin port on specified port. */ 02392 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 02393 /* @brief Has external pin 15 connected to LLWU device. */ 02394 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 02395 /* @brief Index of port of external pin. */ 02396 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 02397 /* @brief Number of external pin port on specified port. */ 02398 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 02399 /* @brief Has external pin 16 connected to LLWU device. */ 02400 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 02401 /* @brief Index of port of external pin. */ 02402 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 02403 /* @brief Number of external pin port on specified port. */ 02404 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 02405 /* @brief Has external pin 17 connected to LLWU device. */ 02406 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 02407 /* @brief Index of port of external pin. */ 02408 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 02409 /* @brief Number of external pin port on specified port. */ 02410 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 02411 /* @brief Has external pin 18 connected to LLWU device. */ 02412 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 02413 /* @brief Index of port of external pin. */ 02414 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 02415 /* @brief Number of external pin port on specified port. */ 02416 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 02417 /* @brief Has external pin 19 connected to LLWU device. */ 02418 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 02419 /* @brief Index of port of external pin. */ 02420 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 02421 /* @brief Number of external pin port on specified port. */ 02422 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 02423 /* @brief Has external pin 20 connected to LLWU device. */ 02424 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 02425 /* @brief Index of port of external pin. */ 02426 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 02427 /* @brief Number of external pin port on specified port. */ 02428 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 02429 /* @brief Has external pin 21 connected to LLWU device. */ 02430 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 02431 /* @brief Index of port of external pin. */ 02432 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 02433 /* @brief Number of external pin port on specified port. */ 02434 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 02435 /* @brief Has external pin 22 connected to LLWU device. */ 02436 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 02437 /* @brief Index of port of external pin. */ 02438 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 02439 /* @brief Number of external pin port on specified port. */ 02440 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 02441 /* @brief Has external pin 23 connected to LLWU device. */ 02442 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 02443 /* @brief Index of port of external pin. */ 02444 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 02445 /* @brief Number of external pin port on specified port. */ 02446 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 02447 /* @brief Has external pin 24 connected to LLWU device. */ 02448 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 02449 /* @brief Index of port of external pin. */ 02450 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 02451 /* @brief Number of external pin port on specified port. */ 02452 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 02453 /* @brief Has external pin 25 connected to LLWU device. */ 02454 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 02455 /* @brief Index of port of external pin. */ 02456 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 02457 /* @brief Number of external pin port on specified port. */ 02458 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 02459 /* @brief Has external pin 26 connected to LLWU device. */ 02460 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 02461 /* @brief Index of port of external pin. */ 02462 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 02463 /* @brief Number of external pin port on specified port. */ 02464 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 02465 /* @brief Has external pin 27 connected to LLWU device. */ 02466 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 02467 /* @brief Index of port of external pin. */ 02468 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 02469 /* @brief Number of external pin port on specified port. */ 02470 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 02471 /* @brief Has external pin 28 connected to LLWU device. */ 02472 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 02473 /* @brief Index of port of external pin. */ 02474 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 02475 /* @brief Number of external pin port on specified port. */ 02476 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 02477 /* @brief Has external pin 29 connected to LLWU device. */ 02478 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 02479 /* @brief Index of port of external pin. */ 02480 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 02481 /* @brief Number of external pin port on specified port. */ 02482 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 02483 /* @brief Has external pin 30 connected to LLWU device. */ 02484 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 02485 /* @brief Index of port of external pin. */ 02486 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 02487 /* @brief Number of external pin port on specified port. */ 02488 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 02489 /* @brief Has external pin 31 connected to LLWU device. */ 02490 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 02491 /* @brief Index of port of external pin. */ 02492 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 02493 /* @brief Number of external pin port on specified port. */ 02494 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 02495 /* @brief Has internal module 0 connected to LLWU device. */ 02496 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 02497 /* @brief Has internal module 1 connected to LLWU device. */ 02498 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 02499 /* @brief Has internal module 2 connected to LLWU device. */ 02500 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 02501 /* @brief Has internal module 3 connected to LLWU device. */ 02502 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 02503 /* @brief Has internal module 4 connected to LLWU device. */ 02504 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 02505 /* @brief Has internal module 5 connected to LLWU device. */ 02506 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 02507 /* @brief Has internal module 6 connected to LLWU device. */ 02508 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 02509 /* @brief Has internal module 7 connected to LLWU device. */ 02510 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 02511 /* @brief Has Version ID Register (LLWU_VERID). */ 02512 #define FSL_FEATURE_LLWU_HAS_VERID (0) 02513 /* @brief Has Parameter Register (LLWU_PARAM). */ 02514 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 02515 /* @brief Width of registers of the LLWU. */ 02516 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 02517 /* @brief Has DMA Enable register (LLWU_DE). */ 02518 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 02519 #endif /* defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ 02520 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) */ 02521 02522 /* LPTMR module features */ 02523 02524 /* No feature definitions */ 02525 02526 /* MCG module features */ 02527 02528 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 02529 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 02530 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 02531 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) 02532 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 02533 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) 02534 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 02535 #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) 02536 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 02537 #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) 02538 /* @brief The PLL clock is divided by 2 before VCO divider. */ 02539 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 02540 /* @brief FRDIV supports 1280. */ 02541 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 02542 /* @brief FRDIV supports 1536. */ 02543 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 02544 /* @brief MCGFFCLK divider. */ 02545 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 02546 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 02547 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 02548 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 02549 #define FSL_FEATURE_MCG_HAS_RTC_32K (1) 02550 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 02551 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 02552 /* @brief Has 48MHz internal oscillator. */ 02553 #define FSL_FEATURE_MCG_HAS_IRC_48M (0) 02554 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 02555 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 02556 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 02557 #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) 02558 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 02559 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 02560 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 02561 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 02562 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 02563 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 02564 /* @brief TBD */ 02565 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 02566 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ 02567 #define FSL_FEATURE_MCG_HAS_PLL (1) 02568 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 02569 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 02570 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 02571 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 02572 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 02573 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) 02574 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 02575 #define FSL_FEATURE_MCG_HAS_FLL (1) 02576 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 02577 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 02578 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 02579 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 02580 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 02581 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 02582 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 02583 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 02584 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 02585 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 02586 /* @brief Has external clock monitor (register bit C6[CME]). */ 02587 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 02588 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 02589 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 02590 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 02591 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 02592 /* @brief Has PEI mode or PBI mode. */ 02593 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 02594 /* @brief Reset clock mode is BLPI. */ 02595 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 02596 02597 /* interrupt module features */ 02598 02599 /* @brief Lowest interrupt request number. */ 02600 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 02601 /* @brief Highest interrupt request number. */ 02602 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) 02603 02604 /* OSC module features */ 02605 02606 /* @brief Has OSC1 external oscillator. */ 02607 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 02608 /* @brief Has OSC0 external oscillator. */ 02609 #define FSL_FEATURE_OSC_HAS_OSC0 (1) 02610 /* @brief Has OSC external oscillator (without index). */ 02611 #define FSL_FEATURE_OSC_HAS_OSC (0) 02612 /* @brief Number of OSC external oscillators. */ 02613 #define FSL_FEATURE_OSC_OSC_COUNT (1) 02614 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 02615 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 02616 02617 /* PDB module features */ 02618 02619 /* @brief Define the count of supporting ADC pre-trigger for each channel. */ 02620 #define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2) 02621 /* @brief Has DAC support. */ 02622 #define FSL_FEATURE_PDB_HAS_DAC (0) 02623 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 02624 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 02625 02626 /* PIT module features */ 02627 02628 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 02629 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 02630 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 02631 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) 02632 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 02633 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (0) 02634 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 02635 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 02636 02637 /* PMC module features */ 02638 02639 /* @brief Has Bandgap Enable In VLPx Operation support. */ 02640 #define FSL_FEATURE_PMC_HAS_BGEN (0) 02641 /* @brief Has Bandgap Buffer Enable. */ 02642 #define FSL_FEATURE_PMC_HAS_BGBE (1) 02643 /* @brief Has Bandgap Buffer Drive Select. */ 02644 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 02645 /* @brief Has Low-Voltage Detect Voltage Select support. */ 02646 #define FSL_FEATURE_PMC_HAS_LVDV (1) 02647 /* @brief Has Low-Voltage Warning Voltage Select support. */ 02648 #define FSL_FEATURE_PMC_HAS_LVWV (1) 02649 /* @brief Has LPO. */ 02650 #define FSL_FEATURE_PMC_HAS_LPO (0) 02651 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 02652 #define FSL_FEATURE_PMC_HAS_VLPO (0) 02653 /* @brief Has acknowledge isolation support. */ 02654 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 02655 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 02656 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 02657 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 02658 #define FSL_FEATURE_PMC_HAS_REGONS (1) 02659 /* @brief Has PMC_HVDSC1. */ 02660 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 02661 /* @brief Has PMC_PARAM. */ 02662 #define FSL_FEATURE_PMC_HAS_PARAM (0) 02663 /* @brief Has PMC_VERID. */ 02664 #define FSL_FEATURE_PMC_HAS_VERID (0) 02665 02666 /* PORT module features */ 02667 02668 /* @brief Has control lock (register bit PCR[LK]). */ 02669 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 02670 /* @brief Has open drain control (register bit PCR[ODE]). */ 02671 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 02672 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 02673 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 02674 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 02675 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 02676 /* @brief Has pull resistor selection available. */ 02677 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 02678 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 02679 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 02680 /* @brief Has slew rate control (register bit PCR[SRE]). */ 02681 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 02682 /* @brief Has passive filter (register bit field PCR[PFE]). */ 02683 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 02684 /* @brief Has drive strength control (register bit PCR[DSE]). */ 02685 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 02686 /* @brief Has separate drive strength register (HDRVE). */ 02687 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 02688 /* @brief Has glitch filter (register IOFLT). */ 02689 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 02690 /* @brief Defines width of PCR[MUX] field. */ 02691 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 02692 /* @brief Has dedicated interrupt vector. */ 02693 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (0) 02694 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 02695 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 02696 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 02697 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 02698 02699 /* GPIO module features */ 02700 02701 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ 02702 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) 02703 /* @brief Has port input disable register (PIDR). */ 02704 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) 02705 /* @brief Has dedicated interrupt vector. */ 02706 #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) 02707 02708 /* RCM module features */ 02709 02710 /* @brief Has Loss-of-Lock Reset support. */ 02711 #define FSL_FEATURE_RCM_HAS_LOL (1) 02712 /* @brief Has Loss-of-Clock Reset support. */ 02713 #define FSL_FEATURE_RCM_HAS_LOC (1) 02714 /* @brief Has JTAG generated Reset support. */ 02715 #define FSL_FEATURE_RCM_HAS_JTAG (1) 02716 /* @brief Has EzPort generated Reset support. */ 02717 #define FSL_FEATURE_RCM_HAS_EZPORT (1) 02718 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 02719 #define FSL_FEATURE_RCM_HAS_EZPMS (1) 02720 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 02721 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 02722 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 02723 #define FSL_FEATURE_RCM_HAS_SSRS (0) 02724 /* @brief Has Version ID Register (RCM_VERID). */ 02725 #define FSL_FEATURE_RCM_HAS_VERID (0) 02726 /* @brief Has Parameter Register (RCM_PARAM). */ 02727 #define FSL_FEATURE_RCM_HAS_PARAM (0) 02728 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 02729 #define FSL_FEATURE_RCM_HAS_SRIE (0) 02730 /* @brief Width of registers of the RCM. */ 02731 #define FSL_FEATURE_RCM_REG_WIDTH (8) 02732 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 02733 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 02734 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 02735 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 02736 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 02737 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 02738 02739 /* RTC module features */ 02740 02741 /* @brief Has wakeup pin. */ 02742 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) 02743 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 02744 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) 02745 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 02746 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 02747 /* @brief Has read/write access control (registers WAR and RAR). */ 02748 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) 02749 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 02750 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 02751 /* @brief Has RTC_CLKIN available. */ 02752 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) 02753 /* @brief Has prescaler adjust for LPO. */ 02754 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 02755 /* @brief Has Clock Pin Enable field. */ 02756 #define FSL_FEATURE_RTC_HAS_CPE (0) 02757 /* @brief Has Timer Seconds Interrupt Configuration field. */ 02758 #define FSL_FEATURE_RTC_HAS_TSIC (0) 02759 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 02760 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 02761 02762 /* SMC module features */ 02763 02764 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 02765 #define FSL_FEATURE_SMC_HAS_PSTOPO (0) 02766 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 02767 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 02768 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 02769 #define FSL_FEATURE_SMC_HAS_PORPO (1) 02770 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 02771 #define FSL_FEATURE_SMC_HAS_LPWUI (1) 02772 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 02773 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 02774 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 02775 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 02776 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 02777 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) 02778 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 02779 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 02780 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 02781 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 02782 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 02783 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 02784 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 02785 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 02786 /* @brief Has stop submode. */ 02787 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 02788 /* @brief Has stop submode 0(VLLS0). */ 02789 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 02790 /* @brief Has stop submode 2(VLLS2). */ 02791 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 02792 /* @brief Has SMC_PARAM. */ 02793 #define FSL_FEATURE_SMC_HAS_PARAM (0) 02794 /* @brief Has SMC_VERID. */ 02795 #define FSL_FEATURE_SMC_HAS_VERID (0) 02796 02797 /* DSPI module features */ 02798 02799 #if defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ 02800 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) 02801 /* @brief Receive/transmit FIFO size in number of items. */ 02802 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) 02803 /* @brief Maximum transfer data width in bits. */ 02804 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 02805 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 02806 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 02807 /* @brief Number of chip select pins. */ 02808 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4) 02809 /* @brief Has chip select strobe capability on the PCS5 pin. */ 02810 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 02811 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 02812 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 02813 /* @brief Has 16-bit data transfer support. */ 02814 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 02815 /* @brief Has separate DMA RX and TX requests. */ 02816 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 02817 #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ 02818 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ 02819 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ 02820 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ 02821 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ 02822 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) 02823 /* @brief Receive/transmit FIFO size in number of items. */ 02824 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) 02825 /* @brief Maximum transfer data width in bits. */ 02826 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 02827 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 02828 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 02829 /* @brief Number of chip select pins. */ 02830 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) 02831 /* @brief Has chip select strobe capability on the PCS5 pin. */ 02832 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 02833 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 02834 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 02835 /* @brief Has 16-bit data transfer support. */ 02836 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 02837 /* @brief Has separate DMA RX and TX requests. */ 02838 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 02839 #endif /* defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ 02840 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) */ 02841 02842 /* SysTick module features */ 02843 02844 /* @brief Systick has external reference clock. */ 02845 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 02846 /* @brief Systick external reference clock is core clock divided by this value. */ 02847 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 02848 02849 /* TSI module features */ 02850 02851 /* @brief TSI module version. */ 02852 #define FSL_FEATURE_TSI_VERSION (2) 02853 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ 02854 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) 02855 /* @brief Number of TSI channels. */ 02856 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16) 02857 02858 /* UART module features */ 02859 02860 #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ 02861 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ 02862 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ 02863 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ 02864 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ 02865 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) 02866 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 02867 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 02868 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 02869 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 02870 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 02871 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 02872 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 02873 #define FSL_FEATURE_UART_HAS_FIFO (1) 02874 /* @brief Hardware flow control (RTS, CTS) is supported. */ 02875 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 02876 /* @brief Infrared (modulation) is supported. */ 02877 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 02878 /* @brief 2 bits long stop bit is available. */ 02879 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) 02880 /* @brief Maximal data width without parity bit. */ 02881 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) 02882 /* @brief Baud rate fine adjustment is available. */ 02883 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 02884 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 02885 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 02886 /* @brief Baud rate oversampling is available. */ 02887 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 02888 /* @brief Baud rate oversampling is available. */ 02889 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 02890 /* @brief Peripheral type. */ 02891 #define FSL_FEATURE_UART_IS_SCI (0) 02892 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 02893 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 02894 ((x) == UART0 ? (8) : \ 02895 ((x) == UART1 ? (1) : \ 02896 ((x) == UART2 ? (1) : (-1)))) 02897 /* @brief Maximal data width without parity bit. */ 02898 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) 02899 /* @brief Maximal data width with parity bit. */ 02900 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) 02901 /* @brief Supports two match addresses to filter incoming frames. */ 02902 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 02903 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 02904 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 02905 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 02906 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 02907 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 02908 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 02909 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 02910 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 02911 /* @brief Has improved smart card (ISO7816 protocol) support. */ 02912 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 02913 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 02914 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1) 02915 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 02916 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 02917 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 02918 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 02919 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 02920 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 02921 /* @brief Has separate DMA RX and TX requests. */ 02922 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 02923 #elif defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ 02924 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) 02925 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 02926 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 02927 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 02928 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 02929 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 02930 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 02931 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 02932 #define FSL_FEATURE_UART_HAS_FIFO (1) 02933 /* @brief Hardware flow control (RTS, CTS) is supported. */ 02934 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 02935 /* @brief Infrared (modulation) is supported. */ 02936 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 02937 /* @brief 2 bits long stop bit is available. */ 02938 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) 02939 /* @brief Maximal data width without parity bit. */ 02940 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) 02941 /* @brief Baud rate fine adjustment is available. */ 02942 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 02943 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 02944 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 02945 /* @brief Baud rate oversampling is available. */ 02946 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 02947 /* @brief Baud rate oversampling is available. */ 02948 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 02949 /* @brief Peripheral type. */ 02950 #define FSL_FEATURE_UART_IS_SCI (0) 02951 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 02952 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 02953 ((x) == UART0 ? (8) : \ 02954 ((x) == UART1 ? (1) : (-1))) 02955 /* @brief Maximal data width without parity bit. */ 02956 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) 02957 /* @brief Maximal data width with parity bit. */ 02958 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) 02959 /* @brief Supports two match addresses to filter incoming frames. */ 02960 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 02961 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 02962 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 02963 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 02964 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 02965 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 02966 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 02967 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 02968 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 02969 /* @brief Has improved smart card (ISO7816 protocol) support. */ 02970 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 02971 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 02972 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1) 02973 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 02974 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 02975 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 02976 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 02977 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 02978 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 02979 /* @brief Has separate DMA RX and TX requests. */ 02980 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 02981 #endif /* defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ 02982 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ 02983 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ 02984 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ 02985 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ 02986 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) */ 02987 02988 /* USB module features */ 02989 02990 /* @brief HOST mode enabled */ 02991 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) 02992 /* @brief OTG mode enabled */ 02993 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) 02994 /* @brief Size of the USB dedicated RAM */ 02995 #define FSL_FEATURE_USB_KHCI_USB_RAM (0) 02996 /* @brief Has KEEP_ALIVE_CTRL register */ 02997 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) 02998 /* @brief Has the Dynamic SOF threshold compare support */ 02999 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) 03000 /* @brief Has the VBUS detect support */ 03001 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) 03002 /* @brief Has the IRC48M module clock support */ 03003 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0) 03004 /* @brief Number of endpoints supported */ 03005 #define FSL_FEATURE_USB_ENDPT_COUNT (16) 03006 03007 /* VREF module features */ 03008 03009 #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ 03010 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ 03011 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ 03012 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ 03013 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ 03014 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) 03015 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 03016 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 03017 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 03018 #define FSL_FEATURE_VREF_HAS_COMPENSATION (0) 03019 /* @brief If high/low buffer mode supported */ 03020 #define FSL_FEATURE_VREF_MODE_LV_TYPE (0) 03021 /* @brief Module has also low reference (registers VREFL/VREFH) */ 03022 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 03023 /* @brief Has VREF_TRM4. */ 03024 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 03025 #endif /* defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ 03026 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ 03027 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ 03028 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ 03029 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ 03030 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) */ 03031 03032 /* WDOG module features */ 03033 03034 /* @brief Watchdog is available. */ 03035 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 03036 /* @brief Has Wait mode support. */ 03037 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 03038 03039 #endif /* _MK20D5_FEATURES_H_ */ 03040
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