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LPC11Uxx.h File Reference
CMSIS Cortex-M0 Core Peripheral Access Layer Header File for default LPC11Uxx Device Series. More...
Go to the source code of this file.
Data Structures | |
| struct | LPC_I2C_Type |
| Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C) More... | |
| struct | LPC_WWDT_Type |
| Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT) More... | |
| struct | LPC_USART_Type |
| Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART) More... | |
| struct | LPC_CTxxBx_Type |
| Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3. More... | |
| struct | LPC_ADC_Type |
| Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC) More... | |
| struct | LPC_PMU_Type |
| Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU) More... | |
| struct | LPC_FLASHCTRL_Type |
| Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL) More... | |
| struct | LPC_SSPx_Type |
| Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0) More... | |
| struct | LPC_IOCON_Type |
| Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) More... | |
| struct | LPC_SYSCON_Type |
| Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON) More... | |
| struct | LPC_GPIO_PIN_INT_Type |
| Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT) More... | |
| struct | LPC_GPIO_GROUP_INTx_Type |
| Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0) More... | |
| struct | LPC_USB_Type |
| Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB) More... | |
| struct | LPC_GPIO_Type |
| Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) More... | |
Enumerations | |
| enum | IRQn_Type { , Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, FLEX_INT0_IRQn = 0 , GINT0_IRQn = 8, GINT1_IRQn = 9, Reserved0_IRQn = 10 , SSP1_IRQn = 14, I2C_IRQn = 15, TIMER_16_0_IRQn = 16, TIMER_16_1_IRQn = 17, TIMER_32_0_IRQn = 18, TIMER_32_1_IRQn = 19, SSP0_IRQn = 20, UART_IRQn = 21, USB_IRQn = 22, USB_FIQn = 23, ADC_IRQn = 24, WDT_IRQn = 25, BOD_IRQn = 26, FMC_IRQn = 27, Reserved4_IRQn = 28, Reserved5_IRQn = 29, USBWakeup_IRQn = 30, Reserved6_IRQn = 31, Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, DAC_IRQn = 0, M0CORE_IRQn = 1, DMA_IRQn = 2, RESERVED1_IRQn = 3 , ETHERNET_IRQn = 5, SDIO_IRQn = 6, LCD_IRQn = 7, USB0_IRQn = 8, USB1_IRQn = 9, SCT_IRQn = 10, RITIMER_IRQn = 11, TIMER0_IRQn = 12, TIMER1_IRQn = 13, TIMER2_IRQn = 14, TIMER3_IRQn = 15, MCPWM_IRQn = 16, ADC0_IRQn = 17, I2C0_IRQn = 18, I2C1_IRQn = 19, SPI_INT_IRQn = 20, ADC1_IRQn = 21, SSP0_IRQn = 22, SSP1_IRQn = 23, USART0_IRQn = 24, UART1_IRQn = 25, USART2_IRQn = 26, USART3_IRQn = 27, I2S0_IRQn = 28, I2S1_IRQn = 29 , SGPIO_IINT_IRQn = 31, PIN_INT0_IRQn = 32, PIN_INT1_IRQn = 33, PIN_INT2_IRQn = 34, PIN_INT3_IRQn = 35, PIN_INT4_IRQn = 36, PIN_INT5_IRQn = 37, PIN_INT6_IRQn = 38, PIN_INT7_IRQn = 39, GINT0_IRQn = 40, GINT1_IRQn = 41, EVENTROUTER_IRQn = 42, C_CAN1_IRQn = 43 , VADC_IRQn = 45, ATIMER_IRQn = 46, RTC_IRQn = 47 , WWDT_IRQn = 49 , C_CAN0_IRQn = 51, QEI_IRQn = 52, M0_Reset_IRQn = -15, M0_NonMaskableInt_IRQn = -14, M0_HardFault_IRQn = -13, M0_SVCall_IRQn = -5, M0_DebugMonitor_IRQn = -4, M0_PendSV_IRQn = -2, M0_SysTick_IRQn = -1, M0_RTC_IRQn = 0, M0_M4CORE_IRQn = 1, M0_DMA_IRQn = 2 , M0_ETHERNET_IRQn = 5, M0_SDIO_IRQn = 6, M0_LCD_IRQn = 7, M0_USB0_IRQn = 8, M0_USB1_IRQn = 9, M0_SCT_IRQn = 10, M0_RITIMER_OR_WWDT_IRQn = 11, M0_TIMER0_IRQn = 12, M0_GINT1_IRQn = 13, M0_TIMER3_IRQn = 15 , M0_MCPWM_IRQn = 16, M0_ADC0_IRQn = 17, M0_I2C0_OR_I2C1_IRQn = 18, M0_SGPIO_IRQn = 19, M0_SPI_OR_DAC_IRQn = 20, M0_ADC1_IRQn = 21, M0_SSP0_OR_SSP1_IRQn = 22, M0_EVENTROUTER_IRQn = 23, M0_USART0_IRQn = 24, M0_UART1_IRQn = 25, M0_USART2_OR_C_CAN1_IRQn = 26, M0_USART3_IRQn = 27, M0_I2S0_OR_I2S1_OR_QEI_IRQn = 28, M0_C_CAN0_IRQn = 29, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMPER_IRQn = 2, RTC_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11, DMA1_Channel2_IRQn = 12, DMA1_Channel3_IRQn = 13, DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15, DMA1_Channel6_IRQn = 16, DMA1_Channel7_IRQn = 17, ADC1_2_IRQn = 18, USB_HP_CAN1_TX_IRQn = 19, USB_LP_CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_IRQn = 24, TIM1_UP_IRQn = 25, TIM1_TRG_COM_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, USBWakeUp_IRQn = 42 } |
Detailed Description
CMSIS Cortex-M0 Core Peripheral Access Layer Header File for default LPC11Uxx Device Series.
- Version:
- V0.1
- Date:
- 21. March 2011
- Note:
- Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1, created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
Definition in file LPC11Uxx.h.
Generated on Tue Jul 12 2022 15:37:29 by
1.7.2