HardFault_Handler.c

00001 /**
00002  * @file    main.c
00003  * @brief   Entry point for interface program logic
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 
00023 #include "settings.h"
00024 #include "util.h"
00025 #include "cortex_m.h"
00026 
00027 register unsigned int _psp __asm("psp");
00028 register unsigned int _msp __asm("msp");
00029 register unsigned int _lr __asm("lr");
00030 register unsigned int _control __asm("control");
00031 void HardFault_Handler()
00032 {
00033 //hexdump logic on hardfault
00034     uint32_t stk_ptr;
00035     uint32_t * stack = (uint32_t *)_msp;
00036     
00037     if ((_lr & 0xF) == 0xD) { //process stack
00038         stack = (uint32_t *)_psp;
00039     }
00040 
00041     //calculate stack ptr before fault
00042     stk_ptr = (uint32_t)stack + 0x20;
00043     if ((stack[7] & 0x200) != 0) { //xpsr bit 9 align
00044         stk_ptr += 0x4;
00045     }
00046     if ((_lr & 0x10) == 0) { //fp
00047         stk_ptr += 0x48;
00048     }
00049     
00050     config_ram_add_hexdump(_lr);  //EXC_RETURN
00051     config_ram_add_hexdump(_psp);
00052     config_ram_add_hexdump(_msp);
00053     config_ram_add_hexdump(_control);
00054     config_ram_add_hexdump(stk_ptr); //SP
00055     config_ram_add_hexdump(stack[5]);  //LR
00056     config_ram_add_hexdump(stack[6]);  //PC
00057     config_ram_add_hexdump(stack[7]);  //xPSR 
00058 
00059 #ifndef __CORTEX_M
00060 #error __CORTEX_M not defined!!
00061 #else
00062 
00063 #if (__CORTEX_M > 0x00)
00064     config_ram_add_hexdump(SCB->HFSR);
00065     config_ram_add_hexdump(SCB->CFSR);
00066     config_ram_add_hexdump(SCB->DFSR);
00067     config_ram_add_hexdump(SCB->AFSR);
00068     config_ram_add_hexdump(SCB->MMFAR);
00069     config_ram_add_hexdump(SCB->BFAR);
00070 #endif  
00071 
00072 #endif //#ifndef __CORTEX_M
00073 
00074     util_assert(0);
00075     SystemReset();
00076 
00077     while (1); // Wait for reset
00078 }