main.cpp

00001 #include "mbed.h"
00002 #define PWM_PERIOD_COUNT 20000
00003 /*
00004 For register definitions see here:
00005 https://github.com/ARMmbed/mbed-os/blob/master/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h
00006 */
00007 // Using the MBED libraries to configure the PWM outputs (its easier than 
00008 // calculating all of the register contents by hand)
00009 
00010 PwmOut  PhaATop(PA_8); 
00011 PwmOut  PhaBTop(PA_9); 
00012 PwmOut  PhaCTop(PA_10); 
00013 PwmOut  PhaABottom(PA_7); 
00014 PwmOut  PhaBBottom(PB_0); 
00015 PwmOut  PhaCBottom(PB_1); 
00016 
00017 void TimerISR(void)
00018 {   
00019     
00020    
00021     TIM1->CCR1 = PWM_PERIOD_COUNT/2;    
00022     TIM1->CCR2 = PWM_PERIOD_COUNT/2;
00023     TIM1->CCR3 = PWM_PERIOD_COUNT/2;
00024    
00025     TIM1->SR &= ~0x3f; // ack the interrupt    
00026 }
00027 void initTimer1()
00028 {    
00029     
00030     TIM1->CR1 = 0; // make sure Counter is disabled before changing configuration
00031     TIM1->CR2 = 0;
00032     TIM1->ARR = PWM_PERIOD_COUNT;
00033     TIM1->CCR1 = 0; // 0% duty
00034     TIM1->CCR2 = 0; // 0% duty
00035     TIM1->CCR3 = 0; // 0% duty
00036     // Enable complimentary outputs on channels 1 to 3
00037     TIM1->CCER = (1 << 0) + (1 << 2) + (1 << 4) + (1 << 6) + (1 << 8) + (1<<10);
00038     TIM1->SR = 0;      // Clear flags.    
00039     TIM1->BDTR &= ~(0xff);
00040     TIM1->BDTR |= (127); // set dead time to 127 clock cycles
00041     // Set up the interrupt handler
00042     TIM1->DIER = 1; // Want update interrupt
00043     NVIC_SetVector(TIM1_UP_TIM16_IRQn,(uint32_t) TimerISR);   
00044     NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
00045     __enable_irq();   // enable interrupts */
00046     TIM1->CR1 |= 1; // enable counter
00047 
00048 }
00049 int main() {
00050     initTimer1();
00051     while(1) {
00052         
00053     }
00054 }