Anthem / Mbed 2 deprecated Object_Model

Object Model code with hardware support

Dependencies:   mbed

hardware_F072.cpp@0:2b4bbe9ea495, 2014-09-05 (annotated)

Committer:
bgrissom
Date:
Fri Sep 05 00:07:44 2014 +0000
Revision:
0:2b4bbe9ea495
Object Model code with Toshiba S0 and S1 routines compiles with ST F401RE board support.  If you try to compile this for the F030 or F072, it will run out of SRAM space.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bgrissom 0:2b4bbe9ea495 1 #include "hardware_F072.hpp"
bgrissom 0:2b4bbe9ea495 2
bgrissom 0:2b4bbe9ea495 3 static TIM_HandleTypeDef TimHandleBAG;
bgrissom 0:2b4bbe9ea495 4
bgrissom 0:2b4bbe9ea495 5 static void pwmout_write_BAG(pwmout_t* obj, float value) {
bgrissom 0:2b4bbe9ea495 6 TIM_OC_InitTypeDef sConfig;
bgrissom 0:2b4bbe9ea495 7 int channel = 0;
bgrissom 0:2b4bbe9ea495 8 int complementary_channel = 0;
bgrissom 0:2b4bbe9ea495 9
bgrissom 0:2b4bbe9ea495 10 TimHandleBAG.Instance = (TIM_TypeDef *)(obj->pwm);
bgrissom 0:2b4bbe9ea495 11
bgrissom 0:2b4bbe9ea495 12 if (value < (float)0.0) {
bgrissom 0:2b4bbe9ea495 13 value = 0.0;
bgrissom 0:2b4bbe9ea495 14 } else if (value > (float)1.0) {
bgrissom 0:2b4bbe9ea495 15 value = 1.0;
bgrissom 0:2b4bbe9ea495 16 }
bgrissom 0:2b4bbe9ea495 17
bgrissom 0:2b4bbe9ea495 18 obj->pulse = (uint32_t)((float)obj->period * value);
bgrissom 0:2b4bbe9ea495 19
bgrissom 0:2b4bbe9ea495 20 // Configure channels
bgrissom 0:2b4bbe9ea495 21 sConfig.OCMode = TIM_OCMODE_PWM1;
bgrissom 0:2b4bbe9ea495 22 sConfig.Pulse = obj->pulse;
bgrissom 0:2b4bbe9ea495 23 sConfig.OCPolarity = TIM_OCPOLARITY_HIGH;
bgrissom 0:2b4bbe9ea495 24 sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH;
bgrissom 0:2b4bbe9ea495 25 sConfig.OCFastMode = TIM_OCFAST_DISABLE;
bgrissom 0:2b4bbe9ea495 26 sConfig.OCIdleState = TIM_OCIDLESTATE_RESET;
bgrissom 0:2b4bbe9ea495 27 sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
bgrissom 0:2b4bbe9ea495 28
bgrissom 0:2b4bbe9ea495 29 switch (obj->pin) {
bgrissom 0:2b4bbe9ea495 30 // Channels 1
bgrissom 0:2b4bbe9ea495 31 case PA_2:
bgrissom 0:2b4bbe9ea495 32 case PA_4:
bgrissom 0:2b4bbe9ea495 33 case PA_6:
bgrissom 0:2b4bbe9ea495 34 case PA_7:
bgrissom 0:2b4bbe9ea495 35 case PA_8:
bgrissom 0:2b4bbe9ea495 36 case PB_1:
bgrissom 0:2b4bbe9ea495 37 case PB_4:
bgrissom 0:2b4bbe9ea495 38 case PB_8:
bgrissom 0:2b4bbe9ea495 39 case PB_9:
bgrissom 0:2b4bbe9ea495 40 case PB_14:
bgrissom 0:2b4bbe9ea495 41 case PC_6:
bgrissom 0:2b4bbe9ea495 42 channel = TIM_CHANNEL_1;
bgrissom 0:2b4bbe9ea495 43 break;
bgrissom 0:2b4bbe9ea495 44 // Channels 1N
bgrissom 0:2b4bbe9ea495 45 case PA_1:
bgrissom 0:2b4bbe9ea495 46 case PB_6:
bgrissom 0:2b4bbe9ea495 47 case PB_7:
bgrissom 0:2b4bbe9ea495 48 case PB_13:
bgrissom 0:2b4bbe9ea495 49 channel = TIM_CHANNEL_1;
bgrissom 0:2b4bbe9ea495 50 complementary_channel = 1;
bgrissom 0:2b4bbe9ea495 51 break;
bgrissom 0:2b4bbe9ea495 52 // Channels 2
bgrissom 0:2b4bbe9ea495 53 case PA_3:
bgrissom 0:2b4bbe9ea495 54 case PA_9:
bgrissom 0:2b4bbe9ea495 55 case PB_5:
bgrissom 0:2b4bbe9ea495 56 case PB_15:
bgrissom 0:2b4bbe9ea495 57 case PC_7:
bgrissom 0:2b4bbe9ea495 58 channel = TIM_CHANNEL_2;
bgrissom 0:2b4bbe9ea495 59 break;
bgrissom 0:2b4bbe9ea495 60 // Channels 3
bgrissom 0:2b4bbe9ea495 61 case PA_10:
bgrissom 0:2b4bbe9ea495 62 case PB_0:
bgrissom 0:2b4bbe9ea495 63 case PC_8:
bgrissom 0:2b4bbe9ea495 64 channel = TIM_CHANNEL_3;
bgrissom 0:2b4bbe9ea495 65 break;
bgrissom 0:2b4bbe9ea495 66 // Channels 4
bgrissom 0:2b4bbe9ea495 67 case PA_11:
bgrissom 0:2b4bbe9ea495 68 case PC_9:
bgrissom 0:2b4bbe9ea495 69 channel = TIM_CHANNEL_4;
bgrissom 0:2b4bbe9ea495 70 break;
bgrissom 0:2b4bbe9ea495 71 default:
bgrissom 0:2b4bbe9ea495 72 return;
bgrissom 0:2b4bbe9ea495 73 }
bgrissom 0:2b4bbe9ea495 74
bgrissom 0:2b4bbe9ea495 75 HAL_TIM_PWM_ConfigChannel(&TimHandleBAG, &sConfig, channel);
bgrissom 0:2b4bbe9ea495 76
bgrissom 0:2b4bbe9ea495 77 if (complementary_channel) {
bgrissom 0:2b4bbe9ea495 78 HAL_TIMEx_PWMN_Start(&TimHandleBAG, channel);
bgrissom 0:2b4bbe9ea495 79 } else {
bgrissom 0:2b4bbe9ea495 80 HAL_TIM_PWM_Start(&TimHandleBAG, channel);
bgrissom 0:2b4bbe9ea495 81 }
bgrissom 0:2b4bbe9ea495 82 }
bgrissom 0:2b4bbe9ea495 83
bgrissom 0:2b4bbe9ea495 84
bgrissom 0:2b4bbe9ea495 85 void pwmout_period_ns(pwmout_t* obj, int us) {
bgrissom 0:2b4bbe9ea495 86 TimHandleBAG.Instance = (TIM_TypeDef *)(obj->pwm);
bgrissom 0:2b4bbe9ea495 87
bgrissom 0:2b4bbe9ea495 88 float dc = pwmout_read(obj);
bgrissom 0:2b4bbe9ea495 89
bgrissom 0:2b4bbe9ea495 90 __HAL_TIM_DISABLE(&TimHandleBAG);
bgrissom 0:2b4bbe9ea495 91
bgrissom 0:2b4bbe9ea495 92 // Update the SystemCoreClock variable
bgrissom 0:2b4bbe9ea495 93 SystemCoreClockUpdate();
bgrissom 0:2b4bbe9ea495 94
bgrissom 0:2b4bbe9ea495 95 TimHandleBAG.Init.Period = us - 1;
bgrissom 0:2b4bbe9ea495 96 // BAG Orig: TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
bgrissom 0:2b4bbe9ea495 97 TimHandleBAG.Init.Prescaler = 0; // BAG 1 ns tick (?)
bgrissom 0:2b4bbe9ea495 98 TimHandleBAG.Init.ClockDivision = 0;
bgrissom 0:2b4bbe9ea495 99 TimHandleBAG.Init.CounterMode = TIM_COUNTERMODE_UP;
bgrissom 0:2b4bbe9ea495 100 HAL_TIM_PWM_Init(&TimHandleBAG);
bgrissom 0:2b4bbe9ea495 101
bgrissom 0:2b4bbe9ea495 102 // Set duty cycle again
bgrissom 0:2b4bbe9ea495 103 pwmout_write_BAG(obj, dc);
bgrissom 0:2b4bbe9ea495 104
bgrissom 0:2b4bbe9ea495 105 // Save for future use
bgrissom 0:2b4bbe9ea495 106 obj->period = us;
bgrissom 0:2b4bbe9ea495 107
bgrissom 0:2b4bbe9ea495 108 __HAL_TIM_ENABLE(&TimHandleBAG);
bgrissom 0:2b4bbe9ea495 109 }
bgrissom 0:2b4bbe9ea495 110
bgrissom 0:2b4bbe9ea495 111
bgrissom 0:2b4bbe9ea495 112 /* USED FOR THE F030 BOARD
bgrissom 0:2b4bbe9ea495 113 // This code is based off:
bgrissom 0:2b4bbe9ea495 114 // mbed/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/pwmout_api.c pwmout_period_us()
bgrissom 0:2b4bbe9ea495 115 void pwmout_period_ns_NOT_USED(pwmout_t* obj, int us) {
bgrissom 0:2b4bbe9ea495 116 TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm);
bgrissom 0:2b4bbe9ea495 117 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
bgrissom 0:2b4bbe9ea495 118 float dc = pwmout_read(obj);
bgrissom 0:2b4bbe9ea495 119
bgrissom 0:2b4bbe9ea495 120 TIM_Cmd(tim, DISABLE);
bgrissom 0:2b4bbe9ea495 121
bgrissom 0:2b4bbe9ea495 122 obj->period = us;
bgrissom 0:2b4bbe9ea495 123
bgrissom 0:2b4bbe9ea495 124 TIM_TimeBaseStructure.TIM_Period = obj->period - 1;
bgrissom 0:2b4bbe9ea495 125 // Orig code: TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
bgrissom 0:2b4bbe9ea495 126 TIM_TimeBaseStructure.TIM_Prescaler = 0; // BAG 1 ns tick (?)
bgrissom 0:2b4bbe9ea495 127 TIM_TimeBaseStructure.TIM_ClockDivision = 0;
bgrissom 0:2b4bbe9ea495 128 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
bgrissom 0:2b4bbe9ea495 129 TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure);
bgrissom 0:2b4bbe9ea495 130
bgrissom 0:2b4bbe9ea495 131 // Set duty cycle again
bgrissom 0:2b4bbe9ea495 132 pwmout_write(obj, dc);
bgrissom 0:2b4bbe9ea495 133
bgrissom 0:2b4bbe9ea495 134 TIM_ARRPreloadConfig(tim, ENABLE);
bgrissom 0:2b4bbe9ea495 135
bgrissom 0:2b4bbe9ea495 136 TIM_Cmd(tim, ENABLE);
bgrissom 0:2b4bbe9ea495 137 }
bgrissom 0:2b4bbe9ea495 138 */
bgrissom 0:2b4bbe9ea495 139