Anthem / Mbed 2 deprecated Object_Model

Object Model code with hardware support

Dependencies:   mbed

ToshibaTC62D723.cpp@0:2b4bbe9ea495, 2014-09-05 (annotated)

Committer:
bgrissom
Date:
Fri Sep 05 00:07:44 2014 +0000
Revision:
0:2b4bbe9ea495
Object Model code with Toshiba S0 and S1 routines compiles with ST F401RE board support.  If you try to compile this for the F030 or F072, it will run out of SRAM space.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bgrissom 0:2b4bbe9ea495 1 #include <cstddef>
bgrissom 0:2b4bbe9ea495 2 #include <string.h>
bgrissom 0:2b4bbe9ea495 3 #include "ToshibaTC62D723.hpp"
bgrissom 0:2b4bbe9ea495 4
bgrissom 0:2b4bbe9ea495 5 bool gSpiMode;
bgrissom 0:2b4bbe9ea495 6 SPI* gSpiPtr = NULL;
bgrissom 0:2b4bbe9ea495 7 DigitalOut gbbTRANS(PA_4); // Global bit bang TRANS (data) line
bgrissom 0:2b4bbe9ea495 8
bgrissom 0:2b4bbe9ea495 9 ToshibaTC62D723::ToshibaTC62D723(void)
bgrissom 0:2b4bbe9ea495 10 : _dataIn(NULL),
bgrissom 0:2b4bbe9ea495 11 _dataOut(NULL)
bgrissom 0:2b4bbe9ea495 12 {
bgrissom 0:2b4bbe9ea495 13 memset(_channelBrightness, 0, sizeof(uint16_t) * NUM_CHANNELS);
bgrissom 0:2b4bbe9ea495 14 }
bgrissom 0:2b4bbe9ea495 15
bgrissom 0:2b4bbe9ea495 16 ToshibaTC62D723::~ToshibaTC62D723(void)
bgrissom 0:2b4bbe9ea495 17 {
bgrissom 0:2b4bbe9ea495 18 // Its good practice to clear memory in the destructor
bgrissom 0:2b4bbe9ea495 19 memset(_channelBrightness, 0, sizeof(uint16_t) * NUM_CHANNELS);
bgrissom 0:2b4bbe9ea495 20 }
bgrissom 0:2b4bbe9ea495 21
bgrissom 0:2b4bbe9ea495 22 void ToshibaTC62D723::shiftBrightnessDataIn(const uint16_t p_brightness)
bgrissom 0:2b4bbe9ea495 23 {
bgrissom 0:2b4bbe9ea495 24 // TODO check return code?
bgrissom 0:2b4bbe9ea495 25 s0(p_brightness);
bgrissom 0:2b4bbe9ea495 26 }
bgrissom 0:2b4bbe9ea495 27
bgrissom 0:2b4bbe9ea495 28 void ToshibaTC62D723::outputBrightnessDataToLEDs(void)
bgrissom 0:2b4bbe9ea495 29 {
bgrissom 0:2b4bbe9ea495 30 s1();
bgrissom 0:2b4bbe9ea495 31 }
bgrissom 0:2b4bbe9ea495 32
bgrissom 0:2b4bbe9ea495 33 // S0 Command:
bgrissom 0:2b4bbe9ea495 34 // Needs only SCK and SIN (which are SPI_SCK and SPI_MOSI respectively).
bgrissom 0:2b4bbe9ea495 35 // This is because TRANS can be 0 for this command according to the datasheet.
bgrissom 0:2b4bbe9ea495 36 int ToshibaTC62D723::s0(const uint16_t p_value)
bgrissom 0:2b4bbe9ea495 37 {
bgrissom 0:2b4bbe9ea495 38 if (p_value > 0 ) {
bgrissom 0:2b4bbe9ea495 39 BAGINFO3("%x", p_value);
bgrissom 0:2b4bbe9ea495 40 } else {
bgrissom 0:2b4bbe9ea495 41 BAGINFO3(".");
bgrissom 0:2b4bbe9ea495 42 }
bgrissom 0:2b4bbe9ea495 43
bgrissom 0:2b4bbe9ea495 44 // Command S0 and S1 share the same clock line, so we need to be
bgrissom 0:2b4bbe9ea495 45 // careful which mode we are in. This avoids re-initializing these
bgrissom 0:2b4bbe9ea495 46 // pins if we are already in SPI mode.
bgrissom 0:2b4bbe9ea495 47 // WARNING: Re-initializing every time makes the MOSI line dirty and
bgrissom 0:2b4bbe9ea495 48 // is wasteful for the CPU.
bgrissom 0:2b4bbe9ea495 49 if ( gSpiMode == false &&
bgrissom 0:2b4bbe9ea495 50 gSpiPtr == NULL)
bgrissom 0:2b4bbe9ea495 51 {
bgrissom 0:2b4bbe9ea495 52 // We are not using MISO, this is a one-way bus
bgrissom 0:2b4bbe9ea495 53 gSpiPtr = new SPI(SPI_MOSI, NC, SPI_SCK);
bgrissom 0:2b4bbe9ea495 54
bgrissom 0:2b4bbe9ea495 55 if (gSpiPtr == NULL) {
bgrissom 0:2b4bbe9ea495 56 printf("ERROR: Could not allocate SPI\n");
bgrissom 0:2b4bbe9ea495 57 return AERROR;
bgrissom 0:2b4bbe9ea495 58 }
bgrissom 0:2b4bbe9ea495 59
bgrissom 0:2b4bbe9ea495 60 // Note: Polarity and phase are both 0 for the TC62D723FNG
bgrissom 0:2b4bbe9ea495 61 // For a graphical reminder on polarity and phase, visit:
bgrissom 0:2b4bbe9ea495 62 // http://www.eetimes.com/document.asp?doc_id=1272534
bgrissom 0:2b4bbe9ea495 63 gSpiPtr->format(16, 0);
bgrissom 0:2b4bbe9ea495 64 // gSpiPtr->frequency(1000000); // 1.5 MHz on the scope
bgrissom 0:2b4bbe9ea495 65 gSpiPtr->frequency(24000000); // 24 MHz
bgrissom 0:2b4bbe9ea495 66 gSpiMode = true;
bgrissom 0:2b4bbe9ea495 67 }
bgrissom 0:2b4bbe9ea495 68 gbbTRANS = 0; // Like an SPI slave select
bgrissom 0:2b4bbe9ea495 69 gSpiPtr->write(p_value);
bgrissom 0:2b4bbe9ea495 70 gbbTRANS = 1; // Like an SPI slave select
bgrissom 0:2b4bbe9ea495 71
bgrissom 0:2b4bbe9ea495 72 return AOK;
bgrissom 0:2b4bbe9ea495 73 }
bgrissom 0:2b4bbe9ea495 74
bgrissom 0:2b4bbe9ea495 75 void ToshibaTC62D723::s1(void)
bgrissom 0:2b4bbe9ea495 76 {
bgrissom 0:2b4bbe9ea495 77 BAGINFO3("\nLATCH\n");
bgrissom 0:2b4bbe9ea495 78
bgrissom 0:2b4bbe9ea495 79 int i = 0;
bgrissom 0:2b4bbe9ea495 80 int j = 0;
bgrissom 0:2b4bbe9ea495 81
bgrissom 0:2b4bbe9ea495 82 gbbTRANS = 0;
bgrissom 0:2b4bbe9ea495 83
bgrissom 0:2b4bbe9ea495 84 if ( gSpiMode == true &&
bgrissom 0:2b4bbe9ea495 85 gSpiPtr != NULL)
bgrissom 0:2b4bbe9ea495 86 {
bgrissom 0:2b4bbe9ea495 87 delete gSpiPtr;
bgrissom 0:2b4bbe9ea495 88 gSpiPtr = NULL;
bgrissom 0:2b4bbe9ea495 89 gSpiMode = false;
bgrissom 0:2b4bbe9ea495 90 }
bgrissom 0:2b4bbe9ea495 91
bgrissom 0:2b4bbe9ea495 92 DigitalOut bbSCK (D13); // bit bang clock
bgrissom 0:2b4bbe9ea495 93
bgrissom 0:2b4bbe9ea495 94 bbSCK = 0; // Start off/low
bgrissom 0:2b4bbe9ea495 95 gbbTRANS = 1; // Set high
bgrissom 0:2b4bbe9ea495 96
bgrissom 0:2b4bbe9ea495 97 // Loop 6 times = 3 clock cycles
bgrissom 0:2b4bbe9ea495 98 for (j=0; j<6; j++) { // Always use an even number here!
bgrissom 0:2b4bbe9ea495 99 // The order of these two lines matter!
bgrissom 0:2b4bbe9ea495 100 i == 0 ? i = 1 : i = 0; // Toggle i
bgrissom 0:2b4bbe9ea495 101 i == 0 ? bbSCK = 0 : bbSCK = 1; // Set SCK to the same value as i
bgrissom 0:2b4bbe9ea495 102 }
bgrissom 0:2b4bbe9ea495 103 gbbTRANS = 0; // Set low
bgrissom 0:2b4bbe9ea495 104 }