Analog Devices / sdp_k1_sdram

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sdp_k1_sdram.h@1:c1da02c6a73c, 2020-10-15 (annotated)

Committer:
Kjansen45
Date:
Thu Oct 15 14:17:45 2020 +0000
Revision:
1:c1da02c6a73c
Parent:
0:59a74b81fde8
Child:
2:7578b6878449
Repository Created.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kjansen45 0:59a74b81fde8 1 #ifndef __SDPK1_SDRAM_H
Kjansen45 0:59a74b81fde8 2 #define __SDPK1_SDRAM_H
Kjansen45 0:59a74b81fde8 3
Kjansen45 0:59a74b81fde8 4 #ifdef __cplusplus
Kjansen45 0:59a74b81fde8 5 extern "C" {
Kjansen45 0:59a74b81fde8 6 #endif
Kjansen45 0:59a74b81fde8 7
Kjansen45 0:59a74b81fde8 8 #include "stm32f4xx_hal.h"
Kjansen45 0:59a74b81fde8 9
Kjansen45 0:59a74b81fde8 10 /* SDRAM status defines */
Kjansen45 0:59a74b81fde8 11 #define SDRAM_OK ((uint8_t)0x00)
Kjansen45 0:59a74b81fde8 12 #define SDRAM_ERROR ((uint8_t)0x01)
Kjansen45 0:59a74b81fde8 13
Kjansen45 0:59a74b81fde8 14 #define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000) /* SDRAM device address */
Kjansen45 0:59a74b81fde8 15
Kjansen45 0:59a74b81fde8 16 #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32
Kjansen45 0:59a74b81fde8 17
Kjansen45 0:59a74b81fde8 18 #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
Kjansen45 0:59a74b81fde8 19
Kjansen45 0:59a74b81fde8 20 #define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */
Kjansen45 0:59a74b81fde8 21
Kjansen45 0:59a74b81fde8 22 #define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
Kjansen45 0:59a74b81fde8 23
Kjansen45 0:59a74b81fde8 24 /* DMA definitions for SDRAM DMA transfer */
Kjansen45 0:59a74b81fde8 25 #define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
Kjansen45 0:59a74b81fde8 26 #define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
Kjansen45 0:59a74b81fde8 27 #define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
Kjansen45 0:59a74b81fde8 28 #define SDRAM_DMAx_STREAM DMA2_Stream0
Kjansen45 0:59a74b81fde8 29 #define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
Kjansen45 0:59a74b81fde8 30 #define BSP_SDRAM_DMA_IRQHandler DMA2_Stream0_IRQHandler
Kjansen45 0:59a74b81fde8 31
Kjansen45 0:59a74b81fde8 32 /* SDRAM register defines */
Kjansen45 0:59a74b81fde8 33 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
Kjansen45 0:59a74b81fde8 34 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
Kjansen45 0:59a74b81fde8 35 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
Kjansen45 0:59a74b81fde8 36 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
Kjansen45 0:59a74b81fde8 37 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
Kjansen45 0:59a74b81fde8 38 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
Kjansen45 0:59a74b81fde8 39 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
Kjansen45 0:59a74b81fde8 40 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
Kjansen45 0:59a74b81fde8 41 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
Kjansen45 0:59a74b81fde8 42 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
Kjansen45 0:59a74b81fde8 43 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
Kjansen45 0:59a74b81fde8 44
Kjansen45 0:59a74b81fde8 45 uint8_t SDP_SDRAM_Init(void);
Kjansen45 0:59a74b81fde8 46 uint8_t SDP_SDRAM_DeInit(void);
Kjansen45 0:59a74b81fde8 47 void SDP_SDRAM_Setup(uint32_t RefreshCount);
Kjansen45 0:59a74b81fde8 48 uint8_t SDP_SDRAM_ReadData_8b(uint32_t pAddress, uint8_t *pData, uint32_t dataSize);
Kjansen45 0:59a74b81fde8 49 uint8_t SDP_SDRAM_ReadData_16b(uint32_t pAddress, uint16_t *pData, uint32_t dataSize);
Kjansen45 0:59a74b81fde8 50 uint8_t SDP_SDRAM_ReadData_32b(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
Kjansen45 0:59a74b81fde8 51 uint8_t SDP_SDRAM_ReadData_DMA(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
Kjansen45 1:c1da02c6a73c 52 uint8_t SDP_SDRAM_WriteData_8b(uint32_t pAddress, uint8_t *pData, uint32_t dataSize);
Kjansen45 1:c1da02c6a73c 53 uint8_t SDP_SDRAM_WriteData_16b(uint32_t pAddress, uint16_t *pData, uint32_t dataSize);
Kjansen45 1:c1da02c6a73c 54 uint8_t SDP_SDRAM_WriteData_32b(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
Kjansen45 0:59a74b81fde8 55 uint8_t SDP_SDRAM_WriteData_DMA(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
Kjansen45 0:59a74b81fde8 56 uint8_t SDP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
Kjansen45 0:59a74b81fde8 57 void SDP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
Kjansen45 0:59a74b81fde8 58 void SDP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
Kjansen45 0:59a74b81fde8 59
Kjansen45 0:59a74b81fde8 60 #ifdef __cplusplus
Kjansen45 0:59a74b81fde8 61 }
Kjansen45 0:59a74b81fde8 62 #endif
Kjansen45 0:59a74b81fde8 63
Kjansen45 0:59a74b81fde8 64 #endif