Analog Devices
/
sdp_k1_sdram
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sdp_k1_sdram.h
00001 #ifndef __SDPK1_SDRAM_H 00002 #define __SDPK1_SDRAM_H 00003 00004 #ifdef __cplusplus 00005 extern "C" { 00006 #endif 00007 00008 /* Includes ------------------------------------------------------------------*/ 00009 #include "stm32f4xx_hal.h" 00010 00011 00012 /** 00013 * @brief SDRAM status structure definition 00014 */ 00015 #define SDRAM_OK ((uint8_t)0x00) 00016 #define SDRAM_ERROR ((uint8_t)0x01) 00017 00018 #define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000) 00019 #define SDRAM_DEVICE_SIZE ((uint32_t)0x1000000) /* SDRAM device size in MBytes */ 00020 00021 /* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */ 00022 /* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 */ 00023 #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32 00024 00025 #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 00026 /* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ 00027 00028 #define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */ 00029 00030 #define SDRAM_TIMEOUT ((uint32_t)0xFFFF) 00031 00032 /* DMA definitions for SDRAM DMA transfer */ 00033 #define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 00034 #define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 00035 #define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0 00036 #define SDRAM_DMAx_STREAM DMA2_Stream0 00037 #define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn 00038 #define BSP_SDRAM_DMA_IRQHandler DMA2_Stream0_IRQHandler 00039 00040 /* SDRAM register defines */ 00041 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) 00042 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) 00043 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) 00044 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) 00045 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) 00046 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) 00047 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) 00048 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) 00049 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) 00050 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 00051 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) 00052 00053 /* SDP SDRAM Pin defines */ 00054 #define SDRAM_A0 GPIO_PIN_0 00055 #define SDRAM_A1 GPIO_PIN_1 00056 #define SDRAM_A2 GPIO_PIN_2 00057 #define SDRAM_A3 GPIO_PIN_3 00058 #define SDRAM_A4 GPIO_PIN_4 00059 #define SDRAM_A5 GPIO_PIN_5 00060 #define SDRAM_A6 GPIO_PIN_12 00061 #define SDRAM_A7 GPIO_PIN_13 00062 #define SDRAM_A8 GPIO_PIN_14 00063 #define SDRAM_A9 GPIO_PIN_15 00064 #define SDRAM_A10 GPIO_PIN_0 00065 #define SDRAM_A11 GPIO_PIN_1 00066 #define SDRAM_A12 GPIO_PIN_2 00067 #define SDRAM_A13 GPIO_PIN_3 00068 #define SDRAM_A14 GPIO_PIN_4 00069 #define SDRAM_A15 GPIO_PIN_5 00070 #define SDRAM_D0 GPIO_PIN_14 00071 #define SDRAM_D1 GPIO_PIN_15 00072 #define SDRAM_D2 GPIO_PIN_0 00073 #define SDRAM_D3 GPIO_PIN_1 00074 #define SDRAM_D4 GPIO_PIN_7 00075 #define SDRAM_D5 GPIO_PIN_8 00076 #define SDRAM_D6 GPIO_PIN_9 00077 #define SDRAM_D7 GPIO_PIN_10 00078 #define SDRAM_D8 GPIO_PIN_11 00079 #define SDRAM_D9 GPIO_PIN_12 00080 #define SDRAM_D10 GPIO_PIN_13 00081 #define SDRAM_D11 GPIO_PIN_14 00082 #define SDRAM_D12 GPIO_PIN_15 00083 #define SDRAM_D13 GPIO_PIN_8 00084 #define SDRAM_D14 GPIO_PIN_9 00085 #define SDRAM_D15 GPIO_PIN_10 00086 #define SDRAM_D16 GPIO_PIN_8 00087 #define SDRAM_D17 GPIO_PIN_9 00088 #define SDRAM_D18 GPIO_PIN_10 00089 #define SDRAM_D19 GPIO_PIN_11 00090 #define SDRAM_D20 GPIO_PIN_12 00091 #define SDRAM_D21 GPIO_PIN_13 00092 #define SDRAM_D22 GPIO_PIN_14 00093 #define SDRAM_D23 GPIO_PIN_15 00094 #define SDRAM_D24 GPIO_PIN_0 00095 #define SDRAM_D25 GPIO_PIN_1 00096 #define SDRAM_D26 GPIO_PIN_2 00097 #define SDRAM_D27 GPIO_PIN_3 00098 #define SDRAM_D28 GPIO_PIN_6 00099 #define SDRAM_D29 GPIO_PIN_7 00100 #define SDRAM_D30 GPIO_PIN_9 00101 #define SDRAM_D31 GPIO_PIN_10 00102 #define SDRAM_NBL0 GPIO_PIN_0 00103 #define SDRAM_NBL1 GPIO_PIN_1 00104 #define SDRAM_NBL2 GPIO_PIN_4 00105 #define SDRAM_NBL3 GPIO_PIN_5 00106 #define SDRAM_SDCLK GPIO_PIN_8 00107 #define SDRAM_N_CAS GPIO_PIN_15 00108 #define SDRAM_N_RAS GPIO_PIN_11 00109 #define SDRAM_SDCKE0 GPIO_PIN_2 00110 #define SDRAM_SDNE0 GPIO_PIN_3 00111 #define SDRAM_N_WE GPIO_PIN_5 00112 00113 uint8_t SDP_SDRAM_Init(void); 00114 uint8_t SDP_SDRAM_DeInit(void); 00115 void SDP_SDRAM_Initialization_sequence(uint32_t RefreshCount); 00116 uint8_t SDP_SDRAM_ReadData_8b(uint32_t pAddress, uint8_t *pData, uint32_t dataSize); 00117 uint8_t SDP_SDRAM_ReadData_16b(uint32_t pAddress, uint16_t *pData, uint32_t dataSize); 00118 uint8_t SDP_SDRAM_ReadData_32b(uint32_t pAddress, uint32_t *pData, uint32_t dataSize); 00119 uint8_t SDP_SDRAM_ReadData_DMA(uint32_t pAddress, uint32_t *pData, uint32_t dataSize); 00120 uint8_t SDP_SDRAM_WriteData_8b(uint32_t pAddress, uint8_t *pData, uint32_t dataSize); 00121 uint8_t SDP_SDRAM_WriteData_16b(uint32_t pAddress, uint16_t *pData, uint32_t dataSize); 00122 uint8_t SDP_SDRAM_WriteData_32b(uint32_t pAddress, uint32_t *pData, uint32_t dataSize); 00123 uint8_t SDP_SDRAM_WriteData_DMA(uint32_t pAddress, uint32_t *pData, uint32_t dataSize); 00124 uint8_t SDP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd); 00125 00126 /* These functions can be modified in case the current settings (e.g. DMA stream) 00127 need to be changed for specific application needs */ 00128 void SDP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params); 00129 void SDP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params); 00130 00131 #ifdef __cplusplus 00132 } 00133 #endif 00134 00135 #endif
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