ad77681_regs.c

00001 /***************************************************************************//**
00002  *   @file    ad77681_regs.c
00003  *   @brief   AD77681 registers map
00004  *   @details
00005 ********************************************************************************
00006  * Copyright (c) 2021 Analog Devices, Inc.
00007  * All rights reserved.
00008  *
00009  * This software is proprietary to Analog Devices, Inc. and its licensors.
00010  * By using this software you agree to the terms of the associated
00011  * Analog Devices Software License Agreement.
00012 *******************************************************************************/
00013 
00014 /******************************************************************************/
00015 /***************************** Include Files **********************************/
00016 /******************************************************************************/
00017 
00018 #include <stdint.h>
00019 #include "ad77681.h"
00020 
00021 /******************************************************************************/
00022 /*************************** Types Declarations *******************************/
00023 /******************************************************************************/
00024 
00025 const uint32_t ad77681_regs[] = {
00026     AD77681_REG_CHIP_TYPE,
00027     AD77681_REG_PROD_ID_L,
00028     AD77681_REG_PROD_ID_H,
00029     AD77681_REG_CHIP_GRADE,
00030     AD77681_REG_SCRATCH_PAD,
00031     AD77681_REG_VENDOR_L,
00032     AD77681_REG_VENDOR_H,
00033     AD77681_REG_INTERFACE_FORMAT,
00034     AD77681_REG_POWER_CLOCK,
00035     AD77681_REG_ANALOG,
00036     AD77681_REG_ANALOG2,
00037     AD77681_REG_CONVERSION,
00038     AD77681_REG_DIGITAL_FILTER,
00039     AD77681_REG_SINC3_DEC_RATE_MSB,
00040     AD77681_REG_SINC3_DEC_RATE_LSB,
00041     AD77681_REG_DUTY_CYCLE_RATIO,
00042     AD77681_REG_SYNC_RESET,
00043     AD77681_REG_GPIO_CONTROL,
00044     AD77681_REG_GPIO_WRITE,
00045     AD77681_REG_GPIO_READ,
00046     AD77681_REG_OFFSET_HI,
00047     AD77681_REG_OFFSET_MID,
00048     AD77681_REG_OFFSET_LO,
00049     AD77681_REG_GAIN_HI,
00050     AD77681_REG_GAIN_MID,
00051     AD77681_REG_GAIN_LO,
00052     AD77681_REG_SPI_DIAG_ENABLE,
00053     AD77681_REG_ADC_DIAG_ENABLE,
00054     AD77681_REG_DIG_DIAG_ENABLE,
00055     AD77681_REG_ADC_DATA,
00056     AD77681_REG_MASTER_STATUS,
00057     AD77681_REG_SPI_DIAG_STATUS,
00058     AD77681_REG_ADC_DIAG_STATUS,
00059     AD77681_REG_DIG_DIAG_STATUS,
00060     AD77681_REG_MCLK_COUNTER
00061 };
00062