ad469x.h

00001 /***************************************************************************//**
00002  *   @file   ad469x.h
00003  *   @brief  Header file for ad469x Driver.
00004  *   @author Cristian Pop (cristian.pop@analog.com)
00005 ********************************************************************************
00006  * Copyright 2021(c) Analog Devices, Inc.
00007  *
00008  * All rights reserved.
00009  *
00010  * Redistribution and use in source and binary forms, with or without
00011  * modification, are permitted provided that the following conditions are met:
00012  *  - Redistributions of source code must retain the above copyright
00013  *    notice, this list of conditions and the following disclaimer.
00014  *  - Redistributions in binary form must reproduce the above copyright
00015  *    notice, this list of conditions and the following disclaimer in
00016  *    the documentation and/or other materials provided with the
00017  *    distribution.
00018  *  - Neither the name of Analog Devices, Inc. nor the names of its
00019  *    contributors may be used to endorse or promote products derived
00020  *    from this software without specific prior written permission.
00021  *  - The use of this software may or may not infringe the patent rights
00022  *    of one or more patent holders.  This license does not release you
00023  *    from the requirement that you obtain separate licenses from these
00024  *    patent holders to use this software.
00025  *  - Use of the software either in source or binary form, must be run
00026  *    on or directly connected to an Analog Devices Inc. component.
00027  *
00028  * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
00029  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
00030  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
00031  * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
00032  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00033  * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
00034  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038 *******************************************************************************/
00039 
00040 #ifndef SRC_AD469X_H_
00041 #define SRC_AD469X_H_
00042 
00043 // **** Note for User: SPI Standard/Engine selection **** //
00044 /* By default the Standard SPI protocol is used for communicating with eval board. 
00045  * Uncomment the "ENABLE_SPI_ENGINE" macro to enable the SPI engine controller 
00046  * framework. 
00047  * */
00048 //#define ENABLE_SPI_ENGINE
00049 
00050 /******************************************************************************/
00051 /***************************** Include Files **********************************/
00052 /******************************************************************************/
00053 #include <stdlib.h>
00054 #include <stdbool.h>
00055 
00056 #if defined(ENABLE_SPI_ENGINE)
00057 #include "spi_engine.h"
00058 #include "clk_axi_clkgen.h"
00059 #include "pwm.h"
00060 #else
00061 #include "spi.h"
00062 #endif
00063 
00064 /******************************************************************************/
00065 /********************** Macros and Constants Definitions **********************/
00066 /******************************************************************************/
00067 /* AD469x registers */
00068 #define AD469x_REG_IF_CONFIG_A      0x000
00069 #define AD469x_REG_IF_CONFIG_B      0x001
00070 #define AD469x_REG_DEVICE_TYPE      0x003
00071 #define AD469x_REG_DEVICE_ID_L      0x004
00072 #define AD469x_REG_DEVICE_ID_H      0x005
00073 #define AD469x_REG_SCRATCH_PAD      0x00A
00074 #define AD469x_REG_VENDOR_L     0x00C
00075 #define AD469x_REG_VENDOR_H     0x00D
00076 #define AD469x_REG_LOOP_MODE        0x00E
00077 #define AD469x_REG_IF_CONFIG_C      0x010
00078 #define AD469x_REG_IF_STATUS        0x011
00079 #define AD469x_REG_STATUS       0x014
00080 #define AD469x_REG_ALERT_STATUS1    0x015
00081 #define AD469x_REG_ALERT_STATUS2    0x016
00082 #define AD469x_REG_ALERT_STATUS3    0x017
00083 #define AD469x_REG_ALERT_STATUS4    0x018
00084 #define AD469x_REG_CLAMP_STATUS1    0x01A
00085 #define AD469x_REG_CLAMP_STATUS2    0x01B
00086 #define AD469x_REG_SETUP        0x020
00087 #define AD469x_REG_REF_CTRL     0x021
00088 #define AD469x_REG_SEQ_CTRL     0x022
00089 #define AD469x_REG_AC_CTRL      0x023
00090 #define AD469x_REG_STD_SEQ_CONFIG   0x024
00091 #define AD469x_REG_GPIO_CTRL        0x026
00092 #define AD469x_REG_GP_MODE      0x027
00093 #define AD469x_REG_GPIO_STATE       0x028
00094 #define AD469x_REG_TEMP_CTRL        0x029
00095 #define AD469x_REG_CONFIG_IN(x)     ((x & 0x0F) | 0x30)
00096 #define AD469x_REG_AS_SLOT(x)       ((x & 0x7F) | 0x100)
00097 
00098 /* 5-bit SDI Conversion Mode Commands */
00099 #define AD469x_CMD_REG_CONFIG_MODE      (0x0A << 3)
00100 #define AD469x_CMD_SEL_TEMP_SNSOR_CH        (0x0F << 3)
00101 #define AD469x_CMD_CONFIG_CH_SEL(x)     ((0x10 | (0x0F & x)) << 3)
00102 
00103 /* AD469x_REG_SETUP */
00104 #define AD469x_SETUP_IF_MODE_MASK       (0x01 << 2)
00105 #define AD469x_SETUP_IF_MODE_CONV       (0x01 << 2)
00106 #define AD469x_SETUP_CYC_CTRL_MASK      (0x01 << 1)
00107 #define AD469x_SETUP_CYC_CTRL_SINGLE(x)     ((x & 0x01) << 1)
00108 //Changed 
00109 #define AD469x_SETUP_STATUSBIT_MODE_MASK        (0x01 << 5)
00110 #define AD469x_SETUP_STATUSBIT_MODE_CONV        (0x01 << 5)
00111 
00112 /* AD469x_REG_GP_MODE */
00113 #define AD469x_GP_MODE_BUSY_GP_EN_MASK      (0x01 << 1)
00114 #define AD469x_GP_MODE_BUSY_GP_EN(x)        ((x & 0x01) << 1)
00115 #define AD469x_GP_MODE_BUSY_GP_SEL_MASK     (0x01 << 4)
00116 #define AD469x_GP_MODE_BUSY_GP_SEL(x)       ((x & 0x01) << 4)
00117 
00118 /* AD469x_REG_SEQ_CTRL */
00119 #define AD469x_SEQ_CTRL_STD_SEQ_EN_MASK     (0x01 << 7)
00120 #define AD469x_SEQ_CTRL_STD_SEQ_EN(x)       ((x & 0x01) << 7)
00121 #define AD469x_SEQ_CTRL_NUM_SLOTS_AS_MASK   (0x7f << 0)
00122 #define AD469x_SEQ_CTRL_NUM_SLOTS_AS(x)     ((x & 0x7f) << 0)
00123 
00124 /* AD469x_REG_TEMP_CTRL */
00125 #define AD469x_REG_TEMP_CTRL_TEMP_EN_MASK   (0x01 << 0)
00126 #define AD469x_REG_TEMP_CTRL_TEMP_EN(x)     ((x & 0x01) << 0)
00127 
00128 /* AD469x_REG_AS_SLOT */
00129 #define AD469x_REG_AS_SLOT_INX(x)       ((x & 0x0f) << 0)
00130 
00131 /* AD469x_REG_IF_CONFIG_C */
00132 #define AD469x_REG_IF_CONFIG_C_MB_STRICT_MASK   (0x01 << 5)
00133 #define AD469x_REG_IF_CONFIG_C_MB_STRICT(x) ((x & 0x01) << 5)
00134 
00135 /* AD469x_REG_CONFIG_INn */
00136 #define AD469x_REG_CONFIG_IN_OSR_MASK       (0x03 << 0)
00137 #define AD469x_REG_CONFIG_IN_OSR(x)     ((x & 0x03) << 0)
00138 #define AD469x_REG_CONFIG_IN_HIZ_EN_MASK    (0x01 << 3)
00139 #define AD469x_REG_CONFIG_IN_HIZ_EN(x)      ((x & 0x01) << 3)
00140 #define AD469x_REG_CONFIG_IN_PAIR_MASK      (0x03 << 4)
00141 #define AD469x_REG_CONFIG_IN_PAIR(x)        ((x & 0x03) << 4)
00142 #define AD469x_REG_CONFIG_IN_MODE_MASK      (0x01 << 6)
00143 #define AD469x_REG_CONFIG_IN_MODE(x)        ((x & 0x01) << 6)
00144 #define AD469x_REG_CONFIG_IN_TD_EN_MASK     (0x01 << 7)
00145 #define AD469x_REG_CONFIG_IN_TD_EN(x)       ((x & 0x01) << 7)
00146 
00147 #define AD469x_CHANNEL(x)           (BIT(x) & 0xFFFF)
00148 #define AD469x_CHANNEL_NO           16
00149 #define AD469x_SLOTS_NO             0x80
00150 #define AD469x_CHANNEL_TEMP         16
00151 
00152 /******************************************************************************/
00153 /*************************** Types Declarations *******************************/
00154 /******************************************************************************/
00155 /**
00156  * @enum ad469x_channel_sequencing
00157  * @brief Channel sequencing modes
00158  */
00159 enum ad469x_channel_sequencing {
00160     /** Single cycle read */
00161     AD469x_single_cycle,
00162     /** Two cycle read */
00163     AD469x_two_cycle,
00164     /** Sequence trough channels, standard mode */
00165     AD469x_standard_seq,
00166     /** Sequence trough channels, advanced mode */
00167     AD469x_advanced_seq,
00168 };
00169 
00170 /**
00171   * @enum ad469x_busy_gp_sel
00172   * @brief Busy state, possible general purpose pin selections
00173   */
00174 enum ad469x_busy_gp_sel {
00175     /** Busy on gp0 */
00176     AD469x_busy_gp0 = 0,
00177     /** Busy on gp3 */
00178     AD469x_busy_gp3 = 1,
00179 };
00180 
00181 /**
00182   * @enum ad469x_reg_access
00183   * @brief Register access modes
00184   */
00185 enum ad469x_reg_access {
00186     AD469x_BYTE_ACCESS,
00187     AD469x_WORD_ACCESS,
00188 };
00189 
00190 /**
00191   * @enum ad469x_supported_dev_ids
00192   * @brief Supported devices
00193   */
00194 enum ad469x_supported_dev_ids {
00195     ID_AD4695,
00196     ID_AD4696,
00197     ID_AD4697,
00198 };
00199 
00200 /**
00201   * @enum ad469x_osr_ratios
00202   * @brief Supported oversampling ratios
00203   */
00204 enum ad469x_osr_ratios {
00205     AD469x_OSR_1,
00206     AD469x_OSR_4,
00207     AD469x_OSR_16,
00208     AD469x_OSR_64
00209 };
00210 
00211 /**
00212  * @struct ad469x_init_param
00213  * @brief  Structure containing the init parameters needed by the ad469x device
00214  */
00215 struct ad469x_init_param {
00216     /* SPI */
00217     spi_init_param      *spi_init;
00218     /* SPI module offload init */
00219     struct spi_engine_offload_init_param *offload_init_param;
00220     /* PWM generator init structure */
00221     struct pwm_init_param   *trigger_pwm_init;
00222     /** RESET GPIO initialization structure. */
00223     struct gpio_init_param  *gpio_resetn;
00224     //gpio_init_param * gpio_resetn;
00225     /** CONVST GPIO initialization parameters */
00226     struct gpio_init_param *gpio_convst;
00227     /** BUSY GPIO initialization parameters */
00228     struct gpio_init_param *gpio_busy;
00229     /* Clock gen for hdl design init structure */
00230     struct axi_clkgen_init  *clkgen_init;
00231     /* Clock generator rate */
00232     uint32_t        axi_clkgen_rate;
00233     /* Register access speed */
00234     uint32_t        reg_access_speed;
00235     /* Register data width */
00236     uint8_t     reg_data_width;
00237     /* Capture data width */
00238     uint8_t     capture_data_width;
00239     /* Device Settings */
00240     enum ad469x_supported_dev_ids dev_id;
00241     /** Invalidate the Data cache for the given address range */
00242     void(*dcache_invalidate_range)(uint32_t address, uint32_t bytes_count);
00243 };
00244 
00245 /**
00246  * @struct ad469x_dev
00247  * @brief  Structure representing an ad469x device
00248  */
00249 struct ad469x_dev {
00250     /* SPI descriptor */
00251     spi_desc        *spi_desc;
00252     /* Clock gen for hdl design structure */
00253     struct axi_clkgen   *clkgen;
00254     /* Trigger conversion PWM generator descriptor */
00255     struct pwm_desc     *trigger_pwm_desc;
00256     /* SPI module offload init */
00257     struct spi_engine_offload_init_param *offload_init_param;
00258     /* Register access speed */
00259     uint32_t        reg_access_speed;
00260     /* Register data width */
00261     uint8_t     reg_data_width;
00262     /* Capture data width */
00263     uint8_t     capture_data_width;
00264     /* Device Settings */
00265     enum ad469x_supported_dev_ids dev_id;
00266     /** RESET GPIO handler. */
00267     struct gpio_desc    *gpio_resetn;
00268     /** CONVST GPIO descriptor */
00269     struct gpio_desc *gpio_convst;
00270     /** BUSY GPIO descriptor */
00271     struct gpio_desc *gpio_busy;
00272     /** Invalidate the Data cache for the given address range */
00273     void(*dcache_invalidate_range)(uint32_t address, uint32_t bytes_count);
00274     /** Current channel sequence */
00275     enum ad469x_channel_sequencing ch_sequence;
00276     /** OSR resolution corresponding to each channel, when advanced
00277      * sequencer is selected. */
00278     enum ad469x_osr_ratios adv_seq_osr_resol[AD469x_CHANNEL_NO];
00279     /** Channel slots for advanced sequencer */
00280     uint8_t ch_slots[AD469x_SLOTS_NO];
00281     /** Temperature enabled for standard and advanced sequencer if set. */
00282     bool temp_enabled;
00283     /** Number of active channel slots, for advanced sequencer */
00284     uint8_t num_slots;
00285     /* Buffer to store the conv result */
00286     uint8_t data[16];
00287 };
00288 
00289 /******************************************************************************/
00290 /************************ Functions Declarations ******************************/
00291 /******************************************************************************/
00292 /* Read device register. */
00293 int32_t ad469x_spi_reg_read(struct ad469x_dev *dev,
00294     uint16_t reg_addr,
00295     uint8_t *reg_data);
00296 
00297 /* Write device register */
00298 int32_t ad469x_spi_reg_write(struct ad469x_dev *dev,
00299     uint16_t reg_addr,
00300     uint8_t reg_data);
00301 
00302 /* Read from device using a mask */
00303 int32_t ad469x_spi_read_mask(struct ad469x_dev *dev,
00304     uint16_t reg_addr,
00305     uint8_t mask,
00306     uint8_t *data);
00307 
00308 /* Write to device using a mask */
00309 int32_t ad469x_spi_write_mask(struct ad469x_dev *dev,
00310     uint16_t reg_addr,
00311     uint8_t mask,
00312     uint8_t data);
00313 
00314 /* Read data from device */
00315 int32_t ad469x_read_data(struct ad469x_dev *dev,
00316     uint8_t channel,
00317     uint32_t *buf,
00318     uint16_t samples);
00319 
00320 /* Read from device when converter has the channel sequencer activated */
00321 int32_t ad469x_seq_read_data(struct ad469x_dev *dev,
00322     uint32_t *buf,
00323     uint16_t samples);
00324 
00325 /* Set channel sequence */
00326 int32_t ad469x_set_channel_sequence(struct ad469x_dev *dev,
00327     enum ad469x_channel_sequencing seq);
00328 
00329 /* Configure standard sequencer enabled channels */
00330 int32_t ad469x_std_sequence_ch(struct ad469x_dev *dev,
00331     uint32_t ch_mask);
00332 
00333 /* Configure advanced sequencer number of slots */
00334 int32_t ad469x_adv_sequence_set_num_slots(struct ad469x_dev *dev,
00335     uint8_t num_slots);
00336 
00337 /* Advanced sequencer, assign channel to a slot */
00338 int32_t ad469x_adv_sequence_set_slot(struct ad469x_dev *dev,
00339     uint8_t slot,
00340     uint8_t channel);
00341 
00342 /* Enable temperature read at the end of the sequence, for standard and */
00343 int32_t ad469x_sequence_enable_temp(struct ad469x_dev *dev);
00344 
00345 /* Disable temperature read at the end of the sequence, for standard and */
00346 int32_t ad469x_sequence_disable_temp(struct ad469x_dev *dev);
00347 
00348 /* Configure over sampling ratio in advanced sequencer mode */
00349 int32_t ad469x_adv_seq_osr(struct ad469x_dev *dev,
00350     uint16_t ch,
00351     enum ad469x_osr_ratios ratio);
00352 
00353 /* Configure over sampling ratio in standard sequencer mode */
00354 int32_t ad469x_std_seq_osr(struct ad469x_dev *dev,
00355     enum ad469x_osr_ratios ratio);
00356 
00357 /* Enter conversion mode */
00358 int32_t ad469x_enter_conversion_mode(struct ad469x_dev *dev);
00359 
00360 /* Exit conversion mode */
00361 int32_t ad469x_exit_conversion_mode(struct ad469x_dev *dev);
00362 
00363 /* Initialize the device. */
00364 int32_t ad469x_init(struct ad469x_dev **device,
00365     struct ad469x_init_param *init_param);
00366 
00367 /* Remove the device and release resources. */
00368 int32_t ad469x_remove(struct ad469x_dev *dev);
00369 
00370 #endif /* SRC_AD469X_H_ */