Analog Devices / Mbed OS EVAL-AD4130

Example program for EVAL-AD4130

Dependencies:   tempsensors sdp_k1_sdram

app/ad4130_support.c@2:7b2b268ea49c, 22 months ago (annotated)

Committer:
Mahesh Phalke
Date:
Wed Jul 20 18:12:00 2022 +0530
Revision:
2:7b2b268ea49c
Initial firmware commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Mahesh Phalke 2:7b2b268ea49c 1 /*************************************************************************//**
Mahesh Phalke 2:7b2b268ea49c 2 * @file ad4130_support.c
Mahesh Phalke 2:7b2b268ea49c 3 * @brief AD4130 device No-OS driver supports
Mahesh Phalke 2:7b2b268ea49c 4 ******************************************************************************
Mahesh Phalke 2:7b2b268ea49c 5 * Copyright (c) 2020, 2022 Analog Devices, Inc.
Mahesh Phalke 2:7b2b268ea49c 6 * All rights reserved.
Mahesh Phalke 2:7b2b268ea49c 7 *
Mahesh Phalke 2:7b2b268ea49c 8 * This software is proprietary to Analog Devices, Inc. and its licensors.
Mahesh Phalke 2:7b2b268ea49c 9 * By using this software you agree to the terms of the associated
Mahesh Phalke 2:7b2b268ea49c 10 * Analog Devices Software License Agreement.
Mahesh Phalke 2:7b2b268ea49c 11 *****************************************************************************/
Mahesh Phalke 2:7b2b268ea49c 12
Mahesh Phalke 2:7b2b268ea49c 13 /******************************************************************************/
Mahesh Phalke 2:7b2b268ea49c 14 /***************************** Include Files **********************************/
Mahesh Phalke 2:7b2b268ea49c 15 /******************************************************************************/
Mahesh Phalke 2:7b2b268ea49c 16
Mahesh Phalke 2:7b2b268ea49c 17 #include <stdint.h>
Mahesh Phalke 2:7b2b268ea49c 18
Mahesh Phalke 2:7b2b268ea49c 19 #include "app_config.h"
Mahesh Phalke 2:7b2b268ea49c 20 #include "ad4130_support.h"
Mahesh Phalke 2:7b2b268ea49c 21 #include "no_os_error.h"
Mahesh Phalke 2:7b2b268ea49c 22
Mahesh Phalke 2:7b2b268ea49c 23 /******************************************************************************/
Mahesh Phalke 2:7b2b268ea49c 24 /********************** Macros and Constants Definition ***********************/
Mahesh Phalke 2:7b2b268ea49c 25 /******************************************************************************/
Mahesh Phalke 2:7b2b268ea49c 26
Mahesh Phalke 2:7b2b268ea49c 27 /* AD4130 FIFO size and readback command size in bytes */
Mahesh Phalke 2:7b2b268ea49c 28 #define AD4130_FIFO_MAX_SIZE (256)
Mahesh Phalke 2:7b2b268ea49c 29 #define AD4130_FIFO_READ_CMD_BYTES (2)
Mahesh Phalke 2:7b2b268ea49c 30
Mahesh Phalke 2:7b2b268ea49c 31 #define BYTE_SIZE (8)
Mahesh Phalke 2:7b2b268ea49c 32
Mahesh Phalke 2:7b2b268ea49c 33 /* Timeout to monitor CON monitor GPIO. The timeout count is dependent upon the
Mahesh Phalke 2:7b2b268ea49c 34 * MCU clock frequency. This timeout is tested for SDP-K1 Mbed controller platform */
Mahesh Phalke 2:7b2b268ea49c 35 #define CONV_MON_GPIO_TIMEOUT (10000)
Mahesh Phalke 2:7b2b268ea49c 36
Mahesh Phalke 2:7b2b268ea49c 37 /* Select between GPIO Or STATUS register to monitor the end
Mahesh Phalke 2:7b2b268ea49c 38 * of conversion in single conversion mode */
Mahesh Phalke 2:7b2b268ea49c 39 //#define CONV_MON_USING_RDY_STATUS // Uncomment to use STATUS reg
Mahesh Phalke 2:7b2b268ea49c 40
Mahesh Phalke 2:7b2b268ea49c 41 /* FIFO busy time as per specifications (in usec)
Mahesh Phalke 2:7b2b268ea49c 42 * Note : This time is stringent in FIFO readback.The minimum time period
Mahesh Phalke 2:7b2b268ea49c 43 * as per specifications is 20usec
Mahesh Phalke 2:7b2b268ea49c 44 */
Mahesh Phalke 2:7b2b268ea49c 45 #define FIFO_BUSY_TIME (20)
Mahesh Phalke 2:7b2b268ea49c 46
Mahesh Phalke 2:7b2b268ea49c 47 /******************************************************************************/
Mahesh Phalke 2:7b2b268ea49c 48 /********************** Variables and User Defined Data Types *****************/
Mahesh Phalke 2:7b2b268ea49c 49 /******************************************************************************/
Mahesh Phalke 2:7b2b268ea49c 50
Mahesh Phalke 2:7b2b268ea49c 51 /* AD4130 FIFO readback buffer.
Mahesh Phalke 2:7b2b268ea49c 52 * Size for 24-bit ADC = (256 * 3) + 2 = 770 bytes
Mahesh Phalke 2:7b2b268ea49c 53 * Size for 16-bit ADC = (256 * 2) + 2 = 514 bytes
Mahesh Phalke 2:7b2b268ea49c 54 * */
Mahesh Phalke 2:7b2b268ea49c 55 static uint8_t fifo_buf[(AD4130_FIFO_MAX_SIZE * (ADC_RESOLUTION / BYTE_SIZE)) +
Mahesh Phalke 2:7b2b268ea49c 56 AD4130_FIFO_READ_CMD_BYTES];
Mahesh Phalke 2:7b2b268ea49c 57
Mahesh Phalke 2:7b2b268ea49c 58 /******************************************************************************/
Mahesh Phalke 2:7b2b268ea49c 59 /************************ Functions Definitions *******************************/
Mahesh Phalke 2:7b2b268ea49c 60 /******************************************************************************/
Mahesh Phalke 2:7b2b268ea49c 61
Mahesh Phalke 2:7b2b268ea49c 62 /*!
Mahesh Phalke 2:7b2b268ea49c 63 * @brief Get reference voltage based on the reference source
Mahesh Phalke 2:7b2b268ea49c 64 * @param dev[in] - Device instance
Mahesh Phalke 2:7b2b268ea49c 65 * @param chn[in] - ADC channel
Mahesh Phalke 2:7b2b268ea49c 66 * @return Reference voltage
Mahesh Phalke 2:7b2b268ea49c 67 */
Mahesh Phalke 2:7b2b268ea49c 68 float ad4130_get_reference_voltage(struct ad413x_dev *dev, uint8_t chn)
Mahesh Phalke 2:7b2b268ea49c 69 {
Mahesh Phalke 2:7b2b268ea49c 70 float ref_voltage;
Mahesh Phalke 2:7b2b268ea49c 71 uint8_t preset = dev->ch[chn].preset;
Mahesh Phalke 2:7b2b268ea49c 72 enum ad413x_ref_sel ref = dev->preset[preset].ref_sel;
Mahesh Phalke 2:7b2b268ea49c 73 enum ad413x_int_ref int_ref = dev->int_ref;
Mahesh Phalke 2:7b2b268ea49c 74
Mahesh Phalke 2:7b2b268ea49c 75 switch (ref) {
Mahesh Phalke 2:7b2b268ea49c 76 case AD413X_REFIN1:
Mahesh Phalke 2:7b2b268ea49c 77 ref_voltage = AD4130_REFIN1_VOLTAGE;
Mahesh Phalke 2:7b2b268ea49c 78 break;
Mahesh Phalke 2:7b2b268ea49c 79
Mahesh Phalke 2:7b2b268ea49c 80 case AD413X_REFIN2:
Mahesh Phalke 2:7b2b268ea49c 81 ref_voltage = AD4130_REFIN2_VOLTAGE;
Mahesh Phalke 2:7b2b268ea49c 82 break;
Mahesh Phalke 2:7b2b268ea49c 83
Mahesh Phalke 2:7b2b268ea49c 84 case AD413X_AVDD_AVSS:
Mahesh Phalke 2:7b2b268ea49c 85 ref_voltage = AD4130_AVDD_VOLTAGE;
Mahesh Phalke 2:7b2b268ea49c 86 break;
Mahesh Phalke 2:7b2b268ea49c 87
Mahesh Phalke 2:7b2b268ea49c 88 case AD413X_REFOUT_AVSS:
Mahesh Phalke 2:7b2b268ea49c 89 if (int_ref == AD413X_INTREF_1_25V) {
Mahesh Phalke 2:7b2b268ea49c 90 ref_voltage = AD4170_1_25V_INT_REF_VOLTAGE;
Mahesh Phalke 2:7b2b268ea49c 91 } else {
Mahesh Phalke 2:7b2b268ea49c 92 ref_voltage = AD4170_2_5V_INT_REF_VOLTAGE;
Mahesh Phalke 2:7b2b268ea49c 93 }
Mahesh Phalke 2:7b2b268ea49c 94 break;
Mahesh Phalke 2:7b2b268ea49c 95
Mahesh Phalke 2:7b2b268ea49c 96 default:
Mahesh Phalke 2:7b2b268ea49c 97 ref_voltage = AD4170_2_5V_INT_REF_VOLTAGE;
Mahesh Phalke 2:7b2b268ea49c 98 break;
Mahesh Phalke 2:7b2b268ea49c 99 }
Mahesh Phalke 2:7b2b268ea49c 100
Mahesh Phalke 2:7b2b268ea49c 101 return ref_voltage;
Mahesh Phalke 2:7b2b268ea49c 102 }
Mahesh Phalke 2:7b2b268ea49c 103
Mahesh Phalke 2:7b2b268ea49c 104 /*!
Mahesh Phalke 2:7b2b268ea49c 105 * @brief Perform the sign conversion for handling negative voltages in
Mahesh Phalke 2:7b2b268ea49c 106 * bipolar mode
Mahesh Phalke 2:7b2b268ea49c 107 * @param dev[in] - Device instance
Mahesh Phalke 2:7b2b268ea49c 108 * @param adc_raw_data[in] - ADC raw value
Mahesh Phalke 2:7b2b268ea49c 109 * @param chn[in] - ADC Channel
Mahesh Phalke 2:7b2b268ea49c 110 * @return ADC data after signed conversion
Mahesh Phalke 2:7b2b268ea49c 111 */
Mahesh Phalke 2:7b2b268ea49c 112 int32_t perform_sign_conversion(struct ad413x_dev *dev, uint32_t adc_raw_data,
Mahesh Phalke 2:7b2b268ea49c 113 uint8_t chn)
Mahesh Phalke 2:7b2b268ea49c 114 {
Mahesh Phalke 2:7b2b268ea49c 115 int32_t adc_data;
Mahesh Phalke 2:7b2b268ea49c 116 bool bipolar = dev->bipolar;
Mahesh Phalke 2:7b2b268ea49c 117
Mahesh Phalke 2:7b2b268ea49c 118 /* Bipolar ADC Range: (-FS) <-> 0 <-> (+FS) : 0 <-> 2^(ADC_RES-1)-1 <-> 2^(ADC_RES-1)
Mahesh Phalke 2:7b2b268ea49c 119 Unipolar ADC Range: 0 <-> (+FS) : 0 <-> 2^ADC_RES
Mahesh Phalke 2:7b2b268ea49c 120 **/
Mahesh Phalke 2:7b2b268ea49c 121 if (bipolar) {
Mahesh Phalke 2:7b2b268ea49c 122 /* Data output format is offset binary for bipolar mode */
Mahesh Phalke 2:7b2b268ea49c 123 adc_data = adc_raw_data - ADC_MAX_COUNT_BIPOLAR;
Mahesh Phalke 2:7b2b268ea49c 124 } else {
Mahesh Phalke 2:7b2b268ea49c 125 /* Data output format is straight binary for unipolar mode */
Mahesh Phalke 2:7b2b268ea49c 126 adc_data = adc_raw_data;
Mahesh Phalke 2:7b2b268ea49c 127 }
Mahesh Phalke 2:7b2b268ea49c 128
Mahesh Phalke 2:7b2b268ea49c 129 return adc_data;
Mahesh Phalke 2:7b2b268ea49c 130 }
Mahesh Phalke 2:7b2b268ea49c 131
Mahesh Phalke 2:7b2b268ea49c 132 /*!
Mahesh Phalke 2:7b2b268ea49c 133 * @brief Convert the ADC raw value into equivalent voltage
Mahesh Phalke 2:7b2b268ea49c 134 * @param dev[in] - Device instance
Mahesh Phalke 2:7b2b268ea49c 135 * @param adc_raw[in]- ADC raw data
Mahesh Phalke 2:7b2b268ea49c 136 * @param chn[in] - ADC channel
Mahesh Phalke 2:7b2b268ea49c 137 * @return ADC voltage value
Mahesh Phalke 2:7b2b268ea49c 138 */
Mahesh Phalke 2:7b2b268ea49c 139 float convert_adc_sample_into_voltage(void *dev, uint32_t adc_raw,
Mahesh Phalke 2:7b2b268ea49c 140 uint8_t chn)
Mahesh Phalke 2:7b2b268ea49c 141 {
Mahesh Phalke 2:7b2b268ea49c 142 enum ad413x_gain pga;
Mahesh Phalke 2:7b2b268ea49c 143 float vref;
Mahesh Phalke 2:7b2b268ea49c 144 int32_t adc_data;
Mahesh Phalke 2:7b2b268ea49c 145 uint8_t preset = ((struct ad413x_dev *)dev)->ch[chn].preset;
Mahesh Phalke 2:7b2b268ea49c 146 bool bipolar = ((struct ad413x_dev *)dev)->bipolar;
Mahesh Phalke 2:7b2b268ea49c 147
Mahesh Phalke 2:7b2b268ea49c 148 pga = ((struct ad413x_dev *)dev)->preset[preset].gain;
Mahesh Phalke 2:7b2b268ea49c 149 vref = ad4130_get_reference_voltage(dev, chn);
Mahesh Phalke 2:7b2b268ea49c 150 adc_data = perform_sign_conversion(dev, adc_raw, chn);
Mahesh Phalke 2:7b2b268ea49c 151
Mahesh Phalke 2:7b2b268ea49c 152 if (bipolar) {
Mahesh Phalke 2:7b2b268ea49c 153 return (adc_data * (vref / (ADC_MAX_COUNT_BIPOLAR * (1 << pga))));
Mahesh Phalke 2:7b2b268ea49c 154 } else {
Mahesh Phalke 2:7b2b268ea49c 155 return (adc_data * (vref / (ADC_MAX_COUNT_UNIPOLAR * (1 << pga))));
Mahesh Phalke 2:7b2b268ea49c 156 }
Mahesh Phalke 2:7b2b268ea49c 157 }
Mahesh Phalke 2:7b2b268ea49c 158
Mahesh Phalke 2:7b2b268ea49c 159 /*!
Mahesh Phalke 2:7b2b268ea49c 160 * @brief Convert the ADC raw value into equivalent RTD resistance
Mahesh Phalke 2:7b2b268ea49c 161 * @param dev[in] - Device instance
Mahesh Phalke 2:7b2b268ea49c 162 * @param adc_raw[in] - ADC raw sample
Mahesh Phalke 2:7b2b268ea49c 163 * @param rtd_ref[in] - RTD reference resistance in ohms
Mahesh Phalke 2:7b2b268ea49c 164 * @param chn[in] - ADC channel
Mahesh Phalke 2:7b2b268ea49c 165 * @return RTD resistance value
Mahesh Phalke 2:7b2b268ea49c 166 * @note RTD is biased with constant excitation current. Below formula
Mahesh Phalke 2:7b2b268ea49c 167 * is based on ratiometric measurement, where fixed value of RTD RREF
Mahesh Phalke 2:7b2b268ea49c 168 * (reference resistor) and gain is taken into account
Mahesh Phalke 2:7b2b268ea49c 169 */
Mahesh Phalke 2:7b2b268ea49c 170 float convert_adc_raw_into_rtd_resistance(void *dev, uint32_t adc_raw,
Mahesh Phalke 2:7b2b268ea49c 171 float rtd_ref, uint8_t chn)
Mahesh Phalke 2:7b2b268ea49c 172 {
Mahesh Phalke 2:7b2b268ea49c 173 enum ad413x_gain pga;
Mahesh Phalke 2:7b2b268ea49c 174 int32_t adc_data;
Mahesh Phalke 2:7b2b268ea49c 175 uint8_t preset = ((struct ad413x_dev *)dev)->ch[chn].preset;
Mahesh Phalke 2:7b2b268ea49c 176 bool bipolar = ((struct ad413x_dev *)dev)->bipolar;
Mahesh Phalke 2:7b2b268ea49c 177
Mahesh Phalke 2:7b2b268ea49c 178 pga = ((struct ad413x_dev *)dev)->preset[preset].gain;
Mahesh Phalke 2:7b2b268ea49c 179 adc_data = perform_sign_conversion(dev, adc_raw, chn);
Mahesh Phalke 2:7b2b268ea49c 180
Mahesh Phalke 2:7b2b268ea49c 181 if (bipolar) {
Mahesh Phalke 2:7b2b268ea49c 182 return (((float)adc_data * rtd_ref) / (ADC_MAX_COUNT_BIPOLAR * (1 << pga)));
Mahesh Phalke 2:7b2b268ea49c 183 } else {
Mahesh Phalke 2:7b2b268ea49c 184 return (((float)adc_data * rtd_ref) / (ADC_MAX_COUNT_UNIPOLAR * (1 << pga)));
Mahesh Phalke 2:7b2b268ea49c 185 }
Mahesh Phalke 2:7b2b268ea49c 186 }
Mahesh Phalke 2:7b2b268ea49c 187
Mahesh Phalke 2:7b2b268ea49c 188 /*!
Mahesh Phalke 2:7b2b268ea49c 189 * @brief Function to monitor end of conversion and read
Mahesh Phalke 2:7b2b268ea49c 190 * conversion result
Mahesh Phalke 2:7b2b268ea49c 191 * @param dev[in] - Device instance
Mahesh Phalke 2:7b2b268ea49c 192 * @param raw_data[in, out]- ADC raw data
Mahesh Phalke 2:7b2b268ea49c 193 * @return 0 in case of success, negative error code otherwise
Mahesh Phalke 2:7b2b268ea49c 194 */
Mahesh Phalke 2:7b2b268ea49c 195 int32_t ad413x_mon_conv_and_read_data(struct ad413x_dev *dev,
Mahesh Phalke 2:7b2b268ea49c 196 uint32_t *raw_data)
Mahesh Phalke 2:7b2b268ea49c 197 {
Mahesh Phalke 2:7b2b268ea49c 198 int32_t ret;
Mahesh Phalke 2:7b2b268ea49c 199 uint8_t conv_mon = 0;
Mahesh Phalke 2:7b2b268ea49c 200 uint32_t timeout = CONV_MON_GPIO_TIMEOUT;
Mahesh Phalke 2:7b2b268ea49c 201
Mahesh Phalke 2:7b2b268ea49c 202 if (!dev || !raw_data) {
Mahesh Phalke 2:7b2b268ea49c 203 return -EINVAL;
Mahesh Phalke 2:7b2b268ea49c 204 }
Mahesh Phalke 2:7b2b268ea49c 205
Mahesh Phalke 2:7b2b268ea49c 206 /* Wait for conversion */
Mahesh Phalke 2:7b2b268ea49c 207 #if defined(CONV_MON_USING_RDY_STATUS)
Mahesh Phalke 2:7b2b268ea49c 208 while (!conv_mon && timeout--) {
Mahesh Phalke 2:7b2b268ea49c 209 /* Read the value of the Status Register */
Mahesh Phalke 2:7b2b268ea49c 210 ret = ad413x_reg_read(dev, AD413X_REG_STATUS, raw_data);
Mahesh Phalke 2:7b2b268ea49c 211 if (ret) {
Mahesh Phalke 2:7b2b268ea49c 212 return ret;
Mahesh Phalke 2:7b2b268ea49c 213 }
Mahesh Phalke 2:7b2b268ea49c 214
Mahesh Phalke 2:7b2b268ea49c 215 /* Check the RDY bit in the Status Register */
Mahesh Phalke 2:7b2b268ea49c 216 conv_mon = (*raw_data & AD413X_ADC_DATA_STATUS);
Mahesh Phalke 2:7b2b268ea49c 217 }
Mahesh Phalke 2:7b2b268ea49c 218
Mahesh Phalke 2:7b2b268ea49c 219 if (!timeout) {
Mahesh Phalke 2:7b2b268ea49c 220 return -EIO;
Mahesh Phalke 2:7b2b268ea49c 221 }
Mahesh Phalke 2:7b2b268ea49c 222
Mahesh Phalke 2:7b2b268ea49c 223 /* Read the conversion result */
Mahesh Phalke 2:7b2b268ea49c 224 ret = ad413x_reg_read(dev, AD413X_REG_DATA, raw_data);
Mahesh Phalke 2:7b2b268ea49c 225 if (ret) {
Mahesh Phalke 2:7b2b268ea49c 226 return ret;
Mahesh Phalke 2:7b2b268ea49c 227 }
Mahesh Phalke 2:7b2b268ea49c 228 #else
Mahesh Phalke 2:7b2b268ea49c 229 conv_mon = NO_OS_GPIO_HIGH;
Mahesh Phalke 2:7b2b268ea49c 230 while (conv_mon == NO_OS_GPIO_HIGH && timeout--) {
Mahesh Phalke 2:7b2b268ea49c 231 ret = no_os_gpio_get_value(conv_mon_gpio_desc, &conv_mon);
Mahesh Phalke 2:7b2b268ea49c 232 if (ret) {
Mahesh Phalke 2:7b2b268ea49c 233 return ret;
Mahesh Phalke 2:7b2b268ea49c 234 }
Mahesh Phalke 2:7b2b268ea49c 235 }
Mahesh Phalke 2:7b2b268ea49c 236
Mahesh Phalke 2:7b2b268ea49c 237 if (!timeout) {
Mahesh Phalke 2:7b2b268ea49c 238 return -EIO;
Mahesh Phalke 2:7b2b268ea49c 239 }
Mahesh Phalke 2:7b2b268ea49c 240
Mahesh Phalke 2:7b2b268ea49c 241 /* Read the conversion result */
Mahesh Phalke 2:7b2b268ea49c 242 ret = ad413x_reg_read(dev, AD413X_REG_DATA, raw_data);
Mahesh Phalke 2:7b2b268ea49c 243 if (ret) {
Mahesh Phalke 2:7b2b268ea49c 244 return ret;
Mahesh Phalke 2:7b2b268ea49c 245 }
Mahesh Phalke 2:7b2b268ea49c 246
Mahesh Phalke 2:7b2b268ea49c 247 conv_mon = NO_OS_GPIO_LOW;
Mahesh Phalke 2:7b2b268ea49c 248 timeout = CONV_MON_GPIO_TIMEOUT;
Mahesh Phalke 2:7b2b268ea49c 249 while (conv_mon == NO_OS_GPIO_LOW && timeout--) {
Mahesh Phalke 2:7b2b268ea49c 250 ret = no_os_gpio_get_value(conv_mon_gpio_desc, &conv_mon);
Mahesh Phalke 2:7b2b268ea49c 251 if (ret) {
Mahesh Phalke 2:7b2b268ea49c 252 return ret;
Mahesh Phalke 2:7b2b268ea49c 253 }
Mahesh Phalke 2:7b2b268ea49c 254 }
Mahesh Phalke 2:7b2b268ea49c 255
Mahesh Phalke 2:7b2b268ea49c 256 if (!timeout) {
Mahesh Phalke 2:7b2b268ea49c 257 return -EIO;
Mahesh Phalke 2:7b2b268ea49c 258 }
Mahesh Phalke 2:7b2b268ea49c 259 #endif
Mahesh Phalke 2:7b2b268ea49c 260
Mahesh Phalke 2:7b2b268ea49c 261 return 0;
Mahesh Phalke 2:7b2b268ea49c 262 }
Mahesh Phalke 2:7b2b268ea49c 263
Mahesh Phalke 2:7b2b268ea49c 264 /*!
Mahesh Phalke 2:7b2b268ea49c 265 * @brief Read the data from FIFO
Mahesh Phalke 2:7b2b268ea49c 266 * @param dev[in] - device instance
Mahesh Phalke 2:7b2b268ea49c 267 * @param data[in] - Buffer to store FIFO data
Mahesh Phalke 2:7b2b268ea49c 268 * @param adc_samples[in] - Number of ADC samples to read
Mahesh Phalke 2:7b2b268ea49c 269 * @return 0 in case of success, negative error code otherwise
Mahesh Phalke 2:7b2b268ea49c 270 * @note This function doesn't consider the FIFO status and header information
Mahesh Phalke 2:7b2b268ea49c 271 * during data readback. It is assumed data user is intending to read
Mahesh Phalke 2:7b2b268ea49c 272 * only the data from FIFO.
Mahesh Phalke 2:7b2b268ea49c 273 */
Mahesh Phalke 2:7b2b268ea49c 274 int32_t ad4130_read_fifo(struct ad413x_dev *dev, uint32_t *data,
Mahesh Phalke 2:7b2b268ea49c 275 uint32_t adc_samples)
Mahesh Phalke 2:7b2b268ea49c 276 {
Mahesh Phalke 2:7b2b268ea49c 277 int32_t ret;
Mahesh Phalke 2:7b2b268ea49c 278 uint32_t loop_cntr;
Mahesh Phalke 2:7b2b268ea49c 279 uint32_t buf_indx = 0;
Mahesh Phalke 2:7b2b268ea49c 280 uint32_t bytes;
Mahesh Phalke 2:7b2b268ea49c 281
Mahesh Phalke 2:7b2b268ea49c 282 if (!dev || !data) {
Mahesh Phalke 2:7b2b268ea49c 283 return -EINVAL;
Mahesh Phalke 2:7b2b268ea49c 284 }
Mahesh Phalke 2:7b2b268ea49c 285
Mahesh Phalke 2:7b2b268ea49c 286 /* Watermark count of 0 implies full FIFO readback */
Mahesh Phalke 2:7b2b268ea49c 287 if ((adc_samples == 0) || (adc_samples > AD4130_FIFO_MAX_SIZE)) {
Mahesh Phalke 2:7b2b268ea49c 288 adc_samples = AD4130_FIFO_MAX_SIZE;
Mahesh Phalke 2:7b2b268ea49c 289 }
Mahesh Phalke 2:7b2b268ea49c 290
Mahesh Phalke 2:7b2b268ea49c 291 /* Delay b/w interrupt trigger and FIFO readback start */
Mahesh Phalke 2:7b2b268ea49c 292 no_os_udelay(FIFO_BUSY_TIME);
Mahesh Phalke 2:7b2b268ea49c 293
Mahesh Phalke 2:7b2b268ea49c 294 /* MOSI pin outputs 0x00 during FIFO data readback */
Mahesh Phalke 2:7b2b268ea49c 295 memset(fifo_buf, 0, sizeof(fifo_buf));
Mahesh Phalke 2:7b2b268ea49c 296
Mahesh Phalke 2:7b2b268ea49c 297 /* Enter into FIFO read mode by issuing dummy read command. Command consists of first byte as
Mahesh Phalke 2:7b2b268ea49c 298 * address of FIFO data register and 2nd byte as number of samples to read from FIFO */
Mahesh Phalke 2:7b2b268ea49c 299 fifo_buf[0] = AD413X_COMM_REG_RD | AD413X_ADDR(AD413X_REG_FIFO_DATA);
Mahesh Phalke 2:7b2b268ea49c 300 fifo_buf[1] = adc_samples;
Mahesh Phalke 2:7b2b268ea49c 301
Mahesh Phalke 2:7b2b268ea49c 302 /* Bytes to read = (samples * data size) + fifo data reg address + sample_cnt */
Mahesh Phalke 2:7b2b268ea49c 303 bytes = (adc_samples * (ADC_RESOLUTION / BYTE_SIZE)) +
Mahesh Phalke 2:7b2b268ea49c 304 AD4130_FIFO_READ_CMD_BYTES;
Mahesh Phalke 2:7b2b268ea49c 305
Mahesh Phalke 2:7b2b268ea49c 306 /* Read all bytes over SPI */
Mahesh Phalke 2:7b2b268ea49c 307 ret = no_os_spi_write_and_read(dev->spi_dev, fifo_buf, bytes);
Mahesh Phalke 2:7b2b268ea49c 308 if (ret) {
Mahesh Phalke 2:7b2b268ea49c 309 return ret;
Mahesh Phalke 2:7b2b268ea49c 310 }
Mahesh Phalke 2:7b2b268ea49c 311
Mahesh Phalke 2:7b2b268ea49c 312 /* Extract the data from buffer (data doesn't contain header/status info) */
Mahesh Phalke 2:7b2b268ea49c 313 for (loop_cntr = AD4130_FIFO_READ_CMD_BYTES; loop_cntr < bytes;
Mahesh Phalke 2:7b2b268ea49c 314 loop_cntr += (ADC_RESOLUTION / BYTE_SIZE)) {
Mahesh Phalke 2:7b2b268ea49c 315 #if (ADC_RESOLUTION == 24)
Mahesh Phalke 2:7b2b268ea49c 316 data[buf_indx++] = ((int32_t)fifo_buf[loop_cntr] << 16) |
Mahesh Phalke 2:7b2b268ea49c 317 ((int32_t)fifo_buf[loop_cntr + 1] << 8) |
Mahesh Phalke 2:7b2b268ea49c 318 (int32_t)fifo_buf[loop_cntr + 2];
Mahesh Phalke 2:7b2b268ea49c 319 #else
Mahesh Phalke 2:7b2b268ea49c 320 /* For 16-bit resolution */
Mahesh Phalke 2:7b2b268ea49c 321 data[buf_indx++] = ((int32_t)fifo_buf[loop_cntr] << 8) |
Mahesh Phalke 2:7b2b268ea49c 322 (int32_t)fifo_buf[loop_cntr + 1];
Mahesh Phalke 2:7b2b268ea49c 323 #endif
Mahesh Phalke 2:7b2b268ea49c 324 }
Mahesh Phalke 2:7b2b268ea49c 325
Mahesh Phalke 2:7b2b268ea49c 326 return 0;
Mahesh Phalke 2:7b2b268ea49c 327 }
Mahesh Phalke 2:7b2b268ea49c 328
Mahesh Phalke 2:7b2b268ea49c 329 /*!
Mahesh Phalke 2:7b2b268ea49c 330 * @brief Set interrupt conversion source (GPIO)
Mahesh Phalke 2:7b2b268ea49c 331 * @param dev[in] - Device instance
Mahesh Phalke 2:7b2b268ea49c 332 * @param conv_int_source[in]- Interrupt source
Mahesh Phalke 2:7b2b268ea49c 333 * @return 0 in case of success, negative error code otherwise
Mahesh Phalke 2:7b2b268ea49c 334 */
Mahesh Phalke 2:7b2b268ea49c 335 int32_t ad413x_set_int_source(struct ad413x_dev *dev,
Mahesh Phalke 2:7b2b268ea49c 336 adc_conv_int_source_e conv_int_source)
Mahesh Phalke 2:7b2b268ea49c 337 {
Mahesh Phalke 2:7b2b268ea49c 338 int32_t ret;
Mahesh Phalke 2:7b2b268ea49c 339
Mahesh Phalke 2:7b2b268ea49c 340 if (!dev) {
Mahesh Phalke 2:7b2b268ea49c 341 return -EINVAL;
Mahesh Phalke 2:7b2b268ea49c 342 }
Mahesh Phalke 2:7b2b268ea49c 343
Mahesh Phalke 2:7b2b268ea49c 344 ret = ad413x_reg_write_msk(dev,
Mahesh Phalke 2:7b2b268ea49c 345 AD413X_REG_IO_CTRL,
Mahesh Phalke 2:7b2b268ea49c 346 AD413X_INT_PIN_SEL(conv_int_source),
Mahesh Phalke 2:7b2b268ea49c 347 AD4130_INT_SRC_SEL_MSK);
Mahesh Phalke 2:7b2b268ea49c 348 if (ret) {
Mahesh Phalke 2:7b2b268ea49c 349 return ret;
Mahesh Phalke 2:7b2b268ea49c 350 }
Mahesh Phalke 2:7b2b268ea49c 351
Mahesh Phalke 2:7b2b268ea49c 352 return 0;
Mahesh Phalke 2:7b2b268ea49c 353 }
Mahesh Phalke 2:7b2b268ea49c 354
Mahesh Phalke 2:7b2b268ea49c 355 /*!
Mahesh Phalke 2:7b2b268ea49c 356 * @brief Set filter FS value
Mahesh Phalke 2:7b2b268ea49c 357 * @param dev[in] - Device instance
Mahesh Phalke 2:7b2b268ea49c 358 * @param fs[in]- FS value
Mahesh Phalke 2:7b2b268ea49c 359 * @param preset[in] - Channel setup
Mahesh Phalke 2:7b2b268ea49c 360 * @return 0 in case of success, negative error code otherwise
Mahesh Phalke 2:7b2b268ea49c 361 */
Mahesh Phalke 2:7b2b268ea49c 362 int32_t ad413x_set_filter_fs(struct ad413x_dev *dev, uint32_t fs,
Mahesh Phalke 2:7b2b268ea49c 363 uint8_t preset)
Mahesh Phalke 2:7b2b268ea49c 364 {
Mahesh Phalke 2:7b2b268ea49c 365 int32_t ret;
Mahesh Phalke 2:7b2b268ea49c 366
Mahesh Phalke 2:7b2b268ea49c 367 if (!dev) {
Mahesh Phalke 2:7b2b268ea49c 368 return -EINVAL;
Mahesh Phalke 2:7b2b268ea49c 369 }
Mahesh Phalke 2:7b2b268ea49c 370
Mahesh Phalke 2:7b2b268ea49c 371 ret = ad413x_reg_write_msk(dev,
Mahesh Phalke 2:7b2b268ea49c 372 AD413X_REG_FILTER(preset),
Mahesh Phalke 2:7b2b268ea49c 373 AD413X_FS_N(fs),
Mahesh Phalke 2:7b2b268ea49c 374 AD4130_FILTER_FS_MSK);
Mahesh Phalke 2:7b2b268ea49c 375 if (ret) {
Mahesh Phalke 2:7b2b268ea49c 376 return ret;
Mahesh Phalke 2:7b2b268ea49c 377 }
Mahesh Phalke 2:7b2b268ea49c 378
Mahesh Phalke 2:7b2b268ea49c 379 return 0;
Mahesh Phalke 2:7b2b268ea49c 380 }