Analog Devices
Library files for AD1234.
Diff: ADE120x.h
- Revision:
- 2:f9a986799375
- Parent:
- 1:2eb9d6296ec3
- Child:
- 3:6c708642886d
--- a/ADE120x.h Thu Oct 03 15:05:59 2019 +0000
+++ b/ADE120x.h Tue Oct 15 12:06:51 2019 +0000
@@ -3,7 +3,7 @@
* @brief ADE120x library. This file contains all ADE120x library functions.
* @version V0.0.1
* @author ADI
- * @date May 2019
+ * @date October 2019
* @par Revision History:
*
* Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved.
@@ -12,6 +12,7 @@
* By using this software you agree to the terms of the associated
* Analog Devices Software License Agreement.
**/
+
#ifndef _ADE120x_h_
#define _ADE120x_h_
@@ -22,54 +23,63 @@
#include "mbed.h"
-/** @addtogroup ADE120x_Library
- * @{
- */
-
- typedef struct threshold{
- float BIN_HighThresh;
- float BIN_LowThresh;
- float WARNA_HighThresh;
- float WARNA_LowThresh;
- float WARNB_HighThresh;
- float WARNB_LowThresh;
- float WARNC_HighThresh;
- float WARNC_LowThresh;
- uint8_t BIN_Mode;
- uint8_t WARNA_Mode;
- uint8_t WARNB_Mode;
- uint8_t WARNC_Mode;
- uint8_t ADCPga;
- float VGain;
+
+ /**
+ * Structure for configuring threshold levels
+*/
+typedef struct threshold{
+ float BIN_HighThresh; /** Binary channel high threshold */
+ float BIN_LowThresh; /** Binary channel low threshold */
+ float WARNA_HighThresh; /** WARNA channel high threshold */
+ float WARNA_LowThresh; /** WARNA channel Low threshold */
+ float WARNB_HighThresh; /** WARNB channel high threshold */
+ float WARNB_LowThresh; /** WARNB channel Low threshold */
+ float WARNC_HighThresh; /** WARNC channel high threshold */
+ float WARNC_LowThresh; /** WARNC channel Low threshold */
+ uint8_t BIN_Mode; /** Binary Channel comparator mode */
+ uint8_t WARNA_Mode; /** WARNA Channel comparator mode */
+ uint8_t WARNB_Mode; /** WARNB Channel comparator mode */
+ uint8_t WARNC_Mode; /** WARNC Channel comparator mode */
+ uint8_t ADCPga; /** ADC PGA setting */
+ float VGain; /** Voltage divider gain */
}THRESHCfg_Type;
-
+
+/**
+ * Structure for setting programmable load
+*/
typedef struct{
uint8_t enable; /** Enable PL */
- uint8_t mode; /** Configure mode, HIGH_IDLE, LOW_IDLE */
- float HighCurrent; /** High current in mA */
+ uint8_t mode; /** Configure mode, HIGH_IDLE, LOW_IDLE */
+ float HighCurrent; /** High current in mA */
float LowCurrent; /** Low current in mA */
float HighTime; /** Duration of current pulse in us */
float VoltThresh; /** VOltage threshold to trigger programmable load */
uint8_t ADCPga; /** ADC PGA setting */
- float VGain; /** Voltage gain set by external resister divider */
+ float VGain; /** Voltage gain set by external resister divider */
}PLOADCfg_Type;
+/**
+ * Structure for configuring energy meter
+*/
typedef struct{
- uint8_t enable; /** Enable energy meter function */
- float FET_Energy; /** SOA energy of exernal FET used */
+ uint8_t enable; /** Enable energy meter function */
+ float FET_Energy; /** SOA energy of exernal FET used */
float PulseMagnitude; /** AMplitude of current pulse in mA */
- float PulseTime; /** Length of current pulse in ms */
+ float PulseTime; /** Length of current pulse in ms */
float WorkingVoltage; /** Working voltage of system in V*/
uint32_t AvgADCCode; /** Average ADC code */
- float SampleRate; /** Sample rate, 20us for ADE1202, 10us foe ADE1201 */
- uint8_t Cooldown_TimeStep;
- uint8_t Cooldown_Decr;
- uint8_t Cooldown_Sec;
- uint8_t Ov_Scale;
- uint8_t ADCPga; /** ADC PGA setting */
- float VGain; /** Voltage gain set by external resister divider */
+ float SampleRate; /** Sample rate, 20us for ADE1202, 10us foe ADE1201 */
+ uint8_t Cooldown_TimeStep; /** Set cooldown timestep */
+ uint8_t Cooldown_Decr; /* Set cooldown decrement */
+ uint8_t Cooldown_Sec; /** Set cooldown period */
+ uint8_t Ov_Scale; /** Set over voltage scale factor */
+ uint8_t ADCPga; /** ADC PGA setting */
+ float VGain; /** Voltage gain set by external resister divider */
}EnergyMtrCfg_Type;
+/**
+ * Data sreuture for reading back register data
+*/
typedef struct{
uint16_t reg_addr;
uint32_t reg_data;
@@ -107,72 +117,34 @@
/**************************************/
/******** BIT DEFINITION **************/
-/** Config_LOCK **/
-#define Dev_Unlock 0xADE0
-#define Dev_Lock 0xADE1
-
-/** CTRL **/
-#define DEV_ADE1201 0x0
-#define DEV_ADE1202 0x1000
-#define SW_RST 0x10
-#define ADDR_RELOAD 0x8
-#define ADE1202_IRQ 0x4
-#define CRC_EN 0x1
+/** Config_LOCK **/
+#define DEV_UNLOCK 0xADE0
+#define DEV_LOCK 0xADE1
-/** ADC **/
-#define ADC_RAW 0
-#define ADC_DECIMATOR 1
-
-#define LOW_IDLE 0
-#define HIGH_IDLE 1
-
-#define OV_SCALE_1 0
-#define OV_SCALE_4 1
-#define OV_SCALE_8 2
-#define OV_SCALE_16 3
-
-/******** DEFAULT CONFIG **************/
-#define BIN_FILTER_VAL 0x8003
+/** CTRL **/
+#define DEV_ADE1201 0x0
+#define DEV_ADE1202 0x1000
+#define SW_RST 0x10
+#define ADDR_RELOAD 0x8
+#define ADE1202_IRQ 0x4
+#define CRC_EN 0x1
-typedef enum
-{
- COOLDOWN_TS_10us = 0,
- COOLDOWN_TS_20us = 1,
- COOLDOWN_TS_40us = 2,
- COOLDOWN_TS_80us = 3
-}COOLDOWN_TIMESTAMP;
-
-#define CH1_Enable 1
-#define CH2_Enable 2
-#define CH1_CH2_Enable 3
-#define CH1_Disable 0
-#define CH2_disable 0
-#define CH1_CH2_Disable 0
-
+/** BIN_CTRL **/
+#define Mode_Hysteretic 0
+#define Mode_Inbetween 1
+#define Mode_Greater 2
+#define Mode_LessEqual 3
+#define Decrate_Bypass 0
+#define Decrate_2 1
+#define Decrate_4 2
+#define Decrate_8 3
-#define PL_CH2_ENABLE 1<<15
-#define PL_CH1_ENABLE 1<<14
-#define PL_CH2_DISABLE 0<<15
-#define PL_CH1_DISABLE 0<<14
+/** xxx_FILTER **/
+#define Filter_En (1<<15)
+#define Filter_UpDown (1<<14)
-/**
- * @defgroup ADCPGA_Const
- * @brief ADC PGA Selection
- * @{
-*/
-#define ADCPGA_1 1
-#define ADCPGA_2 3
-#define ADCPGA_5 7
-#define ADCPGA_10 0xF
-
-
-#define DEV_UNLOCK 0xADE0
-#define DEV_LOCK 0xADE1
-/**
- * @defgroup AFEINTC_SRC_Const
- * @brief Interrupt source selection. These sources are defined as bit mask. They are available for register INT_STATUS and STATUS
- * @{
- * */
+/** Interrupt source selection. These sources are defined as bit mask.
+ * They are available for register INT_STATUS and STATUS **/
#define INTSRC_DOUT1 0x0001 /**< Bit0, DOUT1 */
#define INTSRC_WARNA1 0x0002 /**< Bit1, Warning A from channel 1 */
#define INTSRC_WARNB1 0x0004 /**< Bit2, Warning B from channel 1 */
@@ -188,18 +160,50 @@
#define INTSRC_COOLDOWN2 0x1000 /**< Bit13, Channel 2 is in Cooldown mode */
#define INTSRC_BUSY 0x2000 /**< Bit13, During busy assertion, internal communication is in progress. Once busy is deasserted, an irq can be triggered which indicates normal operation has resumed */
#define INTSRC_RSTDONE 0x4000 /**< Bit14, Indicates that the device has reset and is ready to be programmed or begin default normal operation */
- #define INTSRC_ALL 0x7FFF /**< All bits. Used to clear all interrupt sources */
+ #define INTSRC_ALL 0x7FFF /**< All bits. Used to clear all interrupt sources */
+
+/** ADC **/
+#define ADC_RAW 0
+#define ADC_DECIMATOR 1
+
+/** PL_CTRL **/
+#define LOW_IDLE 0
+#define HIGH_IDLE 1
+
+/** EGY_MTR_CTRL **/
+#define OV_SCALE_1 0
+#define OV_SCALE_4 1
+#define OV_SCALE_8 2
+#define OV_SCALE_16 3
+
-/**
- * @defgroup WARNx Mode Const
- * @brief Comparator modes
- * @details COnfigure mode for WARNx comparator modes
- * @{
-*/
-#define Mode_Hysteretic 0
-#define Mode_Inbetween 1
-#define Mode_Greater 2
-#define Mode_LessEqual 3
+typedef enum
+{
+ COOLDOWN_TS_10us = 0,
+ COOLDOWN_TS_20us = 1,
+ COOLDOWN_TS_40us = 2,
+ COOLDOWN_TS_80us = 3
+}COOLDOWN_TIMESTAMP;
+
+#define CH1_Enable 1
+#define CH2_Enable 2
+#define CH1_CH2_Enable 3
+#define CH1_Disable 0
+#define CH2_disable 0
+#define CH1_CH2_Disable 0
+
+/** PL_EN **/
+#define PL_CH2_ENABLE (1<<15)
+#define PL_CH1_ENABLE (1<<14)
+#define PL_CH2_DISABLE (0<<15)
+#define PL_CH1_DISABLE (0<<14)
+
+/** PGA_GAIN **/
+#define ADCPGA_1 1
+#define ADCPGA_2 3
+#define ADCPGA_5 7
+#define ADCPGA_10 0xF
+
/**
* Method to identify ADE120x
@@ -207,13 +211,11 @@
* [ RES ][MODEL][Addr][RevIf]
*
*/
-#define ADE120x_Model(data) ((((uint32_t)data)>>12)&0x3) /**< Return model. 0: ADE1201, 1:ADE1202 */
-#define ADE120x_ChipAddr(data) ((((uint32_t)data)>>9)&0x7) /**< Return ECC of this FIFO result */
-#define ADE120x_RevId(data) ((((uint32_t)data)>>5)&0xf) /**< Return Channel ID */
+#define ADE120x_Model(data) ((((uint32_t)data)>>12)&0x3) /**< Return model. 0: ADE1201, 1:ADE1202 */
+#define ADE120x_ChipAddr(data) ((((uint32_t)data)>>9)&0x7) /**< Return Chip address*/
+#define ADE120x_RevId(data) ((((uint32_t)data)>>5)&0xf) /**< Return silicon rev ID */
class ADE120x{
-
-
public:
ADE120x(PinName mosi, PinName miso, PinName sclk, PinName cs);