ad77681.h

00001 /***************************************************************************//**
00002  *   @file   ad77681.h
00003  *   @brief  Header file of the AD7768-1 Driver.
00004  *   @author SPopa (stefan.popa@analog.com)
00005 ********************************************************************************
00006  * Copyright 2017(c) Analog Devices, Inc.
00007  *
00008  * All rights reserved.
00009  *
00010  * Redistribution and use in source and binary forms, with or without
00011  * modification, are permitted provided that the following conditions are met:
00012  *  - Redistributions of source code must retain the above copyright
00013  *    notice, this list of conditions and the following disclaimer.
00014  *  - Redistributions in binary form must reproduce the above copyright
00015  *    notice, this list of conditions and the following disclaimer in
00016  *    the documentation and/or other materials provided with the
00017  *    distribution.
00018  *  - Neither the name of Analog Devices, Inc. nor the names of its
00019  *    contributors may be used to endorse or promote products derived
00020  *    from this software without specific prior written permission.
00021  *  - The use of this software may or may not infringe the patent rights
00022  *    of one or more patent holders.  This license does not release you
00023  *    from the requirement that you obtain separate licenses from these
00024  *    patent holders to use this software.
00025  *  - Use of the software either in source or binary form, must be run
00026  *    on or directly connected to an Analog Devices Inc. component.
00027  *
00028  * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
00029  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
00030  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
00031  * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
00032  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00033  * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
00034  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038 *******************************************************************************/
00039 
00040 #ifndef SRC_AD77681_H_
00041 #define SRC_AD77681_H_
00042 
00043 #include "platform_drivers.h"
00044 
00045 /******************************************************************************/
00046 /********************** Macros and Constants Definitions **********************/
00047 /******************************************************************************/
00048 #define AD77681_REG_CHIP_TYPE                   0x3
00049 #define AD77681_REG_PROD_ID_L                   0x4
00050 #define AD77681_REG_PROD_ID_H                   0x5
00051 #define AD77681_REG_CHIP_GRADE                  0x6
00052 #define AD77681_REG_SCRATCH_PAD                 0x0A
00053 #define AD77681_REG_VENDOR_L                    0x0C
00054 #define AD77681_REG_VENDOR_H                    0x0D
00055 #define AD77681_REG_INTERFACE_FORMAT            0x14
00056 #define AD77681_REG_POWER_CLOCK                 0x15
00057 #define AD77681_REG_ANALOG                      0x16
00058 #define AD77681_REG_ANALOG2                     0x17
00059 #define AD77681_REG_CONVERSION                  0x18
00060 #define AD77681_REG_DIGITAL_FILTER              0x19
00061 #define AD77681_REG_SINC3_DEC_RATE_MSB          0x1A
00062 #define AD77681_REG_SINC3_DEC_RATE_LSB          0x1B
00063 #define AD77681_REG_DUTY_CYCLE_RATIO            0x1C
00064 #define AD77681_REG_SYNC_RESET                  0x1D
00065 #define AD77681_REG_GPIO_CONTROL                0x1E
00066 #define AD77681_REG_GPIO_WRITE                  0x1F
00067 #define AD77681_REG_GPIO_READ                   0x20
00068 #define AD77681_REG_OFFSET_HI                   0x21
00069 #define AD77681_REG_OFFSET_MID                  0x22
00070 #define AD77681_REG_OFFSET_LO                   0x23
00071 #define AD77681_REG_GAIN_HI                     0x24
00072 #define AD77681_REG_GAIN_MID                    0x25
00073 #define AD77681_REG_GAIN_LO                     0x26
00074 #define AD77681_REG_SPI_DIAG_ENABLE             0x28
00075 #define AD77681_REG_ADC_DIAG_ENABLE             0x29
00076 #define AD77681_REG_DIG_DIAG_ENABLE             0x2A
00077 #define AD77681_REG_ADC_DATA                    0x2C
00078 #define AD77681_REG_MASTER_STATUS               0x2D
00079 #define AD77681_REG_SPI_DIAG_STATUS             0x2E
00080 #define AD77681_REG_ADC_DIAG_STATUS             0x2F
00081 #define AD77681_REG_DIG_DIAG_STATUS             0x30
00082 #define AD77681_REG_MCLK_COUNTER                0x31
00083 
00084 /* AD77681_REG_INTERFACE_FORMAT */
00085 #define AD77681_INTERFACE_CRC_EN_MSK            (0x1 << 6)
00086 #define AD77681_INTERFACE_CRC_EN(x)             (((x) & 0x1) << 6)
00087 #define AD77681_INTERFACE_CRC_TYPE_MSK          (0x1 << 5)
00088 #define AD77681_INTERFACE_CRC_TYPE(x)           (((x) & 0x1) << 5)
00089 #define AD77681_INTERFACE_STATUS_EN_MSK         (0x1 << 4)
00090 #define AD77681_INTERFACE_STATUS_EN(x)          (((x) & 0x1) << 4)
00091 #define AD77681_INTERFACE_CONVLEN_MSK           (0x1 << 3)
00092 #define AD77681_INTERFACE_CONVLEN(x)            (((x) & 0x1) << 3)
00093 #define AD77681_INTERFACE_RDY_EN_MSK            (0x1 << 2)
00094 #define AD77681_INTERFACE_RDY_EN(x)             (((x) & 0x1) << 3)
00095 #define AD77681_INTERFACE_CONT_READ_MSK         (0x1 << 0)
00096 #define AD77681_INTERFACE_CONT_READ_EN(x)       (((x) & 0x1) << 0)
00097 #define AD77681_REG_COEFF_CONTROL               0x32
00098 #define AD77681_REG_COEFF_DATA                  0x33
00099 #define AD77681_REG_ACCESS_KEY                  0x34
00100 
00101 /* AD77681_REG_SCRATCH_PAD*/
00102 #define AD77681_SCRATCHPAD_MSK                  (0xFF << 0)
00103 #define AD77681_SCRATCHPAD(x)                   (((x) & 0xFF) << 0)
00104 
00105 /* AD77681_REG_POWER_CLOCK */
00106 #define AD77681_POWER_CLK_PWRMODE_MSK           0x3
00107 #define AD77681_POWER_CLK_PWRMODE(x)            (((x) & 0x3) << 0)
00108 #define AD77681_POWER_CLK_MOD_OUT_MSK           (0x1 << 2)
00109 #define AD77681_POWER_CLK_MOD_OUT(x)            (((x) & 0x1) << 2)
00110 #define AD77681_POWER_CLK_POWER_DOWN            0x08
00111 #define AD77681_POWER_CLK_MCLK_DIV_MSK          (0x3 << 4)
00112 #define AD77681_POWER_CLK_MCLK_DIV(x)           (((x) & 0x3) << 4)
00113 #define AD77681_POWER_CLK_CLOCK_SEL_MSK         (0x3 << 6)
00114 #define AD77681_POWER_CLK_CLOCK_SEL(x)          (((x) & 0x3) << 6)
00115 
00116 /* AD77681_CONVERSION_REG */
00117 #define AD77681_CONVERSION_DIAG_MUX_MSK         (0xF << 4)
00118 #define AD77681_CONVERSION_DIAG_MUX_SEL(x)      (((x) & 0xF) << 4)
00119 #define AD77681_CONVERSION_DIAG_SEL_MSK         (0x1 << 3)
00120 #define AD77681_CONVERSION_DIAG_SEL(x)          (((x) & 0x1) << 3)
00121 #define AD77681_CONVERSION_MODE_MSK             (0x7 << 0)
00122 #define AD77681_CONVERSION_MODE(x)              (((x) & 0x7) << 0)
00123 
00124 /* AD77681_REG_ANALOG */
00125 #define AD77681_ANALOG_REF_BUF_POS_MSK          (0x3 << 6)
00126 #define AD77681_ANALOG_REF_BUF_POS(x)           (((x) & 0x3) << 6)
00127 #define AD77681_ANALOG_REF_BUF_NEG_MSK          (0x3 << 4)
00128 #define AD77681_ANALOG_REF_BUF_NEG(x)           (((x) & 0x3) << 4)
00129 #define AD77681_ANALOG_AIN_BUF_POS_OFF_MSK      (0x1 << 1)
00130 #define AD77681_ANALOG_AIN_BUF_POS_OFF(x)       (((x) & 0x1) << 1)
00131 #define AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK      (0x1 << 0)
00132 #define AD77681_ANALOG_AIN_BUF_NEG_OFF(x)       (((x) & 0x1) << 0)
00133 
00134 /* AD77681_REG_ANALOG2 */
00135 #define AD77681_ANALOG2_VCM_MSK                 (0x7 << 0)
00136 #define AD77681_ANALOG2_VCM(x)                  (((x) & 0x7) << 0)
00137 
00138 /* AD77681_REG_DIGITAL_FILTER */
00139 #define AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK     (0x1 << 7)
00140 #define AD77681_DIGI_FILTER_60HZ_REJ_EN(x)      (((x) & 0x1) << 7)
00141 #define AD77681_DIGI_FILTER_FILTER_MSK          (0x7 << 4)
00142 #define AD77681_DIGI_FILTER_FILTER(x)           (((x) & 0x7) << 4)
00143 #define AD77681_DIGI_FILTER_DEC_RATE_MSK        (0x7 << 0)
00144 #define AD77681_DIGI_FILTER_DEC_RATE(x)         (((x) & 0x7) << 0)
00145 
00146 /* AD77681_REG_SINC3_DEC_RATE_MSB */
00147 #define AD77681_SINC3_DEC_RATE_MSB_MSK          (0x0F << 0)
00148 #define AD77681_SINC3_DEC_RATE_MSB(x)           (((x) & 0x0F) << 0)
00149 
00150 /* AD77681_REG_SINC3_DEC_RATE_LSB */
00151 #define AD77681_SINC3_DEC_RATE_LSB_MSK          (0xFF << 0)
00152 #define AD77681_SINC3_DEC_RATE_LSB(x)           (((x) & 0xFF) << 0)
00153 
00154 /* AD77681_REG_DUTY_CYCLE_RATIO */
00155 #define AD77681_DC_RATIO_IDLE_TIME_MSK          (0xFF << 0)
00156 #define AD77681_DC_RATIO_IDLE_TIME(x)           (((x) & 0xFF) << 0)
00157 
00158 /* AD77681_REG_SYNC_RESET */
00159 #define AD77681_SYNC_RST_SPI_STARTB_MSK         (0x1 << 7)
00160 #define AD77681_SYNC_RST_SPI_STARTB(x)          (((x) & 0x1) << 7)
00161 #define AD77681_SYNC_RST_SYNCOUT_EDGE_MSK       (0x1 << 6)
00162 #define AD77681_SYNC_RST_SYNCOUT_EDGE(x)        (((x) & 0x1) << 6)
00163 #define AD77681_SYNC_RST_GPIO_START_EN_MSK      (0x1 << 3)
00164 #define AD77681_SYNC_RST_GPIO_START_EN(x)       (((x) & 0x1) << 3)
00165 #define AD77681_SYNC_RST_SPI_RESET_MSK          (0x3 << 0)
00166 #define AD77681_SYNC_RST_SPI_RESET(x)           (((x) & 0x3) << 0)
00167 
00168 /* AD77681_REG_GPIO_CONTROL */
00169 #define AD77681_GPIO_CNTRL_UGPIO_EN_MSK         (0x1 << 7)
00170 #define AD77681_GPIO_CNTRL_UGPIO_EN(x)          (((x) & 0x1) << 7)
00171 #define AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK      (0x1 << 6)
00172 #define AD77681_GPIO_CNTRL_GPIO2_OD_EN(x)       (((x) & 0x1) << 6)
00173 #define AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK      (0x1 << 5)
00174 #define AD77681_GPIO_CNTRL_GPIO1_OD_EN(x)       (((x) & 0x1) << 5)
00175 #define AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK      (0x1 << 4)
00176 #define AD77681_GPIO_CNTRL_GPIO0_OD_EN(x)       (((x) & 0x1) << 4)
00177 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK  (0x7 << 4)
00178 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN(x)   (((x) & 0x7) << 4)
00179 #define AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK      (0x1 << 3)
00180 #define AD77681_GPIO_CNTRL_GPIO3_OP_EN(x)       (((x) & 0x1) << 3)
00181 #define AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK      (0x1 << 2)
00182 #define AD77681_GPIO_CNTRL_GPIO2_OP_EN(x)       (((x) & 0x1) << 2)
00183 #define AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK      (0x1 << 1)
00184 #define AD77681_GPIO_CNTRL_GPIO1_OP_EN(x)       (((x) & 0x1) << 1)
00185 #define AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK      (0x1 << 0)
00186 #define AD77681_GPIO_CNTRL_GPIO0_OP_EN(x)       (((x) & 0x1) << 0)
00187 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK  (0xF << 0)
00188 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN(x)   (((x) & 0xF) << 0)
00189 
00190 /* AD77681_REG_GPIO_WRITE */
00191 #define AD77681_GPIO_WRITE_3_MSK                (0x1 << 3)
00192 #define AD77681_GPIO_WRITE_3(x)                 (((x) & 0x1) << 3)
00193 #define AD77681_GPIO_WRITE_2_MSK                (0x1 << 2)
00194 #define AD77681_GPIO_WRITE_2(x)                 (((x) & 0x1) << 2)
00195 #define AD77681_GPIO_WRITE_1_MSK                (0x1 << 1)
00196 #define AD77681_GPIO_WRITE_1(x)                 (((x) & 0x1) << 1)
00197 #define AD77681_GPIO_WRITE_0_MSK                (0x1 << 0)
00198 #define AD77681_GPIO_WRITE_0(x)                 (((x) & 0x1) << 0)
00199 #define AD77681_GPIO_WRITE_ALL_MSK              (0xF << 0)
00200 #define AD77681_GPIO_WRITE_ALL(x)               (((x) & 0xF))
00201 
00202 /* AD77681_REG_GPIO_READ */
00203 #define AD77681_GPIO_READ_3_MSK                 (0x1 << 3)
00204 #define AD77681_GPIO_READ_2_MSK                 (0x1 << 2)
00205 #define AD77681_GPIO_READ_1_MSK                 (0x1 << 1)
00206 #define AD77681_GPIO_READ_0_MSK                 (0x1 << 0)
00207 #define AD77681_GPIO_READ_ALL_MSK               (0xF << 0)
00208 
00209 /* AD77681_REG_OFFSET_HI */
00210 #define AD77681_OFFSET_HI_MSK                   (0xFF << 0)
00211 #define AD77681_OFFSET_HI(x)                    (((x) & 0xFF) << 0)
00212 
00213 /* AD77681_REG_OFFSET_MID */
00214 #define AD77681_OFFSET_MID_MSK                  (0xFF << 0)
00215 #define AD77681_OFFSET_MID(x)                   (((x) & 0xFF) << 0)
00216 
00217 /* AD77681_REG_OFFSET_LO */
00218 #define AD77681_OFFSET_LO_MSK                   (0xFF << 0)
00219 #define AD77681_OFFSET_LO(x)                    (((x) & 0xFF) << 0)
00220 
00221 /* AD77681_REG_GAIN_HI */
00222 #define AD77681_GAIN_HI_MSK                     (0xFF << 0)
00223 #define AD77681_GAIN_HI(x)                      (((x) & 0xFF) << 0)
00224 
00225 /* AD77681_REG_GAIN_MID */
00226 #define AD77681_GAIN_MID_MSK                    (0xFF << 0)
00227 #define AD77681_GAIN_MID(x)                     (((x) & 0xFF) << 0)
00228 
00229 /* AD77681_REG_GAIN_HI */
00230 #define AD77681_GAIN_LOW_MSK                    (0xFF << 0)
00231 #define AD77681_GAIN_LOW(x)                     (((x) & 0xFF) << 0)
00232 
00233 /* AD77681_REG_SPI_DIAG_ENABLE */
00234 #define AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK     (0x1 << 4)
00235 #define AD77681_SPI_DIAG_ERR_SPI_IGNORE(x)      (((x) & 0x1) << 4)
00236 #define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK    (0x1 << 3)
00237 #define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT(x)     (((x) & 0x1) << 3)
00238 #define AD77681_SPI_DIAG_ERR_SPI_RD_MSK         (0x1 << 2)
00239 #define AD77681_SPI_DIAG_ERR_SPI_RD(x)          (((x) & 0x1) << 2)
00240 #define AD77681_SPI_DIAG_ERR_SPI_WR_MSK         (0x1 << 1)
00241 #define AD77681_SPI_DIAG_ERR_SPI_WR(x)          (((x) & 0x1) << 1)
00242 
00243 /* AD77681_REG_ADC_DIAG_ENABLE */
00244 #define AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK       (0x1 << 5)
00245 #define AD77681_ADC_DIAG_ERR_DLDO_PSM(x)        (((x) & 0x1) << 5)
00246 #define AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK       (0x1 << 4)
00247 #define AD77681_ADC_DIAG_ERR_ALDO_PSM(x)        (((x) & 0x1) << 4)
00248 #define AD77681_ADC_DIAG_ERR_FILT_SAT_MSK       (0x1 << 2)
00249 #define AD77681_ADC_DIAG_ERR_FILT_SAT(x)            (((x) & 0x1) << 2)
00250 #define AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK   (0x1 << 1)
00251 #define AD77681_ADC_DIAG_ERR_FILT_NOT_SET(x)        (((x) & 0x1) << 1)
00252 #define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK   (0x1 << 0)
00253 #define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL(x)    (((x) & 0x1) << 0)
00254 
00255 /* AD77681_REG_DIG_DIAG_ENABLE */
00256 #define AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK     (0x1 << 4)
00257 #define AD77681_DIG_DIAG_ERR_MEMMAP_CRC(x)      (((x) & 0x1) << 4)
00258 #define AD77681_DIG_DIAG_ERR_RAM_CRC_MSK        (0x1 << 3)
00259 #define AD77681_DIG_DIAG_ERR_RAM_CRC(x)         (((x) & 0x1) << 3)
00260 #define AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK       (0x1 << 2)
00261 #define AD77681_DIG_DIAG_ERR_FUSE_CRC(x)        (((x) & 0x1) << 2)
00262 #define AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK      (0x1 << 0)
00263 #define AD77681_DIG_DIAG_FREQ_COUNT_EN(x)       (((x) & 0x1) << 0)
00264 
00265 /* AD77681_REG_MASTER_STATUS */
00266 #define AD77681_MASTER_ERROR_MSK                (0x1 << 7)
00267 #define AD77681_MASTER_ADC_ERROR_MSK            (0x1 << 6)
00268 #define AD77681_MASTER_DIG_ERROR_MSK            (0x1 << 5)
00269 #define AD77681_MASTER_DIG_ERR_EXT_CLK_MSK      (0x1 << 4)
00270 #define AD77681_MASTER_FILT_SAT_MSK             (0x1 << 3)
00271 #define AD77681_MASTER_FILT_NOT_SET_MSK         (0x1 << 2)
00272 #define AD77681_MASTER_SPI_ERROR_MSK            (0x1 << 1)
00273 #define AD77681_MASTER_POR_FLAG_MSK             (0x1 << 0)
00274 
00275 /* AD77681_REG_SPI_DIAG_STATUS */
00276 #define AD77681_SPI_IGNORE_ERROR_MSK            (0x1 << 4)
00277 #define AD77681_SPI_IGNORE_ERROR_CLR(x)         (((x) & 0x1) << 4)
00278 #define AD77681_SPI_CLK_CNT_ERROR_MSK           (0x1 << 3)
00279 #define AD77681_SPI_READ_ERROR_MSK              (0x1 << 2)
00280 #define AD77681_SPI_READ_ERROR_CLR(x)           (((x) & 0x1) << 2)
00281 #define AD77681_SPI_WRITE_ERROR_MSK             (0x1 << 1)
00282 #define AD77681_SPI_WRITE_ERROR_CLR(x)          (((x) & 0x1) << 1)
00283 #define AD77681_SPI_CRC_ERROR_MSK               (0x1 << 0)
00284 #define AD77681_SPI_CRC_ERROR_CLR(x)            (((x) & 0x1) << 0)
00285 
00286 /* AD77681_REG_ADC_DIAG_STATUS */
00287 #define AD77681_ADC_DLDO_PSM_ERROR_MSK          (0x1 << 5)
00288 #define AD77681_ADC_ALDO_PSM_ERROR_MSK          (0x1 << 4)
00289 #define AD77681_ADC_REF_DET_ERROR_MSK           (0x1 << 3)
00290 #define AD77681_ADC_FILT_SAT_MSK                (0x1 << 2)
00291 #define AD77681_ADC_FILT_NOT_SET_MSK            (0x1 << 1)
00292 #define AD77681_ADC_DIG_ERR_EXT_CLK_MSK         (0x1 << 0)
00293 
00294 /* AD77681_REG_DIG_DIAG_STATUS */
00295 #define AD77681_DIG_MEMMAP_CRC_ERROR_MSK        (0x1 << 4)
00296 #define AD77681_DIG_RAM_CRC_ERROR_MSK           (0x1 << 3)
00297 #define AD77681_DIG_FUS_CRC_ERROR_MSK           (0x1 << 2)
00298 
00299 /* AD77681_REG_MCLK_COUNTER */
00300 #define AD77681_MCLK_COUNTER_MSK                (0xFF << 0)
00301 #define AD77681_MCLK_COUNTER(x)                 (((x) & 0xFF) << 0)
00302 
00303 /* AD77681_REG_COEFF_CONTROL */
00304 #define AD77681_COEF_CONTROL_COEFFACCESSEN_MSK  (0x1 << 7)
00305 #define AD77681_COEF_CONTROL_COEFFACCESSEN(x)   (((x) & 0x1) << 7)
00306 #define AD77681_COEF_CONTROL_COEFFWRITEEN_MSK   (0x1 << 6)
00307 #define AD77681_COEF_CONTROL_COEFFWRITEEN(x)    (((x) & 0x1) << 6)
00308 #define AD77681_COEF_CONTROL_COEFFADDR_MSK      (0x3F << 5)
00309 #define AD77681_COEF_CONTROL_COEFFADDR(x)       (((x) & 0x3F) << 5)
00310 
00311 /* AD77681_REG_COEFF_DATA */
00312 #define AD77681_COEFF_DATA_USERCOEFFEN_MSK      (0x1 << 23)
00313 #define AD77681_COEFF_DATA_USERCOEFFEN(x)       (((x) & 0x1) << 23)
00314 #define AD77681_COEFF_DATA_COEFFDATA_MSK        (0x7FFFFF << 22)
00315 #define AD77681_COEFF_DATA_COEFFDATA(x)         (((x) & 0x7FFFFF) << 22)
00316 
00317 /* AD77681_REG_ACCESS_KEY */
00318 #define AD77681_ACCESS_KEY_MSK                  (0xFF << 0)
00319 #define AD77681_ACCESS_KEY(x)                   (((x) & 0xFF) << 0)
00320 #define AD77681_ACCESS_KEY_CHECK_MSK            (0x1 << 0)
00321 
00322 #define AD77681_REG_READ(x)                     ( (1 << 6) | (x & 0xFF) )       // Read from register x
00323 #define AD77681_REG_WRITE(x)                    ( (~(1 << 6)) & (x & 0xFF) )    // Write to register x
00324 
00325 /* 8-bits wide checksum generated using the polynomial */
00326 #define AD77681_CRC8_POLY   0x07 // x^8 + x^2 + x^1 + x^0
00327 
00328 /* Initial CRC for continuous read mode */
00329 #define INITIAL_CRC_CRC8                        0x03
00330 #define INITIAL_CRC_XOR                         0x6C
00331 #define INITIAL_CRC                             0x00
00332 
00333 #define CRC_DEBUG
00334 
00335 /* AD7768-1 */
00336 /* A special key for exit the contiuous read mode, taken from the AD7768-1 datasheet */
00337 #define EXIT_CONT_READ                          0x6C
00338 /* Bit resolution of the AD7768-1 */
00339 #define AD7768_N_BITS                           24
00340 /* Full scale of the AD7768-1 = 2^24 = 16777216 */
00341 #define AD7768_FULL_SCALE                       (1 << AD7768_N_BITS)
00342 /* Half scale of the AD7768-1 = 2^23 = 8388608 */
00343 #define AD7768_HALF_SCALE                       (1 << (AD7768_N_BITS - 1))
00344 
00345 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
00346 
00347 #define ENABLE      1
00348 #define DISABLE     0
00349 
00350 /*****************************************************************************/
00351 /*************************** Types Declarations *******************************/
00352 /******************************************************************************/
00353 enum ad77681_power_mode {
00354     AD77681_ECO = 0,
00355     AD77681_MEDIAN = 2,
00356     AD77681_FAST = 3,
00357 };
00358 
00359 enum ad77681_mclk_div {
00360     AD77681_MCLK_DIV_16 = 0,
00361     AD77681_MCLK_DIV_8 = 1,
00362     AD77681_MCLK_DIV_4 = 2,
00363     AD77681_MCLK_DIV_2 = 3
00364 };
00365 
00366 enum ad77681_conv_mode {
00367     AD77681_CONV_CONTINUOUS = 0,
00368     AD77681_CONV_ONE_SHOT = 1,
00369     AD77681_CONV_SINGLE = 2,
00370     AD77681_CONV_PERIODIC = 3,
00371     AD77681_CONV_STANDBY = 4
00372 };
00373 
00374 enum ad77681_conv_len {
00375     AD77681_CONV_24BIT = 0,
00376     AD77681_CONV_16BIT = 1
00377 };
00378 
00379 enum ad77681_rdy_dout {
00380     AD77681_RDY_DOUT_EN,
00381     AD77681_RDY_DOUT_DIS
00382 };
00383 
00384 enum ad77681_conv_diag_mux {
00385     AD77681_TEMP_SENSOR = 0x0,
00386     AD77681_AIN_SHORT= 0x8,
00387     AD77681_POSITIVE_FS = 0x9,
00388     AD77681_NEGATIVE_FS = 0xA
00389 };
00390 
00391 enum ad77681_crc_sel {
00392     AD77681_CRC,
00393     AD77681_XOR,
00394     AD77681_NO_CRC
00395 };
00396 
00397 /* Filter tye FIR, SINC3, SINC5 */
00398 enum ad77681_filter_type {
00399     AD77681_SINC5           = 0,
00400     AD77681_SINC5_DECx8     = 1,
00401     AD77681_SINC5_DECx16    = 2,
00402     AD77681_SINC3           = 3,
00403     AD77681_FIR             = 4
00404 };
00405 
00406 /* Dectimation ratios for SINC5 and FIR */
00407 enum ad77681_sinc5_fir_decimate {
00408     AD77681_SINC5_FIR_DECx32    = 0,
00409     AD77681_SINC5_FIR_DECx64    = 1,
00410     AD77681_SINC5_FIR_DECx128   = 2,
00411     AD77681_SINC5_FIR_DECx256   = 3,
00412     AD77681_SINC5_FIR_DECx512   = 4,
00413     AD77681_SINC5_FIR_DECx1024  = 5
00414 };
00415 
00416 /* Sleep / Power up */
00417 enum ad77681_sleep_wake {
00418     AD77681_SLEEP   = 1,
00419     AD77681_WAKE = 0
00420 };
00421 
00422 /* Reset option */
00423 enum ad7761_reset_option {
00424     AD77681_SOFT_RESET,
00425     AD77681_HARD_RESET
00426 };
00427 /* AIN- precharge */
00428 enum ad77681_AINn_precharge {
00429     AD77681_AINn_ENABLED   = 0,
00430     AD77681_AINn_DISABLED  = 1
00431 };
00432 
00433 /* AIN+ precharge */
00434 enum ad77681_AINp_precharge {
00435     AD77681_AINp_ENABLED  = 0,
00436     AD77681_AINp_DISABLED = 1
00437 };
00438 
00439 /* REF- buffer */
00440 enum ad77681_REFn_buffer {
00441     AD77681_BUFn_ENABLED        = 0,
00442     AD77681_BUFn_DISABLED       = 1,
00443     AD77681_BUFn_FULL_BUFFER_ON = 2
00444 };
00445 
00446 /* REF+ buffer */
00447 enum ad77681_REFp_buffer {
00448     AD77681_BUFp_ENABLED        = 0,
00449     AD77681_BUFp_DISABLED       = 1,
00450     AD77681_BUFp_FULL_BUFFER_ON = 2
00451 };
00452 
00453 /* VCM output voltage */
00454 enum ad77681_VCM_out {
00455     AD77681_VCM_HALF_VCC    = 0,
00456     AD77681_VCM_2_5V        = 1,
00457     AD77681_VCM_2_05V       = 2,
00458     AD77681_VCM_1_9V        = 3,
00459     AD77681_VCM_1_65V       = 4,
00460     AD77681_VCM_1_1V        = 5,
00461     AD77681_VCM_0_9V        = 6,
00462     AD77681_VCM_OFF         = 7
00463 };
00464 
00465 /* Global GPIO enable/disable */
00466 enum ad77681_gobal_gpio_enable {
00467     AD77681_GLOBAL_GPIO_ENABLE      = 1,
00468     AD77681_GLOBAL_GPIO_DISABLE     = 0
00469 };
00470 
00471 /* ADCs GPIO numbering */
00472 enum ad77681_gpios {
00473     AD77681_GPIO0                   = 0,
00474     AD77681_GPIO1                   = 1,
00475     AD77681_GPIO2                   = 2,
00476     AD77681_GPIO3                   = 3,
00477     AD77681_ALL_GPIOS               = 4
00478 };
00479 
00480 enum ad77681_gpio_output_type {
00481     AD77681_GPIO_STRONG_DRIVER      = 0,
00482     AD77681_GPIO_OPEN_DRAIN         = 1
00483 };
00484 
00485 /* Continuous ADC read */
00486 enum ad77681_continuous_read {
00487     AD77681_CONTINUOUS_READ_ENABLE = 1,
00488     AD77681_CONTINUOUS_READ_DISABLE = 0,
00489 };
00490 
00491 /* ADC data read mode */
00492 enum ad77681_data_read_mode {
00493     AD77681_REGISTER_DATA_READ = 0,
00494     AD77681_CONTINUOUS_DATA_READ = 1,
00495 };
00496 
00497 /* ADC data structure */
00498 struct adc_data {
00499     bool        finish;
00500     uint16_t    count;
00501     uint16_t    samples;
00502     uint32_t    raw_data[4096];
00503 };
00504 /* ADC status registers structure */
00505 struct ad77681_status_registers {
00506     bool                            master_error;
00507     bool                            adc_error;
00508     bool                            dig_error;
00509     bool                            adc_err_ext_clk_qual;
00510     bool                            adc_filt_saturated;
00511     bool                            adc_filt_not_settled;
00512     bool                            spi_error;
00513     bool                            por_flag;
00514     bool                            spi_ignore;
00515     bool                            spi_clock_count;
00516     bool                            spi_read_error;
00517     bool                            spi_write_error;
00518     bool                            spi_crc_error;
00519     bool                            dldo_psm_error;
00520     bool                            aldo_psm_error;
00521     bool                            ref_det_error;
00522     bool                            filt_sat_error;
00523     bool                            filt_not_set_error;
00524     bool                            ext_clk_qual_error;
00525     bool                            memoy_map_crc_error;
00526     bool                            ram_crc_error;
00527     bool                            fuse_crc_error;
00528 };
00529 
00530 struct ad77681_dev {
00531     /* SPI */
00532     spi_desc            *spi_desc;
00533     /* Configuration */
00534     enum ad77681_power_mode     power_mode;
00535     enum ad77681_mclk_div       mclk_div;
00536     enum ad77681_conv_mode      conv_mode;
00537     enum ad77681_conv_diag_mux  diag_mux_sel;
00538     bool                    conv_diag_sel;
00539     enum ad77681_conv_len       conv_len;
00540     enum ad77681_crc_sel        crc_sel;
00541     uint8_t                 status_bit;
00542     enum ad77681_VCM_out            VCM_out;
00543     enum ad77681_AINn_precharge     AINn;
00544     enum ad77681_AINp_precharge     AINp;
00545     enum ad77681_REFn_buffer        REFn;
00546     enum ad77681_REFp_buffer        REFp;
00547     enum ad77681_filter_type        filter;
00548     enum ad77681_sinc5_fir_decimate decimate;
00549     uint16_t                        sinc3_osr;
00550     uint16_t                        vref;               /* Reference voltage*/
00551     uint16_t                        mclk;               /* Mater clock*/
00552     uint32_t                        sample_rate;        /* Sample rate*/
00553     uint8_t                         data_frame_byte;    /* SPI 8bit frames*/
00554 };
00555 
00556 struct ad77681_init_param {
00557     /* SPI */
00558     spi_init_param          spi_eng_dev_init;
00559     /* Configuration */
00560     enum ad77681_power_mode     power_mode;
00561     enum ad77681_mclk_div       mclk_div;
00562     enum ad77681_conv_mode      conv_mode;
00563     enum ad77681_conv_diag_mux  diag_mux_sel;
00564     bool                    conv_diag_sel;
00565     enum ad77681_conv_len       conv_len;
00566     enum ad77681_crc_sel        crc_sel;
00567     uint8_t                 status_bit;
00568     enum ad77681_VCM_out            VCM_out;
00569     enum ad77681_AINn_precharge     AINn;
00570     enum ad77681_AINp_precharge     AINp;
00571     enum ad77681_REFn_buffer        REFn;
00572     enum ad77681_REFp_buffer        REFp;
00573     enum ad77681_filter_type        filter;
00574     enum ad77681_sinc5_fir_decimate decimate;
00575     uint16_t                        sinc3_osr;
00576     uint16_t                        vref;
00577     uint16_t                        mclk;
00578     uint32_t                        sample_rate;
00579     uint8_t                         data_frame_byte;
00580 };
00581 
00582 /******************************************************************************/
00583 /************************ Functions Declarations ******************************/
00584 /******************************************************************************/
00585 uint8_t ad77681_compute_crc8(uint8_t *data,
00586                  uint8_t data_size,
00587                  uint8_t init_val);
00588 uint8_t ad77681_compute_xor(uint8_t *data,
00589                 uint8_t data_size,
00590                 uint8_t init_val);
00591 int32_t ad77681_setup(struct ad77681_dev **device,
00592               struct ad77681_init_param init_param,
00593               struct ad77681_status_registers **status);
00594 int32_t ad77681_spi_reg_read(struct ad77681_dev *dev,
00595                  uint8_t reg_addr,
00596                  uint8_t *reg_data);
00597 int32_t ad77681_spi_read_mask(struct ad77681_dev *dev,
00598                   uint8_t reg_addr,
00599                   uint8_t mask,
00600                   uint8_t *data);
00601 int32_t ad77681_spi_reg_write(struct ad77681_dev *dev,
00602                   uint8_t reg_addr,
00603                   uint8_t reg_data);
00604 int32_t ad77681_spi_write_mask(struct ad77681_dev *dev,
00605                    uint8_t reg_addr,
00606                    uint8_t mask,
00607                    uint8_t data);
00608 int32_t ad77681_set_power_mode(struct ad77681_dev *dev,
00609                    enum ad77681_power_mode mode);
00610 int32_t ad77681_set_mclk_div(struct ad77681_dev *dev,
00611                  enum ad77681_mclk_div clk_div);
00612 int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev,
00613                   uint8_t *adc_data,
00614                   enum ad77681_data_read_mode mode);
00615 int32_t ad77681_set_conv_mode(struct ad77681_dev *dev,
00616                   enum ad77681_conv_mode conv_mode,
00617                   enum ad77681_conv_diag_mux diag_mux_sel,
00618                   bool conv_diag_sel);
00619 int32_t ad77681_set_convlen(struct ad77681_dev *dev,
00620                 enum ad77681_conv_len conv_len);
00621 int32_t ad77681_soft_reset(struct ad77681_dev *dev);
00622 int32_t ad77681_initiate_sync(struct ad77681_dev *dev);
00623 int32_t ad77681_programmable_filter(struct ad77681_dev *dev,
00624                     const float *coeffs,
00625                     uint8_t num_coeffs);
00626 int32_t ad77681_gpio_read(struct ad77681_dev *dev,
00627               uint8_t *value,
00628               enum ad77681_gpios gpio_number);
00629 int32_t ad77681_apply_offset(struct ad77681_dev *dev,
00630                  uint32_t value);
00631 int32_t ad77681_apply_gain(struct ad77681_dev *dev,
00632                uint32_t value);
00633 int32_t ad77681_set_crc_sel(struct ad77681_dev *dev,
00634                 enum ad77681_crc_sel crc_sel);
00635 int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev,
00636                 enum ad77681_gpios gpio_number,
00637                 enum ad77681_gpio_output_type output_type);
00638 int32_t ad77681_set_continuos_read(struct ad77681_dev *dev,
00639                    enum ad77681_continuous_read continuous_enable);
00640 int32_t ad77681_clear_error_flags(struct ad77681_dev *dev);
00641 int32_t ad77681_data_to_voltage(struct ad77681_dev *dev,
00642                 uint32_t *raw_code,
00643                 double *voltage);
00644 int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev,
00645                     uint16_t *data_buffer);
00646 int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev,
00647                 enum ad77681_AINn_precharge AINn);
00648 int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev,
00649                 enum ad77681_AINp_precharge AINp);
00650 int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev,
00651                 enum ad77681_REFn_buffer REFn);
00652 int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev,
00653                 enum ad77681_REFp_buffer REFp);
00654 int32_t ad77681_set_filter_type(struct ad77681_dev *dev,
00655                 enum ad77681_sinc5_fir_decimate decimate,
00656                 enum ad77681_filter_type filter,
00657                 uint16_t sinc3_osr);
00658 int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev,
00659                    uint8_t enable);
00660 int32_t ad77681_power_down(struct ad77681_dev *dev,
00661                enum ad77681_sleep_wake sleep_wake);
00662 int32_t ad77681_set_status_bit(struct ad77681_dev *dev,
00663                    bool status_bit);
00664 int32_t ad77681_set_VCM_output(struct ad77681_dev *dev,
00665                    enum ad77681_VCM_out VCM_out);
00666 int32_t ad77681_gpio_write(struct ad77681_dev *dev,
00667                uint8_t value,
00668                enum ad77681_gpios gpio_number);
00669 int32_t ad77681_gpio_inout(struct ad77681_dev *dev,
00670                uint8_t direction,
00671                enum ad77681_gpios gpio_number);
00672 int32_t ad77681_global_gpio(struct ad77681_dev *devices,
00673                 enum ad77681_gobal_gpio_enable gpio_enable);
00674 int32_t ad77681_scratchpad(struct ad77681_dev *dev,
00675                uint8_t *sequence);
00676 int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev);
00677 int32_t ad77681_update_sample_rate(struct ad77681_dev *dev);
00678 int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev,
00679               uint16_t *sinc3_dec_reg,
00680               float sinc3_odr);
00681 int32_t ad77681_status(struct ad77681_dev *dev,
00682                struct ad77681_status_registers *status);
00683 #endif /* SRC_AD77681_H_ */
00684