ADMW1001_Mbed_FW / Mbed OS EV-PRO-MW1001_Development

Mbed Development branch for MeasrueWare

inc/admw1001/ADMW1001_REGISTERS.h@79:dddd92b3a416, 2020-05-20 (annotated)

Committer:
Vkadaba
Date:
Wed May 20 06:19:06 2020 +0000
Revision:
79:dddd92b3a416
Parent:
59:3d395512b442 
Updated Mbed release notes;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Vkadaba 5:0728bde67bdb 1 /* ================================================================================
Vkadaba 32:52445bef314d 2
Vkadaba 32:52445bef314d 3 Created by :
Vkadaba 59:3d395512b442 4 Created on : 2020 Mar 12, 16:15 GMT Standard Time
Vkadaba 5:0728bde67bdb 5
Vkadaba 6:9d393a9677f4 6 Project : ADMW1001_REGISTERS
Vkadaba 6:9d393a9677f4 7 File : ADMW1001_REGISTERS.h
Vkadaba 5:0728bde67bdb 8 Description : Register Definitions
Vkadaba 5:0728bde67bdb 9
Vkadaba 32:52445bef314d 10 !! ADI Confidential !!
Vkadaba 32:52445bef314d 11 INTERNAL USE ONLY
Vkadaba 5:0728bde67bdb 12
Vkadaba 44:94bdfaefddac 13 Copyright (c) 2020 Analog Devices, Inc. All Rights Reserved.
Vkadaba 5:0728bde67bdb 14 This software is proprietary and confidential to Analog Devices, Inc. and
Vkadaba 5:0728bde67bdb 15 its licensors.
Vkadaba 5:0728bde67bdb 16
Vkadaba 5:0728bde67bdb 17 This file was auto-generated. Do not make local changes to this file.
Vkadaba 32:52445bef314d 18
Vkadaba 32:52445bef314d 19 Auto generation script information:
Vkadaba 32:52445bef314d 20 Script: C:\Program Files (x86)\Yoda-19.05.01\generators\inc\genHeaders
Vkadaba 32:52445bef314d 21 Last modified: 26-SEP-2017
Vkadaba 5:0728bde67bdb 22
Vkadaba 5:0728bde67bdb 23 ================================================================================ */
Vkadaba 5:0728bde67bdb 24
Vkadaba 5:0728bde67bdb 25 #ifndef _DEF_ADMW1001_REGISTERS_H
Vkadaba 5:0728bde67bdb 26 #define _DEF_ADMW1001_REGISTERS_H
Vkadaba 5:0728bde67bdb 27
Vkadaba 5:0728bde67bdb 28 #if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
Vkadaba 5:0728bde67bdb 29 #include <stdint.h>
Vkadaba 5:0728bde67bdb 30 #endif /* _LANGUAGE_C */
Vkadaba 5:0728bde67bdb 31
Vkadaba 59:3d395512b442 32 #ifndef __ADMW_GENERATED_DEF_HEADERS__
Vkadaba 59:3d395512b442 33 #define __ADMW_GENERATED_DEF_HEADERS__ 1
Vkadaba 5:0728bde67bdb 34 #endif
Vkadaba 5:0728bde67bdb 35
Vkadaba 59:3d395512b442 36 #define __ADMW_HAS_CORE__ 1
Vkadaba 59:3d395512b442 37 #define __ADMW_HAS_SPI__ 1
Vkadaba 5:0728bde67bdb 38
Vkadaba 5:0728bde67bdb 39 /* ============================================================================================================================
Vkadaba 5:0728bde67bdb 40
Vkadaba 5:0728bde67bdb 41 ============================================================================================================================ */
Vkadaba 5:0728bde67bdb 42
Vkadaba 5:0728bde67bdb 43 /* ============================================================================================================================
Vkadaba 6:9d393a9677f4 44 SPI
Vkadaba 5:0728bde67bdb 45 ============================================================================================================================ */
Vkadaba 32:52445bef314d 46 #define MOD_SPI_BASE 0x00000000 /* */
Vkadaba 32:52445bef314d 47 #define MOD_SPI_MASK 0x00007FFF /* */
Vkadaba 6:9d393a9677f4 48 #define REG_SPI_INTERFACE_CONFIG_A_RESET 0x00000030 /* Reset Value for Interface_Config_A */
Vkadaba 6:9d393a9677f4 49 #define REG_SPI_INTERFACE_CONFIG_A 0x00000000 /* SPI Interface Configuration A */
Vkadaba 6:9d393a9677f4 50 #define REG_SPI_CHIP_TYPE_RESET 0x00000007 /* Reset Value for Chip_Type */
Vkadaba 6:9d393a9677f4 51 #define REG_SPI_CHIP_TYPE 0x00000003 /* SPI Chip Type */
Vkadaba 6:9d393a9677f4 52 #define REG_SPI_PRODUCT_ID_L_RESET 0x00000020 /* Reset Value for Product_ID_L */
Vkadaba 6:9d393a9677f4 53 #define REG_SPI_PRODUCT_ID_L 0x00000004 /* SPI Product ID Low */
Vkadaba 6:9d393a9677f4 54 #define REG_SPI_PRODUCT_ID_H_RESET 0x00000000 /* Reset Value for Product_ID_H */
Vkadaba 6:9d393a9677f4 55 #define REG_SPI_PRODUCT_ID_H 0x00000005 /* SPI Product ID High */
Vkadaba 6:9d393a9677f4 56 #define REG_SPI_SCRATCH_PAD_RESET 0x00000000 /* Reset Value for Scratch_Pad */
Vkadaba 6:9d393a9677f4 57 #define REG_SPI_SCRATCH_PAD 0x0000000A /* SPI Scratch Pad */
Vkadaba 6:9d393a9677f4 58 #define REG_SPI_SPI_REVISION_RESET 0x00000082 /* Reset Value for SPI_Revision */
Vkadaba 6:9d393a9677f4 59 #define REG_SPI_SPI_REVISION 0x0000000B /* SPI SPI Revision */
Vkadaba 6:9d393a9677f4 60 #define REG_SPI_VENDOR_L_RESET 0x00000056 /* Reset Value for Vendor_L */
Vkadaba 6:9d393a9677f4 61 #define REG_SPI_VENDOR_L 0x0000000C /* SPI Vendor ID Low */
Vkadaba 6:9d393a9677f4 62 #define REG_SPI_VENDOR_H_RESET 0x00000004 /* Reset Value for Vendor_H */
Vkadaba 6:9d393a9677f4 63 #define REG_SPI_VENDOR_H 0x0000000D /* SPI Vendor ID High */
Vkadaba 6:9d393a9677f4 64 #define REG_SPI_STREAM_MODE_RESET 0x00000000 /* Reset Value for Stream_Mode */
Vkadaba 6:9d393a9677f4 65 #define REG_SPI_STREAM_MODE 0x0000000E /* SPI Stream Mode */
Vkadaba 6:9d393a9677f4 66 #define REG_SPI_INTERFACE_STATUS_A_RESET 0x00000000 /* Reset Value for Interface_Status_A */
Vkadaba 6:9d393a9677f4 67 #define REG_SPI_INTERFACE_STATUS_A 0x00000011 /* SPI Interface Status A */
Vkadaba 5:0728bde67bdb 68
Vkadaba 5:0728bde67bdb 69 /* ============================================================================================================================
Vkadaba 6:9d393a9677f4 70 SPI Register BitMasks, Positions & Enumerations
Vkadaba 5:0728bde67bdb 71 ============================================================================================================================ */
Vkadaba 5:0728bde67bdb 72 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 73 SPI_INTERFACE_CONFIG_A Pos/Masks Description
Vkadaba 5:0728bde67bdb 74 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 75 #define BITP_SPI_INTERFACE_CONFIG_A_SW_RESET 7 /* First of Two of the SW_RESET Bits. */
Vkadaba 5:0728bde67bdb 76 #define BITP_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 5 /* Determines Sequential Addressing Behavior */
Vkadaba 32:52445bef314d 77 #define BITP_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 4 /* Serial Data Output Pin Enable */
Vkadaba 32:52445bef314d 78 #define BITP_SPI_INTERFACE_CONFIG_A_SW_RESETX 0 /* Second of Two of the SW_RESET Bits. */
Vkadaba 32:52445bef314d 79 #define BITM_SPI_INTERFACE_CONFIG_A_SW_RESET 0x00000080 /* First of Two of the SW_RESET Bits. */
Vkadaba 5:0728bde67bdb 80 #define BITM_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 0x00000020 /* Determines Sequential Addressing Behavior */
Vkadaba 32:52445bef314d 81 #define BITM_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 0x00000010 /* Serial Data Output Pin Enable */
Vkadaba 32:52445bef314d 82 #define BITM_SPI_INTERFACE_CONFIG_A_SW_RESETX 0x00000001 /* Second of Two of the SW_RESET Bits. */
Vkadaba 6:9d393a9677f4 83 #define ENUM_SPI_INTERFACE_CONFIG_A_DESCEND 0x00000000 /* Addr_Ascension: Address accessed is decremented by one for each data byte when streaming */
Vkadaba 6:9d393a9677f4 84 #define ENUM_SPI_INTERFACE_CONFIG_A_ASCEND 0x00000020 /* Addr_Ascension: Address accessed is incremented by one for each data byte when streaming */
Vkadaba 5:0728bde67bdb 85
Vkadaba 5:0728bde67bdb 86 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 87 SPI_CHIP_TYPE Pos/Masks Description
Vkadaba 5:0728bde67bdb 88 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 89 #define BITP_SPI_CHIP_TYPE_CHIP_TYPE 0 /* Precision ADC */
Vkadaba 6:9d393a9677f4 90 #define BITM_SPI_CHIP_TYPE_CHIP_TYPE 0x0000000F /* Precision ADC */
Vkadaba 5:0728bde67bdb 91
Vkadaba 5:0728bde67bdb 92 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 93 SPI_PRODUCT_ID_L Pos/Masks Description
Vkadaba 5:0728bde67bdb 94 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 59:3d395512b442 95 #define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID 0 /* The Device Chip Type and Family */
Vkadaba 59:3d395512b442 96 #define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID 0x000000FF /* The Device Chip Type and Family */
Vkadaba 5:0728bde67bdb 97
Vkadaba 5:0728bde67bdb 98 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 99 SPI_PRODUCT_ID_H Pos/Masks Description
Vkadaba 5:0728bde67bdb 100 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 59:3d395512b442 101 #define BITP_SPI_PRODUCT_ID_H_PRODUCT_ID 0 /* The Device Chip Type and Family */
Vkadaba 59:3d395512b442 102 #define BITM_SPI_PRODUCT_ID_H_PRODUCT_ID 0x000000FF /* The Device Chip Type and Family */
Vkadaba 5:0728bde67bdb 103
Vkadaba 5:0728bde67bdb 104 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 105 SPI_SCRATCH_PAD Pos/Masks Description
Vkadaba 5:0728bde67bdb 106 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 107 #define BITP_SPI_SCRATCH_PAD_SCRATCH_VALUE 0 /* Software Scratchpad */
Vkadaba 6:9d393a9677f4 108 #define BITM_SPI_SCRATCH_PAD_SCRATCH_VALUE 0x000000FF /* Software Scratchpad */
Vkadaba 5:0728bde67bdb 109
Vkadaba 5:0728bde67bdb 110 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 111 SPI_SPI_REVISION Pos/Masks Description
Vkadaba 5:0728bde67bdb 112 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 113 #define BITP_SPI_SPI_REVISION_SPI_TYPE 6 /* Always Reads as 0x2 */
Vkadaba 6:9d393a9677f4 114 #define BITP_SPI_SPI_REVISION_VERSION 0 /* SPI Version */
Vkadaba 6:9d393a9677f4 115 #define BITM_SPI_SPI_REVISION_SPI_TYPE 0x000000C0 /* Always Reads as 0x2 */
Vkadaba 6:9d393a9677f4 116 #define BITM_SPI_SPI_REVISION_VERSION 0x0000003F /* SPI Version */
Vkadaba 32:52445bef314d 117 #define ENUM_SPI_SPI_REVISION_ADI_SPI 0x00000000 /* SPI_Type: ADI_SPI */
Vkadaba 32:52445bef314d 118 #define ENUM_SPI_SPI_REVISION_LPT_SPI 0x00000080 /* SPI_Type: LPT_SPI */
Vkadaba 6:9d393a9677f4 119 #define ENUM_SPI_SPI_REVISION_REV1_0 0x00000002 /* Version: Revision 1.0 */
Vkadaba 5:0728bde67bdb 120
Vkadaba 5:0728bde67bdb 121 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 122 SPI_VENDOR_L Pos/Masks Description
Vkadaba 5:0728bde67bdb 123 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 124 #define BITP_SPI_VENDOR_L_VID 0 /* Analog Devices Vendor ID */
Vkadaba 6:9d393a9677f4 125 #define BITM_SPI_VENDOR_L_VID 0x000000FF /* Analog Devices Vendor ID */
Vkadaba 5:0728bde67bdb 126
Vkadaba 5:0728bde67bdb 127 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 128 SPI_VENDOR_H Pos/Masks Description
Vkadaba 5:0728bde67bdb 129 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 130 #define BITP_SPI_VENDOR_H_VID 0 /* Analog Devices Vendor ID */
Vkadaba 6:9d393a9677f4 131 #define BITM_SPI_VENDOR_H_VID 0x000000FF /* Analog Devices Vendor ID */
Vkadaba 5:0728bde67bdb 132
Vkadaba 5:0728bde67bdb 133 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 134 SPI_STREAM_MODE Pos/Masks Description
Vkadaba 5:0728bde67bdb 135 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 136 #define BITP_SPI_STREAM_MODE_LOOP_COUNT 0 /* Set the Data Byte Count Before Looping to Start Address */
Vkadaba 32:52445bef314d 137 #define BITM_SPI_STREAM_MODE_LOOP_COUNT 0x000000FF /* Set the Data Byte Count Before Looping to Start Address */
Vkadaba 5:0728bde67bdb 138
Vkadaba 5:0728bde67bdb 139 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 140 SPI_INTERFACE_STATUS_A Pos/Masks Description
Vkadaba 5:0728bde67bdb 141 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 5:0728bde67bdb 142 #define BITP_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 7 /* Device Not Ready for Transaction */
Vkadaba 5:0728bde67bdb 143 #define BITP_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 4 /* Incorrect Number of Clocks Detected in a Transaction */
Vkadaba 5:0728bde67bdb 144 #define BITP_SPI_INTERFACE_STATUS_A_CRC_ERROR 3 /* Invalid/No CRC Received */
Vkadaba 32:52445bef314d 145 #define BITP_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 2 /* Write to Read Only Register Attempted */
Vkadaba 5:0728bde67bdb 146 #define BITP_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 1 /* Set When Fewer Than Expected Number of Bytes Read/Written */
Vkadaba 32:52445bef314d 147 #define BITP_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0 /* Attempt to Read/Write Nonexistent Register Address */
Vkadaba 5:0728bde67bdb 148 #define BITM_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 0x00000080 /* Device Not Ready for Transaction */
Vkadaba 5:0728bde67bdb 149 #define BITM_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 0x00000010 /* Incorrect Number of Clocks Detected in a Transaction */
Vkadaba 5:0728bde67bdb 150 #define BITM_SPI_INTERFACE_STATUS_A_CRC_ERROR 0x00000008 /* Invalid/No CRC Received */
Vkadaba 32:52445bef314d 151 #define BITM_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 0x00000004 /* Write to Read Only Register Attempted */
Vkadaba 5:0728bde67bdb 152 #define BITM_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 0x00000002 /* Set When Fewer Than Expected Number of Bytes Read/Written */
Vkadaba 32:52445bef314d 153 #define BITM_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0x00000001 /* Attempt to Read/Write Nonexistent Register Address */
Vkadaba 5:0728bde67bdb 154
Vkadaba 5:0728bde67bdb 155
Vkadaba 5:0728bde67bdb 156 /* ============================================================================================================================
Vkadaba 59:3d395512b442 157 ADMW1001 Core Registers
Vkadaba 5:0728bde67bdb 158 ============================================================================================================================ */
Vkadaba 5:0728bde67bdb 159
Vkadaba 5:0728bde67bdb 160 /* ============================================================================================================================
Vkadaba 6:9d393a9677f4 161 CORE
Vkadaba 5:0728bde67bdb 162 ============================================================================================================================ */
Vkadaba 59:3d395512b442 163 #define MOD_CORE_BASE 0x00000010 /* ADMW1001 Core Registers */
Vkadaba 59:3d395512b442 164 #define MOD_CORE_MASK 0x00007FFF /* ADMW1001 Core Registers */
Vkadaba 6:9d393a9677f4 165 #define REG_CORE_COMMAND_RESET 0x00000000 /* Reset Value for Command */
Vkadaba 32:52445bef314d 166 #define REG_CORE_COMMAND 0x00000014 /* CORE Special Command Register */
Vkadaba 6:9d393a9677f4 167 #define REG_CORE_MODE_RESET 0x00000000 /* Reset Value for Mode */
Vkadaba 6:9d393a9677f4 168 #define REG_CORE_MODE 0x00000016 /* CORE Operating Mode and DRDY Control */
Vkadaba 6:9d393a9677f4 169 #define REG_CORE_POWER_CONFIG_RESET 0x00000000 /* Reset Value for Power_Config */
Vkadaba 32:52445bef314d 170 #define REG_CORE_POWER_CONFIG 0x00000017 /* CORE Power Configuration */
Vkadaba 59:3d395512b442 171 #define REG_CORE_CYCLE_CONTROL_RESET 0x00002000 /* Reset Value for Cycle_Control */
Vkadaba 6:9d393a9677f4 172 #define REG_CORE_CYCLE_CONTROL 0x00000018 /* CORE Measurement Cycle */
Vkadaba 32:52445bef314d 173 #define REG_CORE_FIFO_NUM_CYCLES_RESET 0x00000001 /* Reset Value for Fifo_Num_Cycles */
Vkadaba 32:52445bef314d 174 #define REG_CORE_FIFO_NUM_CYCLES 0x0000001A /* CORE Number of Measurement Cycles to Store in FIFO */
Vkadaba 6:9d393a9677f4 175 #define REG_CORE_STATUS_RESET 0x00000000 /* Reset Value for Status */
Vkadaba 6:9d393a9677f4 176 #define REG_CORE_STATUS 0x00000020 /* CORE General Status */
Vkadaba 6:9d393a9677f4 177 #define REG_CORE_CHANNEL_ALERT_STATUS_RESET 0x00000000 /* Reset Value for Channel_Alert_Status */
Vkadaba 6:9d393a9677f4 178 #define REG_CORE_CHANNEL_ALERT_STATUS 0x00000026 /* CORE Alert Status Summary */
Vkadaba 6:9d393a9677f4 179 #define REG_CORE_ALERT_DETAIL_CHn_RESET 0x00000000 /* Reset Value for Alert_Detail_Ch[n] */
Vkadaba 6:9d393a9677f4 180 #define REG_CORE_ALERT_DETAIL_CH0_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH0 */
Vkadaba 6:9d393a9677f4 181 #define REG_CORE_ALERT_DETAIL_CH1_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH1 */
Vkadaba 6:9d393a9677f4 182 #define REG_CORE_ALERT_DETAIL_CH2_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH2 */
Vkadaba 6:9d393a9677f4 183 #define REG_CORE_ALERT_DETAIL_CH3_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH3 */
Vkadaba 6:9d393a9677f4 184 #define REG_CORE_ALERT_DETAIL_CH4_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH4 */
Vkadaba 6:9d393a9677f4 185 #define REG_CORE_ALERT_DETAIL_CH5_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH5 */
Vkadaba 6:9d393a9677f4 186 #define REG_CORE_ALERT_DETAIL_CH6_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH6 */
Vkadaba 6:9d393a9677f4 187 #define REG_CORE_ALERT_DETAIL_CH7_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH7 */
Vkadaba 6:9d393a9677f4 188 #define REG_CORE_ALERT_DETAIL_CH8_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH8 */
Vkadaba 6:9d393a9677f4 189 #define REG_CORE_ALERT_DETAIL_CH9_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH9 */
Vkadaba 6:9d393a9677f4 190 #define REG_CORE_ALERT_DETAIL_CH10_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH10 */
Vkadaba 6:9d393a9677f4 191 #define REG_CORE_ALERT_DETAIL_CH11_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH11 */
Vkadaba 6:9d393a9677f4 192 #define REG_CORE_ALERT_DETAIL_CH12_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH12 */
Vkadaba 32:52445bef314d 193 #define REG_CORE_ALERT_DETAIL_CH0 0x0000002A /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 194 #define REG_CORE_ALERT_DETAIL_CH1 0x0000002C /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 195 #define REG_CORE_ALERT_DETAIL_CH2 0x0000002E /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 196 #define REG_CORE_ALERT_DETAIL_CH3 0x00000030 /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 197 #define REG_CORE_ALERT_DETAIL_CH4 0x00000032 /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 198 #define REG_CORE_ALERT_DETAIL_CH5 0x00000034 /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 199 #define REG_CORE_ALERT_DETAIL_CH6 0x00000036 /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 200 #define REG_CORE_ALERT_DETAIL_CH7 0x00000038 /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 201 #define REG_CORE_ALERT_DETAIL_CH8 0x0000003A /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 202 #define REG_CORE_ALERT_DETAIL_CH9 0x0000003C /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 203 #define REG_CORE_ALERT_DETAIL_CH10 0x0000003E /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 204 #define REG_CORE_ALERT_DETAIL_CH11 0x00000040 /* CORE Detailed Channel Error Information */
Vkadaba 32:52445bef314d 205 #define REG_CORE_ALERT_DETAIL_CH12 0x00000042 /* CORE Detailed Channel Error Information */
Vkadaba 6:9d393a9677f4 206 #define REG_CORE_ALERT_DETAIL_CHn(i) (REG_CORE_ALERT_DETAIL_CH0 + ((i) * 2))
Vkadaba 8:2f2775c34640 207 #define REG_CORE_ALERT_DETAIL_CHn_COUNT 13
Vkadaba 6:9d393a9677f4 208 #define REG_CORE_ERROR_CODE_RESET 0x00000000 /* Reset Value for Error_Code */
Vkadaba 6:9d393a9677f4 209 #define REG_CORE_ERROR_CODE 0x0000004C /* CORE Code Indicating Source of Error */
Vkadaba 32:52445bef314d 210 #define REG_CORE_EXTERNAL_REFERENCE_RESISTOR_RESET 0x447A0000 /* Reset Value for External_Reference_Resistor */
Vkadaba 32:52445bef314d 211 #define REG_CORE_EXTERNAL_REFERENCE_RESISTOR 0x00000050 /* CORE External Reference Resistor Value */
Vkadaba 36:54e2418e7620 212 #define REG_CORE_EXTERNAL_VOLTAGE_REFERENCE_RESET 0x3F99999A /* Reset Value for External_Voltage_Reference */
Vkadaba 36:54e2418e7620 213 #define REG_CORE_EXTERNAL_VOLTAGE_REFERENCE 0x00000054 /* CORE External Reference Information */
Vkadaba 44:94bdfaefddac 214 #define REG_CORE_AVDD_VOLTAGE_RESET 0x40533333 /* Reset Value for AVDD_Voltage */
Vkadaba 44:94bdfaefddac 215 #define REG_CORE_AVDD_VOLTAGE 0x00000058 /* CORE AVDD Voltage */
Vkadaba 6:9d393a9677f4 216 #define REG_CORE_DIAGNOSTICS_CONTROL_RESET 0x00000000 /* Reset Value for Diagnostics_Control */
Vkadaba 6:9d393a9677f4 217 #define REG_CORE_DIAGNOSTICS_CONTROL 0x0000005C /* CORE Diagnostic Control */
Vkadaba 59:3d395512b442 218 #define REG_CORE_EXT_VBUFF_RESET 0x00000000 /* Reset Value for EXT_VBUFF */
Vkadaba 59:3d395512b442 219 #define REG_CORE_EXT_VBUFF 0x0000005D /* CORE External Reference Buffer */
Vkadaba 6:9d393a9677f4 220 #define REG_CORE_DATA_FIFO_RESET 0x00000000 /* Reset Value for Data_FIFO */
Vkadaba 6:9d393a9677f4 221 #define REG_CORE_DATA_FIFO 0x00000060 /* CORE FIFO Buffer of Sensor Results */
Vkadaba 6:9d393a9677f4 222 #define REG_CORE_DEBUG_CODE_RESET 0x00000000 /* Reset Value for Debug_Code */
Vkadaba 6:9d393a9677f4 223 #define REG_CORE_DEBUG_CODE 0x00000064 /* CORE Additional Information on Source of Alert or Errors */
Vkadaba 32:52445bef314d 224 #define REG_CORE_TEST_REG_ACCESS_RESET 0x00000000 /* Reset Value for Test_Reg_Access */
Vkadaba 32:52445bef314d 225 #define REG_CORE_TEST_REG_ACCESS 0x0000006C /* CORE Allows Access to Test (Hidden) Registers and Features */
Vkadaba 6:9d393a9677f4 226 #define REG_CORE_LUT_SELECT_RESET 0x00000000 /* Reset Value for LUT_Select */
Vkadaba 32:52445bef314d 227 #define REG_CORE_LUT_SELECT 0x00000070 /* CORE LUT Read/Write Strobe */
Vkadaba 6:9d393a9677f4 228 #define REG_CORE_LUT_OFFSET_RESET 0x00000000 /* Reset Value for LUT_Offset */
Vkadaba 6:9d393a9677f4 229 #define REG_CORE_LUT_OFFSET 0x00000072 /* CORE Offset into Selected LUT */
Vkadaba 6:9d393a9677f4 230 #define REG_CORE_LUT_DATA_RESET 0x00000000 /* Reset Value for LUT_Data */
Vkadaba 6:9d393a9677f4 231 #define REG_CORE_LUT_DATA 0x00000074 /* CORE Data to Read/Write from Addressed LUT Entry */
Vkadaba 32:52445bef314d 232 #define REG_CORE_REVISION_RESET 0x01000000 /* Reset Value for Revision */
Vkadaba 59:3d395512b442 233 #define REG_CORE_REVISION 0x0000008C /* CORE Hardware, Firmware Revision */
Vkadaba 6:9d393a9677f4 234 #define REG_CORE_CHANNEL_COUNTn_RESET 0x00000000 /* Reset Value for Channel_Count[n] */
Vkadaba 6:9d393a9677f4 235 #define REG_CORE_CHANNEL_COUNT0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT0 */
Vkadaba 6:9d393a9677f4 236 #define REG_CORE_CHANNEL_COUNT1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT1 */
Vkadaba 6:9d393a9677f4 237 #define REG_CORE_CHANNEL_COUNT2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT2 */
Vkadaba 6:9d393a9677f4 238 #define REG_CORE_CHANNEL_COUNT3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT3 */
Vkadaba 6:9d393a9677f4 239 #define REG_CORE_CHANNEL_COUNT4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT4 */
Vkadaba 6:9d393a9677f4 240 #define REG_CORE_CHANNEL_COUNT5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT5 */
Vkadaba 6:9d393a9677f4 241 #define REG_CORE_CHANNEL_COUNT6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT6 */
Vkadaba 6:9d393a9677f4 242 #define REG_CORE_CHANNEL_COUNT7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT7 */
Vkadaba 6:9d393a9677f4 243 #define REG_CORE_CHANNEL_COUNT8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT8 */
Vkadaba 6:9d393a9677f4 244 #define REG_CORE_CHANNEL_COUNT9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT9 */
Vkadaba 6:9d393a9677f4 245 #define REG_CORE_CHANNEL_COUNT10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT10 */
Vkadaba 8:2f2775c34640 246 #define REG_CORE_CHANNEL_COUNT11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT11 */
Vkadaba 8:2f2775c34640 247 #define REG_CORE_CHANNEL_COUNT12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT12 */
Vkadaba 6:9d393a9677f4 248 #define REG_CORE_CHANNEL_COUNT0 0x00000090 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 6:9d393a9677f4 249 #define REG_CORE_CHANNEL_COUNT1 0x000000D0 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 6:9d393a9677f4 250 #define REG_CORE_CHANNEL_COUNT2 0x00000110 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 6:9d393a9677f4 251 #define REG_CORE_CHANNEL_COUNT3 0x00000150 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 6:9d393a9677f4 252 #define REG_CORE_CHANNEL_COUNT4 0x00000190 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 6:9d393a9677f4 253 #define REG_CORE_CHANNEL_COUNT5 0x000001D0 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 6:9d393a9677f4 254 #define REG_CORE_CHANNEL_COUNT6 0x00000210 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 6:9d393a9677f4 255 #define REG_CORE_CHANNEL_COUNT7 0x00000250 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 6:9d393a9677f4 256 #define REG_CORE_CHANNEL_COUNT8 0x00000290 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 6:9d393a9677f4 257 #define REG_CORE_CHANNEL_COUNT9 0x000002D0 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 6:9d393a9677f4 258 #define REG_CORE_CHANNEL_COUNT10 0x00000310 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 8:2f2775c34640 259 #define REG_CORE_CHANNEL_COUNT11 0x00000350 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 8:2f2775c34640 260 #define REG_CORE_CHANNEL_COUNT12 0x00000390 /* CORE Number of Channel Occurrences per Measurement Cycle */
Vkadaba 6:9d393a9677f4 261 #define REG_CORE_CHANNEL_COUNTn(i) (REG_CORE_CHANNEL_COUNT0 + ((i) * 64))
Vkadaba 8:2f2775c34640 262 #define REG_CORE_CHANNEL_COUNTn_COUNT 13
Vkadaba 6:9d393a9677f4 263 #define REG_CORE_CHANNEL_OPTIONSn_RESET 0x00000000 /* Reset Value for Channel_Options[n] */
Vkadaba 6:9d393a9677f4 264 #define REG_CORE_CHANNEL_OPTIONS0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS0 */
Vkadaba 6:9d393a9677f4 265 #define REG_CORE_CHANNEL_OPTIONS1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS1 */
Vkadaba 6:9d393a9677f4 266 #define REG_CORE_CHANNEL_OPTIONS2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS2 */
Vkadaba 6:9d393a9677f4 267 #define REG_CORE_CHANNEL_OPTIONS3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS3 */
Vkadaba 6:9d393a9677f4 268 #define REG_CORE_CHANNEL_OPTIONS4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS4 */
Vkadaba 6:9d393a9677f4 269 #define REG_CORE_CHANNEL_OPTIONS5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS5 */
Vkadaba 6:9d393a9677f4 270 #define REG_CORE_CHANNEL_OPTIONS6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS6 */
Vkadaba 6:9d393a9677f4 271 #define REG_CORE_CHANNEL_OPTIONS7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS7 */
Vkadaba 6:9d393a9677f4 272 #define REG_CORE_CHANNEL_OPTIONS8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS8 */
Vkadaba 6:9d393a9677f4 273 #define REG_CORE_CHANNEL_OPTIONS9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS9 */
Vkadaba 6:9d393a9677f4 274 #define REG_CORE_CHANNEL_OPTIONS10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS10 */
Vkadaba 8:2f2775c34640 275 #define REG_CORE_CHANNEL_OPTIONS11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS11 */
Vkadaba 8:2f2775c34640 276 #define REG_CORE_CHANNEL_OPTIONS12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS12 */
Vkadaba 32:52445bef314d 277 #define REG_CORE_CHANNEL_OPTIONS0 0x00000091 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 278 #define REG_CORE_CHANNEL_OPTIONS1 0x000000D1 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 279 #define REG_CORE_CHANNEL_OPTIONS2 0x00000111 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 280 #define REG_CORE_CHANNEL_OPTIONS3 0x00000151 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 281 #define REG_CORE_CHANNEL_OPTIONS4 0x00000191 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 282 #define REG_CORE_CHANNEL_OPTIONS5 0x000001D1 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 283 #define REG_CORE_CHANNEL_OPTIONS6 0x00000211 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 284 #define REG_CORE_CHANNEL_OPTIONS7 0x00000251 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 285 #define REG_CORE_CHANNEL_OPTIONS8 0x00000291 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 286 #define REG_CORE_CHANNEL_OPTIONS9 0x000002D1 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 287 #define REG_CORE_CHANNEL_OPTIONS10 0x00000311 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 288 #define REG_CORE_CHANNEL_OPTIONS11 0x00000351 /* CORE Position of Channel Within Sequence */
Vkadaba 32:52445bef314d 289 #define REG_CORE_CHANNEL_OPTIONS12 0x00000391 /* CORE Position of Channel Within Sequence */
Vkadaba 6:9d393a9677f4 290 #define REG_CORE_CHANNEL_OPTIONSn(i) (REG_CORE_CHANNEL_OPTIONS0 + ((i) * 64))
Vkadaba 8:2f2775c34640 291 #define REG_CORE_CHANNEL_OPTIONSn_COUNT 13
Vkadaba 6:9d393a9677f4 292 #define REG_CORE_SENSOR_TYPEn_RESET 0x00000000 /* Reset Value for Sensor_Type[n] */
Vkadaba 6:9d393a9677f4 293 #define REG_CORE_SENSOR_TYPE0_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE0 */
Vkadaba 6:9d393a9677f4 294 #define REG_CORE_SENSOR_TYPE1_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE1 */
Vkadaba 6:9d393a9677f4 295 #define REG_CORE_SENSOR_TYPE2_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE2 */
Vkadaba 6:9d393a9677f4 296 #define REG_CORE_SENSOR_TYPE3_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE3 */
Vkadaba 6:9d393a9677f4 297 #define REG_CORE_SENSOR_TYPE4_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE4 */
Vkadaba 6:9d393a9677f4 298 #define REG_CORE_SENSOR_TYPE5_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE5 */
Vkadaba 6:9d393a9677f4 299 #define REG_CORE_SENSOR_TYPE6_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE6 */
Vkadaba 6:9d393a9677f4 300 #define REG_CORE_SENSOR_TYPE7_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE7 */
Vkadaba 6:9d393a9677f4 301 #define REG_CORE_SENSOR_TYPE8_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE8 */
Vkadaba 6:9d393a9677f4 302 #define REG_CORE_SENSOR_TYPE9_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE9 */
Vkadaba 6:9d393a9677f4 303 #define REG_CORE_SENSOR_TYPE10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE10 */
Vkadaba 8:2f2775c34640 304 #define REG_CORE_SENSOR_TYPE11_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE11 */
Vkadaba 8:2f2775c34640 305 #define REG_CORE_SENSOR_TYPE12_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE12 */
Vkadaba 6:9d393a9677f4 306 #define REG_CORE_SENSOR_TYPE0 0x00000092 /* CORE Sensor Select */
Vkadaba 6:9d393a9677f4 307 #define REG_CORE_SENSOR_TYPE1 0x000000D2 /* CORE Sensor Select */
Vkadaba 6:9d393a9677f4 308 #define REG_CORE_SENSOR_TYPE2 0x00000112 /* CORE Sensor Select */
Vkadaba 6:9d393a9677f4 309 #define REG_CORE_SENSOR_TYPE3 0x00000152 /* CORE Sensor Select */
Vkadaba 6:9d393a9677f4 310 #define REG_CORE_SENSOR_TYPE4 0x00000192 /* CORE Sensor Select */
Vkadaba 6:9d393a9677f4 311 #define REG_CORE_SENSOR_TYPE5 0x000001D2 /* CORE Sensor Select */
Vkadaba 6:9d393a9677f4 312 #define REG_CORE_SENSOR_TYPE6 0x00000212 /* CORE Sensor Select */
Vkadaba 6:9d393a9677f4 313 #define REG_CORE_SENSOR_TYPE7 0x00000252 /* CORE Sensor Select */
Vkadaba 6:9d393a9677f4 314 #define REG_CORE_SENSOR_TYPE8 0x00000292 /* CORE Sensor Select */
Vkadaba 6:9d393a9677f4 315 #define REG_CORE_SENSOR_TYPE9 0x000002D2 /* CORE Sensor Select */
Vkadaba 6:9d393a9677f4 316 #define REG_CORE_SENSOR_TYPE10 0x00000312 /* CORE Sensor Select */
Vkadaba 8:2f2775c34640 317 #define REG_CORE_SENSOR_TYPE11 0x00000352 /* CORE Sensor Select */
Vkadaba 8:2f2775c34640 318 #define REG_CORE_SENSOR_TYPE12 0x00000392 /* CORE Sensor Select */
Vkadaba 6:9d393a9677f4 319 #define REG_CORE_SENSOR_TYPEn(i) (REG_CORE_SENSOR_TYPE0 + ((i) * 64))
Vkadaba 8:2f2775c34640 320 #define REG_CORE_SENSOR_TYPEn_COUNT 13
Vkadaba 6:9d393a9677f4 321 #define REG_CORE_SENSOR_DETAILSn_RESET 0x000000F0 /* Reset Value for Sensor_Details[n] */
Vkadaba 6:9d393a9677f4 322 #define REG_CORE_SENSOR_DETAILS0_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS0 */
Vkadaba 6:9d393a9677f4 323 #define REG_CORE_SENSOR_DETAILS1_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS1 */
Vkadaba 6:9d393a9677f4 324 #define REG_CORE_SENSOR_DETAILS2_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS2 */
Vkadaba 6:9d393a9677f4 325 #define REG_CORE_SENSOR_DETAILS3_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS3 */
Vkadaba 6:9d393a9677f4 326 #define REG_CORE_SENSOR_DETAILS4_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS4 */
Vkadaba 6:9d393a9677f4 327 #define REG_CORE_SENSOR_DETAILS5_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS5 */
Vkadaba 6:9d393a9677f4 328 #define REG_CORE_SENSOR_DETAILS6_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS6 */
Vkadaba 6:9d393a9677f4 329 #define REG_CORE_SENSOR_DETAILS7_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS7 */
Vkadaba 6:9d393a9677f4 330 #define REG_CORE_SENSOR_DETAILS8_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS8 */
Vkadaba 6:9d393a9677f4 331 #define REG_CORE_SENSOR_DETAILS9_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS9 */
Vkadaba 6:9d393a9677f4 332 #define REG_CORE_SENSOR_DETAILS10_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS10 */
Vkadaba 8:2f2775c34640 333 #define REG_CORE_SENSOR_DETAILS11_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS11 */
Vkadaba 8:2f2775c34640 334 #define REG_CORE_SENSOR_DETAILS12_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS12 */
Vkadaba 6:9d393a9677f4 335 #define REG_CORE_SENSOR_DETAILS0 0x00000094 /* CORE Sensor Details */
Vkadaba 6:9d393a9677f4 336 #define REG_CORE_SENSOR_DETAILS1 0x000000D4 /* CORE Sensor Details */
Vkadaba 6:9d393a9677f4 337 #define REG_CORE_SENSOR_DETAILS2 0x00000114 /* CORE Sensor Details */
Vkadaba 6:9d393a9677f4 338 #define REG_CORE_SENSOR_DETAILS3 0x00000154 /* CORE Sensor Details */
Vkadaba 6:9d393a9677f4 339 #define REG_CORE_SENSOR_DETAILS4 0x00000194 /* CORE Sensor Details */
Vkadaba 6:9d393a9677f4 340 #define REG_CORE_SENSOR_DETAILS5 0x000001D4 /* CORE Sensor Details */
Vkadaba 6:9d393a9677f4 341 #define REG_CORE_SENSOR_DETAILS6 0x00000214 /* CORE Sensor Details */
Vkadaba 6:9d393a9677f4 342 #define REG_CORE_SENSOR_DETAILS7 0x00000254 /* CORE Sensor Details */
Vkadaba 6:9d393a9677f4 343 #define REG_CORE_SENSOR_DETAILS8 0x00000294 /* CORE Sensor Details */
Vkadaba 6:9d393a9677f4 344 #define REG_CORE_SENSOR_DETAILS9 0x000002D4 /* CORE Sensor Details */
Vkadaba 6:9d393a9677f4 345 #define REG_CORE_SENSOR_DETAILS10 0x00000314 /* CORE Sensor Details */
Vkadaba 8:2f2775c34640 346 #define REG_CORE_SENSOR_DETAILS11 0x00000354 /* CORE Sensor Details */
Vkadaba 8:2f2775c34640 347 #define REG_CORE_SENSOR_DETAILS12 0x00000394 /* CORE Sensor Details */
Vkadaba 6:9d393a9677f4 348 #define REG_CORE_SENSOR_DETAILSn(i) (REG_CORE_SENSOR_DETAILS0 + ((i) * 64))
Vkadaba 8:2f2775c34640 349 #define REG_CORE_SENSOR_DETAILSn_COUNT 13
Vkadaba 6:9d393a9677f4 350 #define REG_CORE_CHANNEL_EXCITATIONn_RESET 0x00000000 /* Reset Value for Channel_Excitation[n] */
Vkadaba 6:9d393a9677f4 351 #define REG_CORE_CHANNEL_EXCITATION0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION0 */
Vkadaba 6:9d393a9677f4 352 #define REG_CORE_CHANNEL_EXCITATION1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION1 */
Vkadaba 6:9d393a9677f4 353 #define REG_CORE_CHANNEL_EXCITATION2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION2 */
Vkadaba 6:9d393a9677f4 354 #define REG_CORE_CHANNEL_EXCITATION3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION3 */
Vkadaba 6:9d393a9677f4 355 #define REG_CORE_CHANNEL_EXCITATION4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION4 */
Vkadaba 6:9d393a9677f4 356 #define REG_CORE_CHANNEL_EXCITATION5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION5 */
Vkadaba 6:9d393a9677f4 357 #define REG_CORE_CHANNEL_EXCITATION6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION6 */
Vkadaba 6:9d393a9677f4 358 #define REG_CORE_CHANNEL_EXCITATION7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION7 */
Vkadaba 6:9d393a9677f4 359 #define REG_CORE_CHANNEL_EXCITATION8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION8 */
Vkadaba 6:9d393a9677f4 360 #define REG_CORE_CHANNEL_EXCITATION9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION9 */
Vkadaba 6:9d393a9677f4 361 #define REG_CORE_CHANNEL_EXCITATION10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION10 */
Vkadaba 8:2f2775c34640 362 #define REG_CORE_CHANNEL_EXCITATION11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION11 */
Vkadaba 8:2f2775c34640 363 #define REG_CORE_CHANNEL_EXCITATION12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION12 */
Vkadaba 6:9d393a9677f4 364 #define REG_CORE_CHANNEL_EXCITATION0 0x00000098 /* CORE Excitation Current */
Vkadaba 6:9d393a9677f4 365 #define REG_CORE_CHANNEL_EXCITATION1 0x000000D8 /* CORE Excitation Current */
Vkadaba 6:9d393a9677f4 366 #define REG_CORE_CHANNEL_EXCITATION2 0x00000118 /* CORE Excitation Current */
Vkadaba 6:9d393a9677f4 367 #define REG_CORE_CHANNEL_EXCITATION3 0x00000158 /* CORE Excitation Current */
Vkadaba 6:9d393a9677f4 368 #define REG_CORE_CHANNEL_EXCITATION4 0x00000198 /* CORE Excitation Current */
Vkadaba 6:9d393a9677f4 369 #define REG_CORE_CHANNEL_EXCITATION5 0x000001D8 /* CORE Excitation Current */
Vkadaba 6:9d393a9677f4 370 #define REG_CORE_CHANNEL_EXCITATION6 0x00000218 /* CORE Excitation Current */
Vkadaba 6:9d393a9677f4 371 #define REG_CORE_CHANNEL_EXCITATION7 0x00000258 /* CORE Excitation Current */
Vkadaba 6:9d393a9677f4 372 #define REG_CORE_CHANNEL_EXCITATION8 0x00000298 /* CORE Excitation Current */
Vkadaba 6:9d393a9677f4 373 #define REG_CORE_CHANNEL_EXCITATION9 0x000002D8 /* CORE Excitation Current */
Vkadaba 6:9d393a9677f4 374 #define REG_CORE_CHANNEL_EXCITATION10 0x00000318 /* CORE Excitation Current */
Vkadaba 8:2f2775c34640 375 #define REG_CORE_CHANNEL_EXCITATION11 0x00000358 /* CORE Excitation Current */
Vkadaba 8:2f2775c34640 376 #define REG_CORE_CHANNEL_EXCITATION12 0x00000398 /* CORE Excitation Current */
Vkadaba 6:9d393a9677f4 377 #define REG_CORE_CHANNEL_EXCITATIONn(i) (REG_CORE_CHANNEL_EXCITATION0 + ((i) * 64))
Vkadaba 8:2f2775c34640 378 #define REG_CORE_CHANNEL_EXCITATIONn_COUNT 13
Vkadaba 6:9d393a9677f4 379 #define REG_CORE_SETTLING_TIMEn_RESET 0x00000000 /* Reset Value for Settling_Time[n] */
Vkadaba 6:9d393a9677f4 380 #define REG_CORE_SETTLING_TIME0_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME0 */
Vkadaba 6:9d393a9677f4 381 #define REG_CORE_SETTLING_TIME1_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME1 */
Vkadaba 6:9d393a9677f4 382 #define REG_CORE_SETTLING_TIME2_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME2 */
Vkadaba 6:9d393a9677f4 383 #define REG_CORE_SETTLING_TIME3_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME3 */
Vkadaba 6:9d393a9677f4 384 #define REG_CORE_SETTLING_TIME4_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME4 */
Vkadaba 6:9d393a9677f4 385 #define REG_CORE_SETTLING_TIME5_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME5 */
Vkadaba 6:9d393a9677f4 386 #define REG_CORE_SETTLING_TIME6_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME6 */
Vkadaba 6:9d393a9677f4 387 #define REG_CORE_SETTLING_TIME7_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME7 */
Vkadaba 6:9d393a9677f4 388 #define REG_CORE_SETTLING_TIME8_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME8 */
Vkadaba 6:9d393a9677f4 389 #define REG_CORE_SETTLING_TIME9_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME9 */
Vkadaba 6:9d393a9677f4 390 #define REG_CORE_SETTLING_TIME10_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME10 */
Vkadaba 8:2f2775c34640 391 #define REG_CORE_SETTLING_TIME11_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME11 */
Vkadaba 8:2f2775c34640 392 #define REG_CORE_SETTLING_TIME12_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME12 */
Vkadaba 6:9d393a9677f4 393 #define REG_CORE_SETTLING_TIME0 0x0000009A /* CORE Settling Time */
Vkadaba 6:9d393a9677f4 394 #define REG_CORE_SETTLING_TIME1 0x000000DA /* CORE Settling Time */
Vkadaba 6:9d393a9677f4 395 #define REG_CORE_SETTLING_TIME2 0x0000011A /* CORE Settling Time */
Vkadaba 6:9d393a9677f4 396 #define REG_CORE_SETTLING_TIME3 0x0000015A /* CORE Settling Time */
Vkadaba 6:9d393a9677f4 397 #define REG_CORE_SETTLING_TIME4 0x0000019A /* CORE Settling Time */
Vkadaba 6:9d393a9677f4 398 #define REG_CORE_SETTLING_TIME5 0x000001DA /* CORE Settling Time */
Vkadaba 6:9d393a9677f4 399 #define REG_CORE_SETTLING_TIME6 0x0000021A /* CORE Settling Time */
Vkadaba 6:9d393a9677f4 400 #define REG_CORE_SETTLING_TIME7 0x0000025A /* CORE Settling Time */
Vkadaba 6:9d393a9677f4 401 #define REG_CORE_SETTLING_TIME8 0x0000029A /* CORE Settling Time */
Vkadaba 6:9d393a9677f4 402 #define REG_CORE_SETTLING_TIME9 0x000002DA /* CORE Settling Time */
Vkadaba 6:9d393a9677f4 403 #define REG_CORE_SETTLING_TIME10 0x0000031A /* CORE Settling Time */
Vkadaba 8:2f2775c34640 404 #define REG_CORE_SETTLING_TIME11 0x0000035A /* CORE Settling Time */
Vkadaba 8:2f2775c34640 405 #define REG_CORE_SETTLING_TIME12 0x0000039A /* CORE Settling Time */
Vkadaba 6:9d393a9677f4 406 #define REG_CORE_SETTLING_TIMEn(i) (REG_CORE_SETTLING_TIME0 + ((i) * 64))
Vkadaba 8:2f2775c34640 407 #define REG_CORE_SETTLING_TIMEn_COUNT 13
Vkadaba 6:9d393a9677f4 408 #define REG_CORE_MEASUREMENT_SETUPn_RESET 0x00000000 /* Reset Value for Measurement_Setup[n] */
Vkadaba 6:9d393a9677f4 409 #define REG_CORE_MEASUREMENT_SETUP0_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP0 */
Vkadaba 6:9d393a9677f4 410 #define REG_CORE_MEASUREMENT_SETUP1_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP1 */
Vkadaba 6:9d393a9677f4 411 #define REG_CORE_MEASUREMENT_SETUP2_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP2 */
Vkadaba 6:9d393a9677f4 412 #define REG_CORE_MEASUREMENT_SETUP3_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP3 */
Vkadaba 6:9d393a9677f4 413 #define REG_CORE_MEASUREMENT_SETUP4_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP4 */
Vkadaba 6:9d393a9677f4 414 #define REG_CORE_MEASUREMENT_SETUP5_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP5 */
Vkadaba 6:9d393a9677f4 415 #define REG_CORE_MEASUREMENT_SETUP6_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP6 */
Vkadaba 6:9d393a9677f4 416 #define REG_CORE_MEASUREMENT_SETUP7_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP7 */
Vkadaba 6:9d393a9677f4 417 #define REG_CORE_MEASUREMENT_SETUP8_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP8 */
Vkadaba 6:9d393a9677f4 418 #define REG_CORE_MEASUREMENT_SETUP9_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP9 */
Vkadaba 6:9d393a9677f4 419 #define REG_CORE_MEASUREMENT_SETUP10_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP10 */
Vkadaba 8:2f2775c34640 420 #define REG_CORE_MEASUREMENT_SETUP11_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP11 */
Vkadaba 8:2f2775c34640 421 #define REG_CORE_MEASUREMENT_SETUP12_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP12 */
Vkadaba 32:52445bef314d 422 #define REG_CORE_MEASUREMENT_SETUP0 0x0000009C /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 423 #define REG_CORE_MEASUREMENT_SETUP1 0x000000DC /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 424 #define REG_CORE_MEASUREMENT_SETUP2 0x0000011C /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 425 #define REG_CORE_MEASUREMENT_SETUP3 0x0000015C /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 426 #define REG_CORE_MEASUREMENT_SETUP4 0x0000019C /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 427 #define REG_CORE_MEASUREMENT_SETUP5 0x000001DC /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 428 #define REG_CORE_MEASUREMENT_SETUP6 0x0000021C /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 429 #define REG_CORE_MEASUREMENT_SETUP7 0x0000025C /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 430 #define REG_CORE_MEASUREMENT_SETUP8 0x0000029C /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 431 #define REG_CORE_MEASUREMENT_SETUP9 0x000002DC /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 432 #define REG_CORE_MEASUREMENT_SETUP10 0x0000031C /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 433 #define REG_CORE_MEASUREMENT_SETUP11 0x0000035C /* CORE ADC Measurement Setup */
Vkadaba 32:52445bef314d 434 #define REG_CORE_MEASUREMENT_SETUP12 0x0000039C /* CORE ADC Measurement Setup */
Vkadaba 6:9d393a9677f4 435 #define REG_CORE_MEASUREMENT_SETUPn(i) (REG_CORE_MEASUREMENT_SETUP0 + ((i) * 64))
Vkadaba 8:2f2775c34640 436 #define REG_CORE_MEASUREMENT_SETUPn_COUNT 13
Vkadaba 32:52445bef314d 437 #define REG_CORE_HIGH_THRESHOLD_LIMITn_RESET 0x7F800000 /* Reset Value for High_Threshold_Limit[n] */
Vkadaba 32:52445bef314d 438 #define REG_CORE_HIGH_THRESHOLD_LIMIT0_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT0 */
Vkadaba 32:52445bef314d 439 #define REG_CORE_HIGH_THRESHOLD_LIMIT1_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT1 */
Vkadaba 32:52445bef314d 440 #define REG_CORE_HIGH_THRESHOLD_LIMIT2_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT2 */
Vkadaba 32:52445bef314d 441 #define REG_CORE_HIGH_THRESHOLD_LIMIT3_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT3 */
Vkadaba 32:52445bef314d 442 #define REG_CORE_HIGH_THRESHOLD_LIMIT4_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT4 */
Vkadaba 32:52445bef314d 443 #define REG_CORE_HIGH_THRESHOLD_LIMIT5_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT5 */
Vkadaba 32:52445bef314d 444 #define REG_CORE_HIGH_THRESHOLD_LIMIT6_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT6 */
Vkadaba 32:52445bef314d 445 #define REG_CORE_HIGH_THRESHOLD_LIMIT7_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT7 */
Vkadaba 32:52445bef314d 446 #define REG_CORE_HIGH_THRESHOLD_LIMIT8_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT8 */
Vkadaba 32:52445bef314d 447 #define REG_CORE_HIGH_THRESHOLD_LIMIT9_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT9 */
Vkadaba 32:52445bef314d 448 #define REG_CORE_HIGH_THRESHOLD_LIMIT10_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT10 */
Vkadaba 32:52445bef314d 449 #define REG_CORE_HIGH_THRESHOLD_LIMIT11_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT11 */
Vkadaba 32:52445bef314d 450 #define REG_CORE_HIGH_THRESHOLD_LIMIT12_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT12 */
Vkadaba 6:9d393a9677f4 451 #define REG_CORE_HIGH_THRESHOLD_LIMIT0 0x000000A0 /* CORE High Threshold */
Vkadaba 6:9d393a9677f4 452 #define REG_CORE_HIGH_THRESHOLD_LIMIT1 0x000000E0 /* CORE High Threshold */
Vkadaba 6:9d393a9677f4 453 #define REG_CORE_HIGH_THRESHOLD_LIMIT2 0x00000120 /* CORE High Threshold */
Vkadaba 6:9d393a9677f4 454 #define REG_CORE_HIGH_THRESHOLD_LIMIT3 0x00000160 /* CORE High Threshold */
Vkadaba 6:9d393a9677f4 455 #define REG_CORE_HIGH_THRESHOLD_LIMIT4 0x000001A0 /* CORE High Threshold */
Vkadaba 6:9d393a9677f4 456 #define REG_CORE_HIGH_THRESHOLD_LIMIT5 0x000001E0 /* CORE High Threshold */
Vkadaba 6:9d393a9677f4 457 #define REG_CORE_HIGH_THRESHOLD_LIMIT6 0x00000220 /* CORE High Threshold */
Vkadaba 6:9d393a9677f4 458 #define REG_CORE_HIGH_THRESHOLD_LIMIT7 0x00000260 /* CORE High Threshold */
Vkadaba 6:9d393a9677f4 459 #define REG_CORE_HIGH_THRESHOLD_LIMIT8 0x000002A0 /* CORE High Threshold */
Vkadaba 6:9d393a9677f4 460 #define REG_CORE_HIGH_THRESHOLD_LIMIT9 0x000002E0 /* CORE High Threshold */
Vkadaba 6:9d393a9677f4 461 #define REG_CORE_HIGH_THRESHOLD_LIMIT10 0x00000320 /* CORE High Threshold */
Vkadaba 8:2f2775c34640 462 #define REG_CORE_HIGH_THRESHOLD_LIMIT11 0x00000360 /* CORE High Threshold */
Vkadaba 8:2f2775c34640 463 #define REG_CORE_HIGH_THRESHOLD_LIMIT12 0x000003A0 /* CORE High Threshold */
Vkadaba 6:9d393a9677f4 464 #define REG_CORE_HIGH_THRESHOLD_LIMITn(i) (REG_CORE_HIGH_THRESHOLD_LIMIT0 + ((i) * 64))
Vkadaba 8:2f2775c34640 465 #define REG_CORE_HIGH_THRESHOLD_LIMITn_COUNT 13
Vkadaba 32:52445bef314d 466 #define REG_CORE_LOW_THRESHOLD_LIMITn_RESET 0xFF800000 /* Reset Value for Low_Threshold_Limit[n] */
Vkadaba 32:52445bef314d 467 #define REG_CORE_LOW_THRESHOLD_LIMIT0_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT0 */
Vkadaba 32:52445bef314d 468 #define REG_CORE_LOW_THRESHOLD_LIMIT1_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT1 */
Vkadaba 32:52445bef314d 469 #define REG_CORE_LOW_THRESHOLD_LIMIT2_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT2 */
Vkadaba 32:52445bef314d 470 #define REG_CORE_LOW_THRESHOLD_LIMIT3_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT3 */
Vkadaba 32:52445bef314d 471 #define REG_CORE_LOW_THRESHOLD_LIMIT4_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT4 */
Vkadaba 32:52445bef314d 472 #define REG_CORE_LOW_THRESHOLD_LIMIT5_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT5 */
Vkadaba 32:52445bef314d 473 #define REG_CORE_LOW_THRESHOLD_LIMIT6_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT6 */
Vkadaba 32:52445bef314d 474 #define REG_CORE_LOW_THRESHOLD_LIMIT7_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT7 */
Vkadaba 32:52445bef314d 475 #define REG_CORE_LOW_THRESHOLD_LIMIT8_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT8 */
Vkadaba 32:52445bef314d 476 #define REG_CORE_LOW_THRESHOLD_LIMIT9_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT9 */
Vkadaba 32:52445bef314d 477 #define REG_CORE_LOW_THRESHOLD_LIMIT10_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT10 */
Vkadaba 32:52445bef314d 478 #define REG_CORE_LOW_THRESHOLD_LIMIT11_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT11 */
Vkadaba 32:52445bef314d 479 #define REG_CORE_LOW_THRESHOLD_LIMIT12_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT12 */
Vkadaba 6:9d393a9677f4 480 #define REG_CORE_LOW_THRESHOLD_LIMIT0 0x000000A4 /* CORE Low Threshold */
Vkadaba 6:9d393a9677f4 481 #define REG_CORE_LOW_THRESHOLD_LIMIT1 0x000000E4 /* CORE Low Threshold */
Vkadaba 6:9d393a9677f4 482 #define REG_CORE_LOW_THRESHOLD_LIMIT2 0x00000124 /* CORE Low Threshold */
Vkadaba 6:9d393a9677f4 483 #define REG_CORE_LOW_THRESHOLD_LIMIT3 0x00000164 /* CORE Low Threshold */
Vkadaba 6:9d393a9677f4 484 #define REG_CORE_LOW_THRESHOLD_LIMIT4 0x000001A4 /* CORE Low Threshold */
Vkadaba 6:9d393a9677f4 485 #define REG_CORE_LOW_THRESHOLD_LIMIT5 0x000001E4 /* CORE Low Threshold */
Vkadaba 6:9d393a9677f4 486 #define REG_CORE_LOW_THRESHOLD_LIMIT6 0x00000224 /* CORE Low Threshold */
Vkadaba 6:9d393a9677f4 487 #define REG_CORE_LOW_THRESHOLD_LIMIT7 0x00000264 /* CORE Low Threshold */
Vkadaba 6:9d393a9677f4 488 #define REG_CORE_LOW_THRESHOLD_LIMIT8 0x000002A4 /* CORE Low Threshold */
Vkadaba 6:9d393a9677f4 489 #define REG_CORE_LOW_THRESHOLD_LIMIT9 0x000002E4 /* CORE Low Threshold */
Vkadaba 6:9d393a9677f4 490 #define REG_CORE_LOW_THRESHOLD_LIMIT10 0x00000324 /* CORE Low Threshold */
Vkadaba 8:2f2775c34640 491 #define REG_CORE_LOW_THRESHOLD_LIMIT11 0x00000364 /* CORE Low Threshold */
Vkadaba 8:2f2775c34640 492 #define REG_CORE_LOW_THRESHOLD_LIMIT12 0x000003A4 /* CORE Low Threshold */
Vkadaba 6:9d393a9677f4 493 #define REG_CORE_LOW_THRESHOLD_LIMITn(i) (REG_CORE_LOW_THRESHOLD_LIMIT0 + ((i) * 64))
Vkadaba 8:2f2775c34640 494 #define REG_CORE_LOW_THRESHOLD_LIMITn_COUNT 13
Vkadaba 6:9d393a9677f4 495 #define REG_CORE_SENSOR_OFFSETn_RESET 0x00000000 /* Reset Value for Sensor_Offset[n] */
Vkadaba 6:9d393a9677f4 496 #define REG_CORE_SENSOR_OFFSET0_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET0 */
Vkadaba 6:9d393a9677f4 497 #define REG_CORE_SENSOR_OFFSET1_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET1 */
Vkadaba 6:9d393a9677f4 498 #define REG_CORE_SENSOR_OFFSET2_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET2 */
Vkadaba 6:9d393a9677f4 499 #define REG_CORE_SENSOR_OFFSET3_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET3 */
Vkadaba 6:9d393a9677f4 500 #define REG_CORE_SENSOR_OFFSET4_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET4 */
Vkadaba 6:9d393a9677f4 501 #define REG_CORE_SENSOR_OFFSET5_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET5 */
Vkadaba 6:9d393a9677f4 502 #define REG_CORE_SENSOR_OFFSET6_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET6 */
Vkadaba 6:9d393a9677f4 503 #define REG_CORE_SENSOR_OFFSET7_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET7 */
Vkadaba 6:9d393a9677f4 504 #define REG_CORE_SENSOR_OFFSET8_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET8 */
Vkadaba 6:9d393a9677f4 505 #define REG_CORE_SENSOR_OFFSET9_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET9 */
Vkadaba 6:9d393a9677f4 506 #define REG_CORE_SENSOR_OFFSET10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET10 */
Vkadaba 8:2f2775c34640 507 #define REG_CORE_SENSOR_OFFSET11_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET11 */
Vkadaba 8:2f2775c34640 508 #define REG_CORE_SENSOR_OFFSET12_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET12 */
Vkadaba 6:9d393a9677f4 509 #define REG_CORE_SENSOR_OFFSET0 0x000000A8 /* CORE Sensor Offset Adjustment */
Vkadaba 6:9d393a9677f4 510 #define REG_CORE_SENSOR_OFFSET1 0x000000E8 /* CORE Sensor Offset Adjustment */
Vkadaba 6:9d393a9677f4 511 #define REG_CORE_SENSOR_OFFSET2 0x00000128 /* CORE Sensor Offset Adjustment */
Vkadaba 6:9d393a9677f4 512 #define REG_CORE_SENSOR_OFFSET3 0x00000168 /* CORE Sensor Offset Adjustment */
Vkadaba 6:9d393a9677f4 513 #define REG_CORE_SENSOR_OFFSET4 0x000001A8 /* CORE Sensor Offset Adjustment */
Vkadaba 6:9d393a9677f4 514 #define REG_CORE_SENSOR_OFFSET5 0x000001E8 /* CORE Sensor Offset Adjustment */
Vkadaba 6:9d393a9677f4 515 #define REG_CORE_SENSOR_OFFSET6 0x00000228 /* CORE Sensor Offset Adjustment */
Vkadaba 6:9d393a9677f4 516 #define REG_CORE_SENSOR_OFFSET7 0x00000268 /* CORE Sensor Offset Adjustment */
Vkadaba 6:9d393a9677f4 517 #define REG_CORE_SENSOR_OFFSET8 0x000002A8 /* CORE Sensor Offset Adjustment */
Vkadaba 6:9d393a9677f4 518 #define REG_CORE_SENSOR_OFFSET9 0x000002E8 /* CORE Sensor Offset Adjustment */
Vkadaba 6:9d393a9677f4 519 #define REG_CORE_SENSOR_OFFSET10 0x00000328 /* CORE Sensor Offset Adjustment */
Vkadaba 8:2f2775c34640 520 #define REG_CORE_SENSOR_OFFSET11 0x00000368 /* CORE Sensor Offset Adjustment */
Vkadaba 8:2f2775c34640 521 #define REG_CORE_SENSOR_OFFSET12 0x000003A8 /* CORE Sensor Offset Adjustment */
Vkadaba 6:9d393a9677f4 522 #define REG_CORE_SENSOR_OFFSETn(i) (REG_CORE_SENSOR_OFFSET0 + ((i) * 64))
Vkadaba 8:2f2775c34640 523 #define REG_CORE_SENSOR_OFFSETn_COUNT 13
Vkadaba 32:52445bef314d 524 #define REG_CORE_SENSOR_GAINn_RESET 0x3F800000 /* Reset Value for Sensor_Gain[n] */
Vkadaba 32:52445bef314d 525 #define REG_CORE_SENSOR_GAIN0_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN0 */
Vkadaba 32:52445bef314d 526 #define REG_CORE_SENSOR_GAIN1_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN1 */
Vkadaba 32:52445bef314d 527 #define REG_CORE_SENSOR_GAIN2_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN2 */
Vkadaba 32:52445bef314d 528 #define REG_CORE_SENSOR_GAIN3_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN3 */
Vkadaba 32:52445bef314d 529 #define REG_CORE_SENSOR_GAIN4_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN4 */
Vkadaba 32:52445bef314d 530 #define REG_CORE_SENSOR_GAIN5_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN5 */
Vkadaba 32:52445bef314d 531 #define REG_CORE_SENSOR_GAIN6_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN6 */
Vkadaba 32:52445bef314d 532 #define REG_CORE_SENSOR_GAIN7_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN7 */
Vkadaba 32:52445bef314d 533 #define REG_CORE_SENSOR_GAIN8_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN8 */
Vkadaba 32:52445bef314d 534 #define REG_CORE_SENSOR_GAIN9_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN9 */
Vkadaba 32:52445bef314d 535 #define REG_CORE_SENSOR_GAIN10_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN10 */
Vkadaba 6:9d393a9677f4 536 #define REG_CORE_SENSOR_GAIN0 0x000000AC /* CORE Sensor Gain Adjustment */
Vkadaba 6:9d393a9677f4 537 #define REG_CORE_SENSOR_GAIN1 0x000000EC /* CORE Sensor Gain Adjustment */
Vkadaba 6:9d393a9677f4 538 #define REG_CORE_SENSOR_GAIN2 0x0000012C /* CORE Sensor Gain Adjustment */
Vkadaba 6:9d393a9677f4 539 #define REG_CORE_SENSOR_GAIN3 0x0000016C /* CORE Sensor Gain Adjustment */
Vkadaba 6:9d393a9677f4 540 #define REG_CORE_SENSOR_GAIN4 0x000001AC /* CORE Sensor Gain Adjustment */
Vkadaba 6:9d393a9677f4 541 #define REG_CORE_SENSOR_GAIN5 0x000001EC /* CORE Sensor Gain Adjustment */
Vkadaba 6:9d393a9677f4 542 #define REG_CORE_SENSOR_GAIN6 0x0000022C /* CORE Sensor Gain Adjustment */
Vkadaba 6:9d393a9677f4 543 #define REG_CORE_SENSOR_GAIN7 0x0000026C /* CORE Sensor Gain Adjustment */
Vkadaba 6:9d393a9677f4 544 #define REG_CORE_SENSOR_GAIN8 0x000002AC /* CORE Sensor Gain Adjustment */
Vkadaba 6:9d393a9677f4 545 #define REG_CORE_SENSOR_GAIN9 0x000002EC /* CORE Sensor Gain Adjustment */
Vkadaba 6:9d393a9677f4 546 #define REG_CORE_SENSOR_GAIN10 0x0000032C /* CORE Sensor Gain Adjustment */
Vkadaba 6:9d393a9677f4 547 #define REG_CORE_SENSOR_GAINn(i) (REG_CORE_SENSOR_GAIN0 + ((i) * 64))
Vkadaba 44:94bdfaefddac 548 #define REG_CORE_SENSOR_GAINn_COUNT 11
Vkadaba 6:9d393a9677f4 549 #define REG_CORE_CHANNEL_SKIPn_RESET 0x00000000 /* Reset Value for Channel_Skip[n] */
Vkadaba 6:9d393a9677f4 550 #define REG_CORE_CHANNEL_SKIP0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP0 */
Vkadaba 6:9d393a9677f4 551 #define REG_CORE_CHANNEL_SKIP1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP1 */
Vkadaba 6:9d393a9677f4 552 #define REG_CORE_CHANNEL_SKIP2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP2 */
Vkadaba 6:9d393a9677f4 553 #define REG_CORE_CHANNEL_SKIP3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP3 */
Vkadaba 6:9d393a9677f4 554 #define REG_CORE_CHANNEL_SKIP4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP4 */
Vkadaba 6:9d393a9677f4 555 #define REG_CORE_CHANNEL_SKIP5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP5 */
Vkadaba 6:9d393a9677f4 556 #define REG_CORE_CHANNEL_SKIP6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP6 */
Vkadaba 6:9d393a9677f4 557 #define REG_CORE_CHANNEL_SKIP7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP7 */
Vkadaba 6:9d393a9677f4 558 #define REG_CORE_CHANNEL_SKIP8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP8 */
Vkadaba 6:9d393a9677f4 559 #define REG_CORE_CHANNEL_SKIP9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP9 */
Vkadaba 6:9d393a9677f4 560 #define REG_CORE_CHANNEL_SKIP10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP10 */
Vkadaba 8:2f2775c34640 561 #define REG_CORE_CHANNEL_SKIP11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP11 */
Vkadaba 8:2f2775c34640 562 #define REG_CORE_CHANNEL_SKIP12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP12 */
Vkadaba 6:9d393a9677f4 563 #define REG_CORE_CHANNEL_SKIP0 0x000000B2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 564 #define REG_CORE_CHANNEL_SKIP1 0x000000F2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 565 #define REG_CORE_CHANNEL_SKIP2 0x00000132 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 566 #define REG_CORE_CHANNEL_SKIP3 0x00000172 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 567 #define REG_CORE_CHANNEL_SKIP4 0x000001B2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 568 #define REG_CORE_CHANNEL_SKIP5 0x000001F2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 569 #define REG_CORE_CHANNEL_SKIP6 0x00000232 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 570 #define REG_CORE_CHANNEL_SKIP7 0x00000272 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 571 #define REG_CORE_CHANNEL_SKIP8 0x000002B2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 572 #define REG_CORE_CHANNEL_SKIP9 0x000002F2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 573 #define REG_CORE_CHANNEL_SKIP10 0x00000332 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 8:2f2775c34640 574 #define REG_CORE_CHANNEL_SKIP11 0x00000372 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 8:2f2775c34640 575 #define REG_CORE_CHANNEL_SKIP12 0x000003B2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 576 #define REG_CORE_CHANNEL_SKIPn(i) (REG_CORE_CHANNEL_SKIP0 + ((i) * 64))
Vkadaba 8:2f2775c34640 577 #define REG_CORE_CHANNEL_SKIPn_COUNT 13
Vkadaba 59:3d395512b442 578 #define REG_CORE_SENSOR_PARAMETERn_RESET 0x3F80624E /* Reset Value for Sensor_Parameter[n] */
Vkadaba 59:3d395512b442 579 #define REG_CORE_SENSOR_PARAMETER0_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER0 */
Vkadaba 59:3d395512b442 580 #define REG_CORE_SENSOR_PARAMETER1_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER1 */
Vkadaba 59:3d395512b442 581 #define REG_CORE_SENSOR_PARAMETER2_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER2 */
Vkadaba 59:3d395512b442 582 #define REG_CORE_SENSOR_PARAMETER3_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER3 */
Vkadaba 59:3d395512b442 583 #define REG_CORE_SENSOR_PARAMETER4_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER4 */
Vkadaba 59:3d395512b442 584 #define REG_CORE_SENSOR_PARAMETER5_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER5 */
Vkadaba 59:3d395512b442 585 #define REG_CORE_SENSOR_PARAMETER6_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER6 */
Vkadaba 59:3d395512b442 586 #define REG_CORE_SENSOR_PARAMETER7_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER7 */
Vkadaba 59:3d395512b442 587 #define REG_CORE_SENSOR_PARAMETER8_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER8 */
Vkadaba 59:3d395512b442 588 #define REG_CORE_SENSOR_PARAMETER9_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER9 */
Vkadaba 59:3d395512b442 589 #define REG_CORE_SENSOR_PARAMETER10_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER10 */
Vkadaba 59:3d395512b442 590 #define REG_CORE_SENSOR_PARAMETER11_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER11 */
Vkadaba 59:3d395512b442 591 #define REG_CORE_SENSOR_PARAMETER12_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER12 */
Vkadaba 44:94bdfaefddac 592 #define REG_CORE_SENSOR_PARAMETER0 0x000000B4 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 593 #define REG_CORE_SENSOR_PARAMETER1 0x000000F4 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 594 #define REG_CORE_SENSOR_PARAMETER2 0x00000134 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 595 #define REG_CORE_SENSOR_PARAMETER3 0x00000174 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 596 #define REG_CORE_SENSOR_PARAMETER4 0x000001B4 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 597 #define REG_CORE_SENSOR_PARAMETER5 0x000001F4 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 598 #define REG_CORE_SENSOR_PARAMETER6 0x00000234 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 599 #define REG_CORE_SENSOR_PARAMETER7 0x00000274 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 600 #define REG_CORE_SENSOR_PARAMETER8 0x000002B4 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 601 #define REG_CORE_SENSOR_PARAMETER9 0x000002F4 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 602 #define REG_CORE_SENSOR_PARAMETER10 0x00000334 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 603 #define REG_CORE_SENSOR_PARAMETER11 0x00000374 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 604 #define REG_CORE_SENSOR_PARAMETER12 0x000003B4 /* CORE Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 605 #define REG_CORE_SENSOR_PARAMETERn(i) (REG_CORE_SENSOR_PARAMETER0 + ((i) * 64))
Vkadaba 44:94bdfaefddac 606 #define REG_CORE_SENSOR_PARAMETERn_COUNT 13
Vkadaba 5:0728bde67bdb 607 #define REG_CORE_DIGITAL_SENSOR_CONFIGn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Config[n] */
Vkadaba 5:0728bde67bdb 608 #define REG_CORE_DIGITAL_SENSOR_CONFIG0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG0 */
Vkadaba 5:0728bde67bdb 609 #define REG_CORE_DIGITAL_SENSOR_CONFIG1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG1 */
Vkadaba 5:0728bde67bdb 610 #define REG_CORE_DIGITAL_SENSOR_CONFIG2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG2 */
Vkadaba 5:0728bde67bdb 611 #define REG_CORE_DIGITAL_SENSOR_CONFIG3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG3 */
Vkadaba 5:0728bde67bdb 612 #define REG_CORE_DIGITAL_SENSOR_CONFIG4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG4 */
Vkadaba 5:0728bde67bdb 613 #define REG_CORE_DIGITAL_SENSOR_CONFIG5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG5 */
Vkadaba 5:0728bde67bdb 614 #define REG_CORE_DIGITAL_SENSOR_CONFIG6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG6 */
Vkadaba 5:0728bde67bdb 615 #define REG_CORE_DIGITAL_SENSOR_CONFIG7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG7 */
Vkadaba 5:0728bde67bdb 616 #define REG_CORE_DIGITAL_SENSOR_CONFIG8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG8 */
Vkadaba 5:0728bde67bdb 617 #define REG_CORE_DIGITAL_SENSOR_CONFIG9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG9 */
Vkadaba 5:0728bde67bdb 618 #define REG_CORE_DIGITAL_SENSOR_CONFIG10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG10 */
Vkadaba 8:2f2775c34640 619 #define REG_CORE_DIGITAL_SENSOR_CONFIG11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG11 */
Vkadaba 8:2f2775c34640 620 #define REG_CORE_DIGITAL_SENSOR_CONFIG12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG12 */
Vkadaba 6:9d393a9677f4 621 #define REG_CORE_DIGITAL_SENSOR_CONFIG0 0x000000BC /* CORE Digital Sensor Data Coding */
Vkadaba 6:9d393a9677f4 622 #define REG_CORE_DIGITAL_SENSOR_CONFIG1 0x000000FC /* CORE Digital Sensor Data Coding */
Vkadaba 6:9d393a9677f4 623 #define REG_CORE_DIGITAL_SENSOR_CONFIG2 0x0000013C /* CORE Digital Sensor Data Coding */
Vkadaba 6:9d393a9677f4 624 #define REG_CORE_DIGITAL_SENSOR_CONFIG3 0x0000017C /* CORE Digital Sensor Data Coding */
Vkadaba 6:9d393a9677f4 625 #define REG_CORE_DIGITAL_SENSOR_CONFIG4 0x000001BC /* CORE Digital Sensor Data Coding */
Vkadaba 6:9d393a9677f4 626 #define REG_CORE_DIGITAL_SENSOR_CONFIG5 0x000001FC /* CORE Digital Sensor Data Coding */
Vkadaba 6:9d393a9677f4 627 #define REG_CORE_DIGITAL_SENSOR_CONFIG6 0x0000023C /* CORE Digital Sensor Data Coding */
Vkadaba 6:9d393a9677f4 628 #define REG_CORE_DIGITAL_SENSOR_CONFIG7 0x0000027C /* CORE Digital Sensor Data Coding */
Vkadaba 6:9d393a9677f4 629 #define REG_CORE_DIGITAL_SENSOR_CONFIG8 0x000002BC /* CORE Digital Sensor Data Coding */
Vkadaba 6:9d393a9677f4 630 #define REG_CORE_DIGITAL_SENSOR_CONFIG9 0x000002FC /* CORE Digital Sensor Data Coding */
Vkadaba 6:9d393a9677f4 631 #define REG_CORE_DIGITAL_SENSOR_CONFIG10 0x0000033C /* CORE Digital Sensor Data Coding */
Vkadaba 8:2f2775c34640 632 #define REG_CORE_DIGITAL_SENSOR_CONFIG11 0x0000037C /* CORE Digital Sensor Data Coding */
Vkadaba 8:2f2775c34640 633 #define REG_CORE_DIGITAL_SENSOR_CONFIG12 0x000003BC /* CORE Digital Sensor Data Coding */
Vkadaba 6:9d393a9677f4 634 #define REG_CORE_DIGITAL_SENSOR_CONFIGn(i) (REG_CORE_DIGITAL_SENSOR_CONFIG0 + ((i) * 64))
Vkadaba 8:2f2775c34640 635 #define REG_CORE_DIGITAL_SENSOR_CONFIGn_COUNT 13
Vkadaba 5:0728bde67bdb 636 #define REG_CORE_DIGITAL_SENSOR_ADDRESSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Address[n] */
Vkadaba 5:0728bde67bdb 637 #define REG_CORE_DIGITAL_SENSOR_ADDRESS0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS0 */
Vkadaba 5:0728bde67bdb 638 #define REG_CORE_DIGITAL_SENSOR_ADDRESS1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS1 */
Vkadaba 5:0728bde67bdb 639 #define REG_CORE_DIGITAL_SENSOR_ADDRESS2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS2 */
Vkadaba 5:0728bde67bdb 640 #define REG_CORE_DIGITAL_SENSOR_ADDRESS3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS3 */
Vkadaba 5:0728bde67bdb 641 #define REG_CORE_DIGITAL_SENSOR_ADDRESS4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS4 */
Vkadaba 5:0728bde67bdb 642 #define REG_CORE_DIGITAL_SENSOR_ADDRESS5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS5 */
Vkadaba 5:0728bde67bdb 643 #define REG_CORE_DIGITAL_SENSOR_ADDRESS6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS6 */
Vkadaba 5:0728bde67bdb 644 #define REG_CORE_DIGITAL_SENSOR_ADDRESS7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS7 */
Vkadaba 5:0728bde67bdb 645 #define REG_CORE_DIGITAL_SENSOR_ADDRESS8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS8 */
Vkadaba 5:0728bde67bdb 646 #define REG_CORE_DIGITAL_SENSOR_ADDRESS9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS9 */
Vkadaba 5:0728bde67bdb 647 #define REG_CORE_DIGITAL_SENSOR_ADDRESS10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS10 */
Vkadaba 8:2f2775c34640 648 #define REG_CORE_DIGITAL_SENSOR_ADDRESS11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS11 */
Vkadaba 8:2f2775c34640 649 #define REG_CORE_DIGITAL_SENSOR_ADDRESS12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS12 */
Vkadaba 6:9d393a9677f4 650 #define REG_CORE_DIGITAL_SENSOR_ADDRESS0 0x000000BE /* CORE Sensor Address */
Vkadaba 6:9d393a9677f4 651 #define REG_CORE_DIGITAL_SENSOR_ADDRESS1 0x000000FE /* CORE Sensor Address */
Vkadaba 6:9d393a9677f4 652 #define REG_CORE_DIGITAL_SENSOR_ADDRESS2 0x0000013E /* CORE Sensor Address */
Vkadaba 6:9d393a9677f4 653 #define REG_CORE_DIGITAL_SENSOR_ADDRESS3 0x0000017E /* CORE Sensor Address */
Vkadaba 6:9d393a9677f4 654 #define REG_CORE_DIGITAL_SENSOR_ADDRESS4 0x000001BE /* CORE Sensor Address */
Vkadaba 6:9d393a9677f4 655 #define REG_CORE_DIGITAL_SENSOR_ADDRESS5 0x000001FE /* CORE Sensor Address */
Vkadaba 6:9d393a9677f4 656 #define REG_CORE_DIGITAL_SENSOR_ADDRESS6 0x0000023E /* CORE Sensor Address */
Vkadaba 6:9d393a9677f4 657 #define REG_CORE_DIGITAL_SENSOR_ADDRESS7 0x0000027E /* CORE Sensor Address */
Vkadaba 6:9d393a9677f4 658 #define REG_CORE_DIGITAL_SENSOR_ADDRESS8 0x000002BE /* CORE Sensor Address */
Vkadaba 6:9d393a9677f4 659 #define REG_CORE_DIGITAL_SENSOR_ADDRESS9 0x000002FE /* CORE Sensor Address */
Vkadaba 6:9d393a9677f4 660 #define REG_CORE_DIGITAL_SENSOR_ADDRESS10 0x0000033E /* CORE Sensor Address */
Vkadaba 8:2f2775c34640 661 #define REG_CORE_DIGITAL_SENSOR_ADDRESS11 0x0000037E /* CORE Sensor Address */
Vkadaba 8:2f2775c34640 662 #define REG_CORE_DIGITAL_SENSOR_ADDRESS12 0x000003BE /* CORE Sensor Address */
Vkadaba 6:9d393a9677f4 663 #define REG_CORE_DIGITAL_SENSOR_ADDRESSn(i) (REG_CORE_DIGITAL_SENSOR_ADDRESS0 + ((i) * 64))
Vkadaba 8:2f2775c34640 664 #define REG_CORE_DIGITAL_SENSOR_ADDRESSn_COUNT 13
Vkadaba 5:0728bde67bdb 665 #define REG_CORE_DIGITAL_SENSOR_COMMSn_RESET 0x00000006 /* Reset Value for Digital_Sensor_Comms[n] */
Vkadaba 5:0728bde67bdb 666 #define REG_CORE_DIGITAL_SENSOR_COMMS0_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS0 */
Vkadaba 5:0728bde67bdb 667 #define REG_CORE_DIGITAL_SENSOR_COMMS1_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS1 */
Vkadaba 5:0728bde67bdb 668 #define REG_CORE_DIGITAL_SENSOR_COMMS2_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS2 */
Vkadaba 5:0728bde67bdb 669 #define REG_CORE_DIGITAL_SENSOR_COMMS3_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS3 */
Vkadaba 5:0728bde67bdb 670 #define REG_CORE_DIGITAL_SENSOR_COMMS4_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS4 */
Vkadaba 5:0728bde67bdb 671 #define REG_CORE_DIGITAL_SENSOR_COMMS5_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS5 */
Vkadaba 5:0728bde67bdb 672 #define REG_CORE_DIGITAL_SENSOR_COMMS6_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS6 */
Vkadaba 5:0728bde67bdb 673 #define REG_CORE_DIGITAL_SENSOR_COMMS7_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS7 */
Vkadaba 5:0728bde67bdb 674 #define REG_CORE_DIGITAL_SENSOR_COMMS8_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS8 */
Vkadaba 5:0728bde67bdb 675 #define REG_CORE_DIGITAL_SENSOR_COMMS9_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS9 */
Vkadaba 5:0728bde67bdb 676 #define REG_CORE_DIGITAL_SENSOR_COMMS10_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS10 */
Vkadaba 8:2f2775c34640 677 #define REG_CORE_DIGITAL_SENSOR_COMMS11_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS11 */
Vkadaba 8:2f2775c34640 678 #define REG_CORE_DIGITAL_SENSOR_COMMS12_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS12 */
Vkadaba 6:9d393a9677f4 679 #define REG_CORE_DIGITAL_SENSOR_COMMS0 0x000000C0 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 6:9d393a9677f4 680 #define REG_CORE_DIGITAL_SENSOR_COMMS1 0x00000100 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 6:9d393a9677f4 681 #define REG_CORE_DIGITAL_SENSOR_COMMS2 0x00000140 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 6:9d393a9677f4 682 #define REG_CORE_DIGITAL_SENSOR_COMMS3 0x00000180 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 6:9d393a9677f4 683 #define REG_CORE_DIGITAL_SENSOR_COMMS4 0x000001C0 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 6:9d393a9677f4 684 #define REG_CORE_DIGITAL_SENSOR_COMMS5 0x00000200 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 6:9d393a9677f4 685 #define REG_CORE_DIGITAL_SENSOR_COMMS6 0x00000240 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 6:9d393a9677f4 686 #define REG_CORE_DIGITAL_SENSOR_COMMS7 0x00000280 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 6:9d393a9677f4 687 #define REG_CORE_DIGITAL_SENSOR_COMMS8 0x000002C0 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 6:9d393a9677f4 688 #define REG_CORE_DIGITAL_SENSOR_COMMS9 0x00000300 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 6:9d393a9677f4 689 #define REG_CORE_DIGITAL_SENSOR_COMMS10 0x00000340 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 8:2f2775c34640 690 #define REG_CORE_DIGITAL_SENSOR_COMMS11 0x00000380 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 8:2f2775c34640 691 #define REG_CORE_DIGITAL_SENSOR_COMMS12 0x000003C0 /* CORE Digital Sensor Communication Clock Configuration */
Vkadaba 6:9d393a9677f4 692 #define REG_CORE_DIGITAL_SENSOR_COMMSn(i) (REG_CORE_DIGITAL_SENSOR_COMMS0 + ((i) * 64))
Vkadaba 8:2f2775c34640 693 #define REG_CORE_DIGITAL_SENSOR_COMMSn_COUNT 13
Vkadaba 5:0728bde67bdb 694
Vkadaba 5:0728bde67bdb 695 /* ============================================================================================================================
Vkadaba 6:9d393a9677f4 696 CORE Register BitMasks, Positions & Enumerations
Vkadaba 5:0728bde67bdb 697 ============================================================================================================================ */
Vkadaba 5:0728bde67bdb 698 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 699 CORE_COMMAND Pos/Masks Description
Vkadaba 5:0728bde67bdb 700 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 701 #define BITP_CORE_COMMAND_SPECIAL_COMMAND 0 /* Special Command */
Vkadaba 6:9d393a9677f4 702 #define BITM_CORE_COMMAND_SPECIAL_COMMAND 0x000000FF /* Special Command */
Vkadaba 32:52445bef314d 703 #define ENUM_CORE_COMMAND_NOP 0x00000000 /* Special_Command: No command */
Vkadaba 32:52445bef314d 704 #define ENUM_CORE_COMMAND_CONVERT 0x00000001 /* Special_Command: Start ADC conversions */
Vkadaba 32:52445bef314d 705 #define ENUM_CORE_COMMAND_CONVERT_WITH_RAW 0x00000002 /* Special_Command: Start conversions with added raw ADC data */
Vkadaba 32:52445bef314d 706 #define ENUM_CORE_COMMAND_LATCH_CONFIG 0x00000007 /* Special_Command: Latch configuration. */
Vkadaba 32:52445bef314d 707 #define ENUM_CORE_COMMAND_LOAD_LUT 0x00000008 /* Special_Command: Load LUT from flash */
Vkadaba 32:52445bef314d 708 #define ENUM_CORE_COMMAND_SAVE_LUT 0x00000009 /* Special_Command: Save LUT to flash */
Vkadaba 32:52445bef314d 709 #define ENUM_CORE_COMMAND_LOAD_CONFIG_1 0x00000018 /* Special_Command: Load registers with configuration from flash */
Vkadaba 32:52445bef314d 710 #define ENUM_CORE_COMMAND_SAVE_CONFIG_1 0x00000019 /* Special_Command: Store current registers to flash configuration */
Vkadaba 5:0728bde67bdb 711
Vkadaba 5:0728bde67bdb 712 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 713 CORE_MODE Pos/Masks Description
Vkadaba 5:0728bde67bdb 714 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 715 #define BITP_CORE_MODE_DRDY_MODE 2 /* Indicates Behavior of DRDY Pin */
Vkadaba 6:9d393a9677f4 716 #define BITP_CORE_MODE_CONVERSION_MODE 0 /* Conversion Mode */
Vkadaba 32:52445bef314d 717 #define BITM_CORE_MODE_DRDY_MODE 0x0000000C /* Indicates Behavior of DRDY Pin */
Vkadaba 6:9d393a9677f4 718 #define BITM_CORE_MODE_CONVERSION_MODE 0x00000003 /* Conversion Mode */
Vkadaba 32:52445bef314d 719 #define ENUM_CORE_MODE_DRDY_PER_CONVERSION 0x00000000 /* Drdy_Mode: Data ready per conversion */
Vkadaba 32:52445bef314d 720 #define ENUM_CORE_MODE_DRDY_PER_CYCLE 0x00000004 /* Drdy_Mode: Data ready per cycle */
Vkadaba 59:3d395512b442 721 #define ENUM_CORE_MODE_DRDY_PER_FIFO_FILL 0x00000008 /* Drdy_Mode: Data ready per FIFO fill */
Vkadaba 32:52445bef314d 722 #define ENUM_CORE_MODE_SINGLECYCLE 0x00000000 /* Conversion_Mode: Single cycle conversion mode. A cycle is completed every time a convert command is issued */
Vkadaba 32:52445bef314d 723 #define ENUM_CORE_MODE_RESERVED 0x00000001 /* Conversion_Mode: Reserved for future use */
Vkadaba 32:52445bef314d 724 #define ENUM_CORE_MODE_CONTINUOUS 0x00000002 /* Conversion_Mode: Continuous conversion mode. A cycle is started repeatedly at time specified in cycle time */
Vkadaba 5:0728bde67bdb 725
Vkadaba 5:0728bde67bdb 726 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 727 CORE_POWER_CONFIG Pos/Masks Description
Vkadaba 5:0728bde67bdb 728 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 729 #define BITP_CORE_POWER_CONFIG_POWER_MODE_MCU 0 /* MCU Power Mode */
Vkadaba 6:9d393a9677f4 730 #define BITM_CORE_POWER_CONFIG_POWER_MODE_MCU 0x00000001 /* MCU Power Mode */
Vkadaba 32:52445bef314d 731 #define ENUM_CORE_POWER_CONFIG_ACTIVE_MODE 0x00000000 /* Power_Mode_MCU: ADMW1001 is fully power up and ready to convert */
Vkadaba 32:52445bef314d 732 #define ENUM_CORE_POWER_CONFIG_HIBERNATION 0x00000001 /* Power_Mode_MCU: Lowest power mode. wakeup pin required to enter active mode. SPI powered down */
Vkadaba 5:0728bde67bdb 733
Vkadaba 5:0728bde67bdb 734 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 735 CORE_CYCLE_CONTROL Pos/Masks Description
Vkadaba 5:0728bde67bdb 736 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 43:e1789b7214cf 737 #define BITP_CORE_CYCLE_CONTROL_PST_MEAS_EXC_CTRL 15 /* Disable Current Sources After Measurement Completes */
Vkadaba 5:0728bde67bdb 738 #define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 14 /* Units for Cycle Time */
Vkadaba 8:2f2775c34640 739 #define BITP_CORE_CYCLE_CONTROL_VBIAS 13 /* Voltage Bias Global Enable */
Vkadaba 43:e1789b7214cf 740 #define BITP_CORE_CYCLE_CONTROL_GND_SW_CTRL 12 /* Ground Switch Cycle Control */
Vkadaba 32:52445bef314d 741 #define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME 0 /* Time Between Measurement Cycles */
Vkadaba 43:e1789b7214cf 742 #define BITM_CORE_CYCLE_CONTROL_PST_MEAS_EXC_CTRL 0x00008000 /* Disable Current Sources After Measurement Completes */
Vkadaba 32:52445bef314d 743 #define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 0x00004000 /* Units for Cycle Time */
Vkadaba 8:2f2775c34640 744 #define BITM_CORE_CYCLE_CONTROL_VBIAS 0x00002000 /* Voltage Bias Global Enable */
Vkadaba 43:e1789b7214cf 745 #define BITM_CORE_CYCLE_CONTROL_GND_SW_CTRL 0x00001000 /* Ground Switch Cycle Control */
Vkadaba 32:52445bef314d 746 #define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME 0x00000FFF /* Time Between Measurement Cycles */
Vkadaba 43:e1789b7214cf 747 #define ENUM_CORE_CYCLE_CONTROL_POWERCYCLE 0x00000000
Vkadaba 43:e1789b7214cf 748 #define ENUM_CORE_CYCLE_CONTROL_ALWAYSON 0x00008000
Vkadaba 32:52445bef314d 749 #define ENUM_CORE_CYCLE_CONTROL_MILLISECONDS 0x00000000 /* Cycle_Time_Units: Milli-seconds */
Vkadaba 8:2f2775c34640 750 #define ENUM_CORE_CYCLE_CONTROL_SECONDS 0x00004000 /* Cycle_Time_Units: Seconds */
Vkadaba 32:52445bef314d 751 #define ENUM_CORE_CYCLE_CONTROL_VBIAS_DISABLE 0x00000000 /* Vbias: Vbias disabled */
Vkadaba 32:52445bef314d 752 #define ENUM_CORE_CYCLE_CONTROL_VBIAS_ENABLE 0x00002000 /* Vbias: Enable Vbias output for the duration of a cycle */
Vkadaba 59:3d395512b442 753 #define ENUM_CORE_CYCLE_CONTROL_OPEN_SW 0x00000000 /* GND_SW_CTRL: Ground Switch Opens outside of measurement cycle to conserve power */
Vkadaba 59:3d395512b442 754 #define ENUM_CORE_CYCLE_CONTROL_CLOSE_SW 0x00001000 /* GND_SW_CTRL: Ground Switch Closed */
Vkadaba 32:52445bef314d 755
Vkadaba 32:52445bef314d 756 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 32:52445bef314d 757 CORE_FIFO_NUM_CYCLES Pos/Masks Description
Vkadaba 32:52445bef314d 758 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 759 #define BITP_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0 /* Number of Cycles to Fill the FIFO */
Vkadaba 32:52445bef314d 760 #define BITM_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0x000000FF /* Number of Cycles to Fill the FIFO */
Vkadaba 5:0728bde67bdb 761
Vkadaba 5:0728bde67bdb 762 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 763 CORE_STATUS Pos/Masks Description
Vkadaba 5:0728bde67bdb 764 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 765 #define BITP_CORE_STATUS_LUT_ERROR 7 /* Indicates Error with One or More Lookup Tables */
Vkadaba 32:52445bef314d 766 #define BITP_CORE_STATUS_DIAG_CHECKSUM_ERROR 6 /* Indicates Error on Internal Checksum Calculations */
Vkadaba 6:9d393a9677f4 767 #define BITP_CORE_STATUS_FIFO_ERROR 5 /* Indicates Error with FIFO */
Vkadaba 32:52445bef314d 768 #define BITP_CORE_STATUS_CMD_RUNNING 4 /* Indicates Special Command Active */
Vkadaba 32:52445bef314d 769 #define BITP_CORE_STATUS_DRDY 3 /* Indicates New Sensor Result Available to Read */
Vkadaba 6:9d393a9677f4 770 #define BITP_CORE_STATUS_ERROR 2 /* Indicates an Error */
Vkadaba 32:52445bef314d 771 #define BITP_CORE_STATUS_ALERT_ACTIVE 1 /* Indicates One or More Sensor Alerts Active */
Vkadaba 32:52445bef314d 772 #define BITP_CORE_STATUS_CONFIGURATION_ERROR 0 /* Indicates Error with Programmed Configuration */
Vkadaba 32:52445bef314d 773 #define BITM_CORE_STATUS_LUT_ERROR 0x00000080 /* Indicates Error with One or More Lookup Tables */
Vkadaba 32:52445bef314d 774 #define BITM_CORE_STATUS_DIAG_CHECKSUM_ERROR 0x00000040 /* Indicates Error on Internal Checksum Calculations */
Vkadaba 6:9d393a9677f4 775 #define BITM_CORE_STATUS_FIFO_ERROR 0x00000020 /* Indicates Error with FIFO */
Vkadaba 59:3d395512b442 776 #define BITM_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates Special Command Active, Active Low */
Vkadaba 32:52445bef314d 777 #define BITM_CORE_STATUS_DRDY 0x00000008 /* Indicates New Sensor Result Available to Read */
Vkadaba 6:9d393a9677f4 778 #define BITM_CORE_STATUS_ERROR 0x00000004 /* Indicates an Error */
Vkadaba 32:52445bef314d 779 #define BITM_CORE_STATUS_ALERT_ACTIVE 0x00000002 /* Indicates One or More Sensor Alerts Active */
Vkadaba 32:52445bef314d 780 #define BITM_CORE_STATUS_CONFIGURATION_ERROR 0x00000001 /* Indicates Error with Programmed Configuration */
Vkadaba 5:0728bde67bdb 781
Vkadaba 5:0728bde67bdb 782 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 783 CORE_CHANNEL_ALERT_STATUS Pos/Masks Description
Vkadaba 5:0728bde67bdb 784 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 785 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 12 /* Indicates Channel 12 Alert Active */
Vkadaba 32:52445bef314d 786 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 11 /* Indicates Channel 11 Alert Active */
Vkadaba 32:52445bef314d 787 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 10 /* Indicates Channel 10 Alert Active */
Vkadaba 32:52445bef314d 788 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 9 /* Indicates Channel 9 Alert Active */
Vkadaba 32:52445bef314d 789 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 8 /* Indicates Channel 8 Alert Active */
Vkadaba 32:52445bef314d 790 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 7 /* Indicates Channel 7 Alert Active */
Vkadaba 32:52445bef314d 791 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 6 /* Indicates Channel 6 Alert Active */
Vkadaba 32:52445bef314d 792 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 5 /* Indicates Channel 5Alert Active */
Vkadaba 32:52445bef314d 793 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 4 /* Indicates Channel 4 Alert Active */
Vkadaba 32:52445bef314d 794 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 3 /* Indicates Channel 3 Alert Active */
Vkadaba 32:52445bef314d 795 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 2 /* Indicates Channel 2 Alert Active */
Vkadaba 32:52445bef314d 796 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 1 /* Indicates Channel 1 Alert Active */
Vkadaba 32:52445bef314d 797 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0 /* Indicates Channel 0 Alert Active */
Vkadaba 32:52445bef314d 798 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 0x00001000 /* Indicates Channel 12 Alert Active */
Vkadaba 32:52445bef314d 799 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 0x00000800 /* Indicates Channel 11 Alert Active */
Vkadaba 32:52445bef314d 800 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 0x00000400 /* Indicates Channel 10 Alert Active */
Vkadaba 32:52445bef314d 801 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 0x00000200 /* Indicates Channel 9 Alert Active */
Vkadaba 32:52445bef314d 802 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 0x00000100 /* Indicates Channel 8 Alert Active */
Vkadaba 32:52445bef314d 803 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 0x00000080 /* Indicates Channel 7 Alert Active */
Vkadaba 32:52445bef314d 804 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 0x00000040 /* Indicates Channel 6 Alert Active */
Vkadaba 32:52445bef314d 805 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 0x00000020 /* Indicates Channel 5Alert Active */
Vkadaba 32:52445bef314d 806 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 0x00000010 /* Indicates Channel 4 Alert Active */
Vkadaba 32:52445bef314d 807 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 0x00000008 /* Indicates Channel 3 Alert Active */
Vkadaba 32:52445bef314d 808 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 0x00000004 /* Indicates Channel 2 Alert Active */
Vkadaba 32:52445bef314d 809 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 0x00000002 /* Indicates Channel 1 Alert Active */
Vkadaba 32:52445bef314d 810 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0x00000001 /* Indicates Channel 0 Alert Active */
Vkadaba 5:0728bde67bdb 811
Vkadaba 5:0728bde67bdb 812 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 813 CORE_ALERT_DETAIL_CH[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 814 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 59:3d395512b442 815 #define BITP_CORE_ALERT_DETAIL_CH_THRESHOLD_EXCEEDED 8 /* Channel Threshold Limits Exceeded */
Vkadaba 32:52445bef314d 816 #define BITP_CORE_ALERT_DETAIL_CH_SENSOR_HARDFAULT 7 /* Indicates Sensor Hard Fault */
Vkadaba 32:52445bef314d 817 #define BITP_CORE_ALERT_DETAIL_CH_ADC_INPUT_OVERRANGE 6 /* Indicates the ADC Input is Overrange */
Vkadaba 32:52445bef314d 818 #define BITP_CORE_ALERT_DETAIL_CH_CJ_HARD_FAULT 5 /* Cold Junction Hard Fault */
Vkadaba 32:52445bef314d 819 #define BITP_CORE_ALERT_DETAIL_CH_CJ_SOFT_FAULT 4 /* Cold Junction Soft Fault */
Vkadaba 32:52445bef314d 820 #define BITP_CORE_ALERT_DETAIL_CH_SENSOR_OVERRANGE 3 /* Indicates If the Sensor is Overrange */
Vkadaba 32:52445bef314d 821 #define BITP_CORE_ALERT_DETAIL_CH_SENSOR_UNDERRANGE 2 /* Indicates If the Sensor is Underrange */
Vkadaba 32:52445bef314d 822 #define BITP_CORE_ALERT_DETAIL_CH_ADC_NEAR_OVERRANGE 1 /* Indicates If the ADC is Near Overrange */
Vkadaba 32:52445bef314d 823 #define BITP_CORE_ALERT_DETAIL_CH_RESULT_VALID 0 /* Set If a Result is Valid */
Vkadaba 59:3d395512b442 824 #define BITM_CORE_ALERT_DETAIL_CH_THRESHOLD_EXCEEDED 0x00000100 /* Channel Threshold Limits Exceeded */
Vkadaba 32:52445bef314d 825 #define BITM_CORE_ALERT_DETAIL_CH_SENSOR_HARDFAULT 0x00000080 /* Indicates Sensor Hard Fault */
Vkadaba 32:52445bef314d 826 #define BITM_CORE_ALERT_DETAIL_CH_ADC_INPUT_OVERRANGE 0x00000040 /* Indicates the ADC Input is Overrange */
Vkadaba 32:52445bef314d 827 #define BITM_CORE_ALERT_DETAIL_CH_CJ_HARD_FAULT 0x00000020 /* Cold Junction Hard Fault */
Vkadaba 32:52445bef314d 828 #define BITM_CORE_ALERT_DETAIL_CH_CJ_SOFT_FAULT 0x00000010 /* Cold Junction Soft Fault */
Vkadaba 32:52445bef314d 829 #define BITM_CORE_ALERT_DETAIL_CH_SENSOR_OVERRANGE 0x00000008 /* Indicates If the Sensor is Overrange */
Vkadaba 32:52445bef314d 830 #define BITM_CORE_ALERT_DETAIL_CH_SENSOR_UNDERRANGE 0x00000004 /* Indicates If the Sensor is Underrange */
Vkadaba 32:52445bef314d 831 #define BITM_CORE_ALERT_DETAIL_CH_ADC_NEAR_OVERRANGE 0x00000002 /* Indicates If the ADC is Near Overrange */
Vkadaba 32:52445bef314d 832 #define BITM_CORE_ALERT_DETAIL_CH_RESULT_VALID 0x00000001 /* Set If a Result is Valid */
Vkadaba 5:0728bde67bdb 833
Vkadaba 5:0728bde67bdb 834 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 835 CORE_ERROR_CODE Pos/Masks Description
Vkadaba 5:0728bde67bdb 836 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 837 #define BITP_CORE_ERROR_CODE_ERROR_CODE 0 /* Code Indicating Type of Error */
Vkadaba 6:9d393a9677f4 838 #define BITM_CORE_ERROR_CODE_ERROR_CODE 0x0000FFFF /* Code Indicating Type of Error */
Vkadaba 5:0728bde67bdb 839
Vkadaba 5:0728bde67bdb 840 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 841 CORE_EXTERNAL_REFERENCE_RESISTOR Pos/Masks Description
Vkadaba 5:0728bde67bdb 842 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 843 #define BITP_CORE_EXTERNAL_REFERENCE_RESISTOR_EXT_REFIN1_VALUE 0 /* External Reference Resistor Value */
Vkadaba 32:52445bef314d 844 #define BITM_CORE_EXTERNAL_REFERENCE_RESISTOR_EXT_REFIN1_VALUE 0xFFFFFFFF /* External Reference Resistor Value */
Vkadaba 5:0728bde67bdb 845
Vkadaba 5:0728bde67bdb 846 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 36:54e2418e7620 847 CORE_EXTERNAL_VOLTAGE_REFERENCE Pos/Masks Description
Vkadaba 36:54e2418e7620 848 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 36:54e2418e7620 849 #define BITP_CORE_EXTERNAL_VOLTAGE_REFERENCE_EXT_REFIN2_VALUE 0 /* Reference Input Value */
Vkadaba 36:54e2418e7620 850 #define BITM_CORE_EXTERNAL_VOLTAGE_REFERENCE_EXT_REFIN2_VALUE 0xFFFFFFFF /* Reference Input Value */
Vkadaba 36:54e2418e7620 851
Vkadaba 36:54e2418e7620 852 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 44:94bdfaefddac 853 CORE_AVDD_VOLTAGE Pos/Masks Description
Vkadaba 44:94bdfaefddac 854 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 44:94bdfaefddac 855 #define BITP_CORE_AVDD_VOLTAGE_AVDD_VOLTAGE 0 /* AVDD Voltage */
Vkadaba 44:94bdfaefddac 856 #define BITM_CORE_AVDD_VOLTAGE_AVDD_VOLTAGE 0xFFFFFFFF /* AVDD Voltage */
Vkadaba 44:94bdfaefddac 857
Vkadaba 44:94bdfaefddac 858 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 859 CORE_DIAGNOSTICS_CONTROL Pos/Masks Description
Vkadaba 5:0728bde67bdb 860 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 59:3d395512b442 861 #define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 1 /* Diagnostics Open Sensor Detect Frequency */
Vkadaba 32:52445bef314d 862 #define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0 /* Diagnostics Measure Enable */
Vkadaba 59:3d395512b442 863 #define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 0x000000FE /* Diagnostics Open Sensor Detect Frequency */
Vkadaba 32:52445bef314d 864 #define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0x00000001 /* Diagnostics Measure Enable */
Vkadaba 5:0728bde67bdb 865
Vkadaba 5:0728bde67bdb 866 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 59:3d395512b442 867 CORE_EXT_VBUFF Pos/Masks Description
Vkadaba 59:3d395512b442 868 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 59:3d395512b442 869 #define BITP_CORE_EXT_VBUFF_EXT_VBUFF 0 /* This field is used to configure the reference buffers */
Vkadaba 59:3d395512b442 870 #define BITM_CORE_EXT_VBUFF_EXT_VBUFF 0x00000003 /* This field is used to configure the reference buffers */
Vkadaba 59:3d395512b442 871 #define ENUM_CORE_EXT_VBUFF_BOTH_INACTIVE_MODE 0x00000000 /* EXT_VBUFF: Both Reference Buffers Disabled */
Vkadaba 59:3d395512b442 872 #define ENUM_CORE_EXT_VBUFF_BOTH_ACTIVE_MODE 0x00000001 /* EXT_VBUFF: Both Reference Buffers Enabled */
Vkadaba 59:3d395512b442 873 #define ENUM_CORE_EXT_VBUFF_ONLY_VPOS_MODE 0x00000002 /* EXT_VBUFF: VREF+ Enabled Only */
Vkadaba 59:3d395512b442 874
Vkadaba 59:3d395512b442 875 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 876 CORE_DATA_FIFO Pos/Masks Description
Vkadaba 5:0728bde67bdb 877 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 878 #define BITP_CORE_DATA_FIFO_DATA_FIFO 0 /* FIFO Buffer of Sensor Results */
Vkadaba 32:52445bef314d 879 #define BITM_CORE_DATA_FIFO_DATA_FIFO 0x000000FF /* FIFO Buffer of Sensor Results */
Vkadaba 5:0728bde67bdb 880
Vkadaba 5:0728bde67bdb 881 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 882 CORE_DEBUG_CODE Pos/Masks Description
Vkadaba 5:0728bde67bdb 883 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 884 #define BITP_CORE_DEBUG_CODE_DEBUG_CODE 0 /* Additional Information on Source of Alert or Errors */
Vkadaba 32:52445bef314d 885 #define BITM_CORE_DEBUG_CODE_DEBUG_CODE 0xFFFFFFFF /* Additional Information on Source of Alert or Errors */
Vkadaba 5:0728bde67bdb 886
Vkadaba 5:0728bde67bdb 887 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 32:52445bef314d 888 CORE_TEST_REG_ACCESS Pos/Masks Description
Vkadaba 5:0728bde67bdb 889 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 890 #define BITP_CORE_TEST_REG_ACCESS_TEST_ACCESS 0 /* Test Register Access. Specific Write Sequence Required */
Vkadaba 32:52445bef314d 891 #define BITM_CORE_TEST_REG_ACCESS_TEST_ACCESS 0x0000FFFF /* Test Register Access. Specific Write Sequence Required */
Vkadaba 5:0728bde67bdb 892
Vkadaba 5:0728bde67bdb 893 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 894 CORE_LUT_SELECT Pos/Masks Description
Vkadaba 5:0728bde67bdb 895 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 896 #define BITP_CORE_LUT_SELECT_LUT_RW 7 /* Read or Write LUT Data */
Vkadaba 6:9d393a9677f4 897 #define BITM_CORE_LUT_SELECT_LUT_RW 0x00000080 /* Read or Write LUT Data */
Vkadaba 32:52445bef314d 898 #define ENUM_CORE_LUT_SELECT_LUT_READ 0x00000000 /* LUT_RW: Read addressed LUT data */
Vkadaba 32:52445bef314d 899 #define ENUM_CORE_LUT_SELECT_LUT_WRITE 0x00000080 /* LUT_RW: Write addressed LUT data */
Vkadaba 5:0728bde67bdb 900
Vkadaba 5:0728bde67bdb 901 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 902 CORE_LUT_OFFSET Pos/Masks Description
Vkadaba 5:0728bde67bdb 903 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 904 #define BITP_CORE_LUT_OFFSET_LUT_OFFSET 0 /* Offset into the Lookup Table */
Vkadaba 44:94bdfaefddac 905 #define BITM_CORE_LUT_OFFSET_LUT_OFFSET 0x000007FF /* Offset into the Lookup Table */
Vkadaba 5:0728bde67bdb 906
Vkadaba 5:0728bde67bdb 907 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 908 CORE_LUT_DATA Pos/Masks Description
Vkadaba 5:0728bde67bdb 909 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 910 #define BITP_CORE_LUT_DATA_LUT_DATA 0 /* Data Byte to Write to and Read from the Lookup Table */
Vkadaba 32:52445bef314d 911 #define BITM_CORE_LUT_DATA_LUT_DATA 0x000000FF /* Data Byte to Write to and Read from the Lookup Table */
Vkadaba 5:0728bde67bdb 912
Vkadaba 5:0728bde67bdb 913 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 914 CORE_REVISION Pos/Masks Description
Vkadaba 5:0728bde67bdb 915 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 916 #define BITP_CORE_REVISION_REV_MAJOR 24 /* Major Revision Information */
Vkadaba 6:9d393a9677f4 917 #define BITP_CORE_REVISION_REV_MINOR 16 /* Minor Revision Information */
Vkadaba 6:9d393a9677f4 918 #define BITP_CORE_REVISION_REV_PATCH 0 /* Patch Revision Information */
Vkadaba 6:9d393a9677f4 919 #define BITM_CORE_REVISION_REV_MAJOR 0xFF000000 /* Major Revision Information */
Vkadaba 6:9d393a9677f4 920 #define BITM_CORE_REVISION_REV_MINOR 0x00FF0000 /* Minor Revision Information */
Vkadaba 6:9d393a9677f4 921 #define BITM_CORE_REVISION_REV_PATCH 0x0000FFFF /* Patch Revision Information */
Vkadaba 5:0728bde67bdb 922
Vkadaba 5:0728bde67bdb 923 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 924 CORE_CHANNEL_COUNT[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 925 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 5:0728bde67bdb 926 #define BITP_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 7 /* Enable Channel in Measurement Cycle */
Vkadaba 32:52445bef314d 927 #define BITP_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0 /* How Many Times Channel Appears in One Cycle */
Vkadaba 5:0728bde67bdb 928 #define BITM_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 0x00000080 /* Enable Channel in Measurement Cycle */
Vkadaba 32:52445bef314d 929 #define BITM_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0x0000007F /* How Many Times Channel Appears in One Cycle */
Vkadaba 5:0728bde67bdb 930
Vkadaba 5:0728bde67bdb 931 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 932 CORE_CHANNEL_OPTIONS[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 933 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 5:0728bde67bdb 934 #define BITP_CORE_CHANNEL_OPTIONS_CHANNEL_PRIORITY 0 /* Indicates Priority or Position of This Channel in Sequence */
Vkadaba 5:0728bde67bdb 935 #define BITM_CORE_CHANNEL_OPTIONS_CHANNEL_PRIORITY 0x0000000F /* Indicates Priority or Position of This Channel in Sequence */
Vkadaba 5:0728bde67bdb 936
Vkadaba 5:0728bde67bdb 937 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 938 CORE_SENSOR_TYPE[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 939 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 940 #define BITP_CORE_SENSOR_TYPE_SENSOR_TYPE 0 /* Sensor Type */
Vkadaba 6:9d393a9677f4 941 #define BITM_CORE_SENSOR_TYPE_SENSOR_TYPE 0x00000FFF /* Sensor Type */
Vkadaba 32:52445bef314d 942 #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_T 0x00000000 /* Sensor_Type: Thermocouple T-Type sensor */
Vkadaba 32:52445bef314d 943 #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_J 0x00000001 /* Sensor_Type: Thermocouple J-Type Sensor */
Vkadaba 32:52445bef314d 944 #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_K 0x00000002 /* Sensor_Type: Thermocouple K-Type Sensor */
Vkadaba 59:3d395512b442 945 #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_E 0x00000003 /* Sensor_Type: Thermocouple E-Type Sensor */
Vkadaba 59:3d395512b442 946 #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_N 0x00000004 /* Sensor_Type: Thermocouple N-Type Sensor */
Vkadaba 59:3d395512b442 947 #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_R 0x00000005 /* Sensor_Type: Thermocouple R-Type Sensor */
Vkadaba 59:3d395512b442 948 #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_S 0x00000006 /* Sensor_Type: Thermocouple S-Type Sensor */
Vkadaba 59:3d395512b442 949 #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_B 0x00000007 /* Sensor_Type: Thermocouple B-Type Sensor */
Vkadaba 59:3d395512b442 950 #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_CUSTOM 0x00000008 /* Sensor_Type: Thermocouple CUSTOM-Type Sensor */
Vkadaba 32:52445bef314d 951 #define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT100 0x00000020 /* Sensor_Type: RTD 2 wire PT100 sensor */
Vkadaba 32:52445bef314d 952 #define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT1000 0x00000021 /* Sensor_Type: RTD 2 wire PT1000 sensor */
Vkadaba 59:3d395512b442 953 #define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT10 0x00000022 /* Sensor_Type: RTD 2 wire PT10 sensor */
Vkadaba 59:3d395512b442 954 #define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT50 0x00000023 /* Sensor_Type: RTD 2 wire PT50 sensor */
Vkadaba 59:3d395512b442 955 #define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT200 0x00000024 /* Sensor_Type: RTD 2 wire PT200 sensor */
Vkadaba 59:3d395512b442 956 #define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT500 0x00000025 /* Sensor_Type: RTD 2 wire PT500 sensor */
Vkadaba 59:3d395512b442 957 #define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT1000_0P00375 0x00000026 /* Sensor_Type: RTD 2 wire PT1000 sensor */
Vkadaba 59:3d395512b442 958 #define ENUM_CORE_SENSOR_TYPE_RTD_2W_NI120 0x00000027 /* Sensor_Type: RTD 2 wire PT1000 sensor */
Vkadaba 59:3d395512b442 959 #define ENUM_CORE_SENSOR_TYPE_RTD_2W_CUSTOM 0x00000028 /* Sensor_Type: RTD 2 wire Custom sensor */
Vkadaba 32:52445bef314d 960 #define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT100 0x00000040 /* Sensor_Type: RTD 3 wire PT100 sensor */
Vkadaba 32:52445bef314d 961 #define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT1000 0x00000041 /* Sensor_Type: RTD 3 wire PT1000 sensor */
Vkadaba 59:3d395512b442 962 #define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT10 0x00000042 /* Sensor_Type: RTD 3 wire PT10 sensor */
Vkadaba 59:3d395512b442 963 #define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT50 0x00000043 /* Sensor_Type: RTD 3 wire PT50 sensor */
Vkadaba 59:3d395512b442 964 #define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT200 0x00000044 /* Sensor_Type: RTD 3 wire PT200 sensor */
Vkadaba 59:3d395512b442 965 #define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT500 0x00000045 /* Sensor_Type: RTD 3 wire PT500 sensor */
Vkadaba 59:3d395512b442 966 #define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT1000_0P00375 0x00000046 /* Sensor_Type: RTD 3 wire PT1000 sensor */
Vkadaba 59:3d395512b442 967 #define ENUM_CORE_SENSOR_TYPE_RTD_3W_NI120 0x00000047 /* Sensor_Type: RTD 3 wire NI120 sensor */
Vkadaba 59:3d395512b442 968 #define ENUM_CORE_SENSOR_TYPE_RTD_3W_CUSTOM 0x00000048 /* Sensor_Type: RTD 3 wire Custom sensor */
Vkadaba 32:52445bef314d 969 #define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT100 0x00000060 /* Sensor_Type: RTD 4 wire PT100 sensor */
Vkadaba 32:52445bef314d 970 #define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT1000 0x00000061 /* Sensor_Type: RTD 4 wire PT1000 sensor */
Vkadaba 59:3d395512b442 971 #define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT10 0x00000062 /* Sensor_Type: RTD 4 wire PT10 sensor */
Vkadaba 59:3d395512b442 972 #define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT50 0x00000063 /* Sensor_Type: RTD 4 wire PT50 sensor */
Vkadaba 59:3d395512b442 973 #define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT200 0x00000064 /* Sensor_Type: RTD 4 wire PT200 sensor */
Vkadaba 59:3d395512b442 974 #define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT500 0x00000065 /* Sensor_Type: RTD 4 wire PT500 sensor */
Vkadaba 59:3d395512b442 975 #define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT1000_0P00375 0x00000066 /* Sensor_Type: RTD 4 wire PT1000 0.00375 sensor */
Vkadaba 59:3d395512b442 976 #define ENUM_CORE_SENSOR_TYPE_RTD_4W_NI120 0x00000067 /* Sensor_Type: RTD 4 wire NI120 */
Vkadaba 59:3d395512b442 977 #define ENUM_CORE_SENSOR_TYPE_RTD_4W_CUSTOM 0x00000068 /* Sensor_Type: RTD 4 wire Custom sensor */
Vkadaba 59:3d395512b442 978 #define ENUM_CORE_SENSOR_TYPE_THERMISTOR_44004_44033_2P252K_AT_25C 0x00000080 /* Sensor_Type: THERMISTOR_44004_44033_2P252K_AT_25C */
Vkadaba 59:3d395512b442 979 #define ENUM_CORE_SENSOR_TYPE_THERMISTOR_44005_44030_3K_AT_25C 0x00000081 /* Sensor_Type: THERMISTOR_44005_44030_3K_AT_25C */
Vkadaba 59:3d395512b442 980 #define ENUM_CORE_SENSOR_TYPE_THERMISTOR_44007_44034_5K_AT_25C 0x00000082 /* Sensor_Type: THERMISTOR_44007_44034_5K_AT_25C */
Vkadaba 59:3d395512b442 981 #define ENUM_CORE_SENSOR_TYPE_THERMISTOR_44006_44031_10K_AT_25C 0x00000083 /* Sensor_Type: THERMISTOR_44006_44031_10K_AT_25C */
Vkadaba 59:3d395512b442 982 #define ENUM_CORE_SENSOR_TYPE_THERMISTOR_44008_44032_30K_AT_25C 0x00000084 /* Sensor_Type: THERMISTOR_44008_44032_30K_AT_25C */
Vkadaba 59:3d395512b442 983 #define ENUM_CORE_SENSOR_TYPE_THERMISTOR_YSI_400 0x00000085 /* Sensor_Type: THERMISTOR_YSI_400 */
Vkadaba 59:3d395512b442 984 #define ENUM_CORE_SENSOR_TYPE_THERMISTOR_SPECTRUM_1003K_1K 0x00000086 /* Sensor_Type: THERMISTOR_SPECTRUM_1003K_1K */
Vkadaba 59:3d395512b442 985 #define ENUM_CORE_SENSOR_TYPE_THERMISTOR_CUSTOM_STEINHART_HART 0x00000087 /* Sensor_Type: THERMISTOR_CUSTOM_STEINHART_HART */
Vkadaba 59:3d395512b442 986 #define ENUM_CORE_SENSOR_TYPE_THERMISTOR_CUSTOM_TABLE 0x00000088 /* Sensor_Type: THERMISTOR_CUSTOM_TABLE */
Vkadaba 59:3d395512b442 987 #define ENUM_CORE_SENSOR_TYPE_BRIDGE_4WIRE 0x000000A8 /* Sensor_Type: Bridge 4 wire sensor */
Vkadaba 59:3d395512b442 988 #define ENUM_CORE_SENSOR_TYPE_BRIDGE_6WIRE 0x000000C8 /* Sensor_Type: Bridge 6 wire sensor */
Vkadaba 59:3d395512b442 989 #define ENUM_CORE_SENSOR_TYPE_DIODE 0x000000E0 /* Sensor_Type: DIODE Temperature Sensor */
Vkadaba 59:3d395512b442 990 #define ENUM_CORE_SENSOR_TYPE_SINGLE_ENDED_ABSOLUTE 0x00000240 /* Sensor_Type: Voltage Input Single Ended on V+ */
Vkadaba 59:3d395512b442 991 #define ENUM_CORE_SENSOR_TYPE_DIFFERENTIAL_ABSOLUTE 0x00000280 /* Sensor_Type: Voltage Input Differential Ended on V+ and V- */
Vkadaba 59:3d395512b442 992 #define ENUM_CORE_SENSOR_TYPE_SINGLE_ENDED_RATIO 0x00000290 /* Sensor_Type: Ratiometeric Output, Voltage_IN/Voltage_Reference */
Vkadaba 59:3d395512b442 993 #define ENUM_CORE_SENSOR_TYPE_DIFFERENTIAL_RATIO 0x000002A0 /* Sensor_Type: Ratiometeric Output, Voltage_IN/Voltage_Reference */
Vkadaba 59:3d395512b442 994 #define ENUM_CORE_SENSOR_TYPE_I2C_HUMIDITY 0x00000840 /* Sensor_Type: I2C humidity sensor B */
Vkadaba 59:3d395512b442 995 #define ENUM_CORE_SENSOR_TYPE_I2C_TEMPERATURE_ADT742X 0x000008AA /* Sensor_Type: ADI Precision I2C Digital Temperature Sensor */
Vkadaba 5:0728bde67bdb 996
Vkadaba 5:0728bde67bdb 997 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 998 CORE_SENSOR_DETAILS[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 999 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 32:52445bef314d 1000 #define BITP_CORE_SENSOR_DETAILS_COMPENSATION_DISABLE 31 /* This Bit Indicates Compensation Data Must Not Be Used */
Vkadaba 32:52445bef314d 1001 #define BITP_CORE_SENSOR_DETAILS_RTD_CURVE 27 /* Select RTD Curve for Linearization */
Vkadaba 6:9d393a9677f4 1002 #define BITP_CORE_SENSOR_DETAILS_PGA_GAIN 24 /* PGA Gain */
Vkadaba 5:0728bde67bdb 1003 #define BITP_CORE_SENSOR_DETAILS_REFERENCE_SELECT 20 /* Reference Selection */
Vkadaba 5:0728bde67bdb 1004 #define BITP_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 17 /* Do Not Publish Channel Result */
Vkadaba 8:2f2775c34640 1005 #define BITP_CORE_SENSOR_DETAILS_LUT_SELECT 15 /* Lookup Table Select */
Vkadaba 32:52445bef314d 1006 #define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 4 /* Indicates Which Channel Used to Compensate the Sensor Result */
Vkadaba 5:0728bde67bdb 1007 #define BITP_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0 /* Units of Sensor Measurement */
Vkadaba 32:52445bef314d 1008 #define BITM_CORE_SENSOR_DETAILS_COMPENSATION_DISABLE 0x80000000 /* This Bit Indicates Compensation Data Must Not Be Used */
Vkadaba 32:52445bef314d 1009 #define BITM_CORE_SENSOR_DETAILS_RTD_CURVE 0x18000000 /* Select RTD Curve for Linearization */
Vkadaba 6:9d393a9677f4 1010 #define BITM_CORE_SENSOR_DETAILS_PGA_GAIN 0x07000000 /* PGA Gain */
Vkadaba 5:0728bde67bdb 1011 #define BITM_CORE_SENSOR_DETAILS_REFERENCE_SELECT 0x00F00000 /* Reference Selection */
Vkadaba 5:0728bde67bdb 1012 #define BITM_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 0x00020000 /* Do Not Publish Channel Result */
Vkadaba 8:2f2775c34640 1013 #define BITM_CORE_SENSOR_DETAILS_LUT_SELECT 0x00018000 /* Lookup Table Select */
Vkadaba 32:52445bef314d 1014 #define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 0x000000F0 /* Indicates Which Channel Used to Compensate the Sensor Result */
Vkadaba 5:0728bde67bdb 1015 #define BITM_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0x0000000F /* Units of Sensor Measurement */
Vkadaba 32:52445bef314d 1016 #define ENUM_CORE_SENSOR_DETAILS_EUROPEAN_CURVE 0x00000000 /* RTD_Curve: European curve */
Vkadaba 32:52445bef314d 1017 #define ENUM_CORE_SENSOR_DETAILS_AMERICAN_CURVE 0x08000000 /* RTD_Curve: American curve */
Vkadaba 32:52445bef314d 1018 #define ENUM_CORE_SENSOR_DETAILS_JAPANESE_CURVE 0x10000000 /* RTD_Curve: Japanese curve */
Vkadaba 32:52445bef314d 1019 #define ENUM_CORE_SENSOR_DETAILS_ITS90_CURVE 0x18000000 /* RTD_Curve: ITS-90 curve */
Vkadaba 6:9d393a9677f4 1020 #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_1 0x00000000 /* PGA_Gain: Gain of 1 */
Vkadaba 6:9d393a9677f4 1021 #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_2 0x01000000 /* PGA_Gain: Gain of 2 */
Vkadaba 6:9d393a9677f4 1022 #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_4 0x02000000 /* PGA_Gain: Gain of 4 */
Vkadaba 6:9d393a9677f4 1023 #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_8 0x03000000 /* PGA_Gain: Gain of 8 */
Vkadaba 5:0728bde67bdb 1024 #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_16 0x04000000 /* PGA_Gain: Gain of 16 */
Vkadaba 5:0728bde67bdb 1025 #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_32 0x05000000 /* PGA_Gain: Gain of 32 */
Vkadaba 5:0728bde67bdb 1026 #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_64 0x06000000 /* PGA_Gain: Gain of 64 */
Vkadaba 5:0728bde67bdb 1027 #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_128 0x07000000 /* PGA_Gain: Gain of 128 */
Vkadaba 6:9d393a9677f4 1028 #define ENUM_CORE_SENSOR_DETAILS_REF_VINT 0x00000000 /* Reference_Select: Internal voltage reference (1.2V) */
Vkadaba 32:52445bef314d 1029 #define ENUM_CORE_SENSOR_DETAILS_REF_VEXT1 0x00100000 /* Reference_Select: External voltage reference applied to VERF+ and VREF- */
Vkadaba 32:52445bef314d 1030 #define ENUM_CORE_SENSOR_DETAILS_REF_AVDD 0x00300000 /* Reference_Select: AVDD supply internally used as reference */
Vkadaba 32:52445bef314d 1031 #define ENUM_CORE_SENSOR_DETAILS_LUT_DEFAULT 0x00000000 /* LUT_Select: Default lookup table for selected sensor type */
Vkadaba 59:3d395512b442 1032 #define ENUM_CORE_SENSOR_DETAILS_LUT_CUSTOM 0x00008000 /* LUT_Select: User defined custom lookup table. */
Vkadaba 59:3d395512b442 1033 #define ENUM_CORE_SENSOR_DETAILS_LUT_RESERVED 0x00010000 /* LUT_Select: Reserved */
Vkadaba 5:0728bde67bdb 1034 #define ENUM_CORE_SENSOR_DETAILS_UNITS_UNSPECIFIED 0x00000000 /* Measurement_Units: Not Specified */
Vkadaba 5:0728bde67bdb 1035 #define ENUM_CORE_SENSOR_DETAILS_UNITS_RESERVED 0x00000001 /* Measurement_Units: Reserved */
Vkadaba 6:9d393a9677f4 1036 #define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGC 0x00000002 /* Measurement_Units: Degrees C */
Vkadaba 6:9d393a9677f4 1037 #define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGF 0x00000003 /* Measurement_Units: Degrees F */
Vkadaba 5:0728bde67bdb 1038
Vkadaba 5:0728bde67bdb 1039 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 1040 CORE_CHANNEL_EXCITATION[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 1041 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 44:94bdfaefddac 1042 #define BITP_CORE_CHANNEL_EXCITATION_IOUT_DIODE_RATIO 6 /* Modify Current Ratios Used for Diode Sensor */
Vkadaba 5:0728bde67bdb 1043 #define BITP_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0 /* Current Source Value */
Vkadaba 44:94bdfaefddac 1044 #define BITM_CORE_CHANNEL_EXCITATION_IOUT_DIODE_RATIO 0x000001C0 /* Modify Current Ratios Used for Diode Sensor */
Vkadaba 6:9d393a9677f4 1045 #define BITM_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0x0000000F /* Current Source Value */
Vkadaba 44:94bdfaefddac 1046 #define ENUM_CORE_CHANNEL_EXCITATION_DIODE_2PT_10UA_100UA 0x00000000 /* IOUT_Diode_Ratio: 2 Current measurement 10uA 100uA */
Vkadaba 44:94bdfaefddac 1047 #define ENUM_CORE_CHANNEL_EXCITATION_DIODE_2PT_20UA_160UA 0x00000040 /* IOUT_Diode_Ratio: 2 Current measurement 20uA 160uA */
Vkadaba 44:94bdfaefddac 1048 #define ENUM_CORE_CHANNEL_EXCITATION_DIODE_2PT_50UA_300UA 0x00000080 /* IOUT_Diode_Ratio: 2 Current measurement 50uA 300uA */
Vkadaba 44:94bdfaefddac 1049 #define ENUM_CORE_CHANNEL_EXCITATION_DIODE_2PT_100UA_600UA 0x000000C0 /* IOUT_Diode_Ratio: 2 Current measurement 100uA 600uA */
Vkadaba 44:94bdfaefddac 1050 #define ENUM_CORE_CHANNEL_EXCITATION_DIODE_3PT_10UA_50UA_100UA 0x00000100 /* IOUT_Diode_Ratio: 3 current measuremet 10uA 50uA 100uA */
Vkadaba 44:94bdfaefddac 1051 #define ENUM_CORE_CHANNEL_EXCITATION_DIODE_3PT_20UA_100UA_160UA 0x00000140 /* IOUT_Diode_Ratio: 3 current measuremet 20uA 100uA 160uA */
Vkadaba 44:94bdfaefddac 1052 #define ENUM_CORE_CHANNEL_EXCITATION_DIODE_3PT_50UA_150UA_300UA 0x00000180 /* IOUT_Diode_Ratio: 3 current measuremet 50uA 150uA 300uA */
Vkadaba 44:94bdfaefddac 1053 #define ENUM_CORE_CHANNEL_EXCITATION_DIODE_3PT_100UA_300UA_600UA 0x000001C0 /* IOUT_Diode_Ratio: 3 current measuremet 100uA 300uA 600uA */
Vkadaba 32:52445bef314d 1054 #define ENUM_CORE_CHANNEL_EXCITATION_NONE 0x00000000 /* IOUT_Excitation_Current: Excitation Current Disabled */
Vkadaba 6:9d393a9677f4 1055 #define ENUM_CORE_CHANNEL_EXCITATION_RESERVED 0x00000001 /* IOUT_Excitation_Current: Reserved */
Vkadaba 6:9d393a9677f4 1056 #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_10UA 0x00000002 /* IOUT_Excitation_Current: 10 \mu;A */
Vkadaba 6:9d393a9677f4 1057 #define ENUM_CORE_CHANNEL_EXCITATION_RESERVED2 0x00000003 /* IOUT_Excitation_Current: Reserved */
Vkadaba 6:9d393a9677f4 1058 #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_50UA 0x00000004 /* IOUT_Excitation_Current: 50 \mu;A */
Vkadaba 6:9d393a9677f4 1059 #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_100UA 0x00000005 /* IOUT_Excitation_Current: 100 \mu;A */
Vkadaba 6:9d393a9677f4 1060 #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_250UA 0x00000006 /* IOUT_Excitation_Current: 250 \mu;A */
Vkadaba 6:9d393a9677f4 1061 #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_500UA 0x00000007 /* IOUT_Excitation_Current: 500 \mu;A */
Vkadaba 6:9d393a9677f4 1062 #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_1000UA 0x00000008 /* IOUT_Excitation_Current: 1000 \mu;A */
Vkadaba 32:52445bef314d 1063 #define ENUM_CORE_CHANNEL_EXCITATION_EXTERNAL 0x0000000F /* IOUT_Excitation_Current: External current sourced */
Vkadaba 5:0728bde67bdb 1064
Vkadaba 5:0728bde67bdb 1065 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 1066 CORE_SETTLING_TIME[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 1067 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 59:3d395512b442 1068 #define BITP_CORE_SETTLING_TIME_SETTLING_TIME 0 /* Additional Settling Time in Milliseconds. Max 255ms */
Vkadaba 59:3d395512b442 1069 #define BITM_CORE_SETTLING_TIME_SETTLING_TIME 0x000000FF /* Additional Settling Time in Milliseconds. Max 255ms */
Vkadaba 5:0728bde67bdb 1070
Vkadaba 5:0728bde67bdb 1071 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 1072 CORE_MEASUREMENT_SETUP[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 1073 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 8:2f2775c34640 1074 #define BITP_CORE_MEASUREMENT_SETUP_BUFFER_BYPASS 15 /* Disable Buffers */
Vkadaba 6:9d393a9677f4 1075 #define BITP_CORE_MEASUREMENT_SETUP_ADC_FILTER_TYPE 12 /* ADC Digital Filter Type */
Vkadaba 6:9d393a9677f4 1076 #define BITP_CORE_MEASUREMENT_SETUP_CHOP_MODE 10 /* Enabled and Disable Chop Mode */
Vkadaba 6:9d393a9677f4 1077 #define BITP_CORE_MEASUREMENT_SETUP_NOTCH_EN_2 8 /* Enable Notch 2 Filter Mode */
Vkadaba 32:52445bef314d 1078 #define BITP_CORE_MEASUREMENT_SETUP_ADC_SF 0 /* ADC Digital Filter Speed */
Vkadaba 8:2f2775c34640 1079 #define BITM_CORE_MEASUREMENT_SETUP_BUFFER_BYPASS 0x00008000 /* Disable Buffers */
Vkadaba 6:9d393a9677f4 1080 #define BITM_CORE_MEASUREMENT_SETUP_ADC_FILTER_TYPE 0x00001000 /* ADC Digital Filter Type */
Vkadaba 59:3d395512b442 1081 #define BITM_CORE_MEASUREMENT_SETUP_CHOP_MODE 0x00000400 /* Enabled and Disable Chop Mode */
Vkadaba 6:9d393a9677f4 1082 #define BITM_CORE_MEASUREMENT_SETUP_NOTCH_EN_2 0x00000100 /* Enable Notch 2 Filter Mode */
Vkadaba 32:52445bef314d 1083 #define BITM_CORE_MEASUREMENT_SETUP_ADC_SF 0x0000007F /* ADC Digital Filter Speed */
Vkadaba 32:52445bef314d 1084 #define ENUM_CORE_MEASUREMENT_SETUP_BUFFERS_ENABLED 0x00000000 /* Buffer_Bypass: Input buffers enabled */
Vkadaba 32:52445bef314d 1085 #define ENUM_CORE_MEASUREMENT_SETUP_BUFFERS_DISABLED 0x00008000 /* Buffer_Bypass: Input buffers disabled */
Vkadaba 32:52445bef314d 1086 #define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_SINC4 0x00000000 /* ADC_Filter_Type: Enabled SINC4 filter */
Vkadaba 32:52445bef314d 1087 #define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_SINC3 0x00001000 /* ADC_Filter_Type: Enabled SINC3 filter */
Vkadaba 32:52445bef314d 1088 #define ENUM_CORE_MEASUREMENT_SETUP_DISABLE_CHOP 0x00000000 /* Chop_Mode: ADC front end chopping disabled */
Vkadaba 59:3d395512b442 1089 #define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_CHOP 0x00000400 /* Chop_Mode: ADC front end chopping enabled */
Vkadaba 32:52445bef314d 1090 #define ENUM_CORE_MEASUREMENT_SETUP_NOTCH_DIS 0x00000000 /* NOTCH_EN_2: Disable notch filter */
Vkadaba 32:52445bef314d 1091 #define ENUM_CORE_MEASUREMENT_SETUP_NOTCH_EN 0x00000100 /* NOTCH_EN_2: Enable notch 2 filter option. */
Vkadaba 5:0728bde67bdb 1092
Vkadaba 5:0728bde67bdb 1093 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 1094 CORE_HIGH_THRESHOLD_LIMIT[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 1095 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 5:0728bde67bdb 1096 #define BITP_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0 /* Upper Limit for Sensor Alert Comparison */
Vkadaba 32:52445bef314d 1097 #define BITM_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0xFFFFFFFF /* Upper Limit for Sensor Alert Comparison */
Vkadaba 5:0728bde67bdb 1098
Vkadaba 5:0728bde67bdb 1099 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 1100 CORE_LOW_THRESHOLD_LIMIT[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 1101 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 5:0728bde67bdb 1102 #define BITP_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0 /* Lower Limit for Sensor Alert Comparison */
Vkadaba 32:52445bef314d 1103 #define BITM_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0xFFFFFFFF /* Lower Limit for Sensor Alert Comparison */
Vkadaba 5:0728bde67bdb 1104
Vkadaba 5:0728bde67bdb 1105 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 1106 CORE_SENSOR_OFFSET[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 1107 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 5:0728bde67bdb 1108 #define BITP_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0 /* Sensor Offset Adjustment */
Vkadaba 32:52445bef314d 1109 #define BITM_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0xFFFFFFFF /* Sensor Offset Adjustment */
Vkadaba 5:0728bde67bdb 1110
Vkadaba 5:0728bde67bdb 1111 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 1112 CORE_SENSOR_GAIN[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 1113 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 1114 #define BITP_CORE_SENSOR_GAIN_SENSOR_GAIN 0 /* Sensor Gain Adjustment */
Vkadaba 32:52445bef314d 1115 #define BITM_CORE_SENSOR_GAIN_SENSOR_GAIN 0xFFFFFFFF /* Sensor Gain Adjustment */
Vkadaba 5:0728bde67bdb 1116
Vkadaba 5:0728bde67bdb 1117 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 1118 CORE_CHANNEL_SKIP[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 1119 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 6:9d393a9677f4 1120 #define BITP_CORE_CHANNEL_SKIP_CHANNEL_SKIP 0 /* Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 6:9d393a9677f4 1121 #define BITM_CORE_CHANNEL_SKIP_CHANNEL_SKIP 0x000000FF /* Indicates If Channel Will Skip Some Measurement Cycles */
Vkadaba 5:0728bde67bdb 1122
Vkadaba 5:0728bde67bdb 1123 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 44:94bdfaefddac 1124 CORE_SENSOR_PARAMETER[n] Pos/Masks Description
Vkadaba 44:94bdfaefddac 1125 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 44:94bdfaefddac 1126 #define BITP_CORE_SENSOR_PARAMETER_SENSOR_PARAMETER 0 /* Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 1127 #define BITM_CORE_SENSOR_PARAMETER_SENSOR_PARAMETER 0xFFFFFFFF /* Sensor Parameter Adjustment */
Vkadaba 44:94bdfaefddac 1128
Vkadaba 44:94bdfaefddac 1129 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 1130 CORE_DIGITAL_SENSOR_CONFIG[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 1131 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 5:0728bde67bdb 1132 #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_DATA_BITS 11 /* Number of Relevant Data Bits */
Vkadaba 5:0728bde67bdb 1133 #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_READ_BYTES 8 /* Number of Bytes to Read from the Sensor */
Vkadaba 5:0728bde67bdb 1134 #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_BIT_OFFSET 4 /* Data Bit Offset, Relative to Alignment */
Vkadaba 5:0728bde67bdb 1135 #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LEFT_ALIGNED 3 /* Data Alignment Within the Data Frame */
Vkadaba 5:0728bde67bdb 1136 #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LITTLE_ENDIAN 2 /* Data Endianness of Sensor Result */
Vkadaba 5:0728bde67bdb 1137 #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_CODING 0 /* Data Encoding of Sensor Result */
Vkadaba 5:0728bde67bdb 1138 #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_DATA_BITS 0x0000F800 /* Number of Relevant Data Bits */
Vkadaba 5:0728bde67bdb 1139 #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_READ_BYTES 0x00000700 /* Number of Bytes to Read from the Sensor */
Vkadaba 5:0728bde67bdb 1140 #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_BIT_OFFSET 0x000000F0 /* Data Bit Offset, Relative to Alignment */
Vkadaba 5:0728bde67bdb 1141 #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LEFT_ALIGNED 0x00000008 /* Data Alignment Within the Data Frame */
Vkadaba 5:0728bde67bdb 1142 #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LITTLE_ENDIAN 0x00000004 /* Data Endianness of Sensor Result */
Vkadaba 5:0728bde67bdb 1143 #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_CODING 0x00000003 /* Data Encoding of Sensor Result */
Vkadaba 5:0728bde67bdb 1144 #define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_NONE 0x00000000 /* Digital_Sensor_Coding: None/Invalid */
Vkadaba 5:0728bde67bdb 1145 #define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_UNIPOLAR 0x00000001 /* Digital_Sensor_Coding: Unipolar */
Vkadaba 32:52445bef314d 1146 #define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL 0x00000002 /* Digital_Sensor_Coding: Twos complement */
Vkadaba 32:52445bef314d 1147 #define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY 0x00000003 /* Digital_Sensor_Coding: Offset binary */
Vkadaba 5:0728bde67bdb 1148
Vkadaba 5:0728bde67bdb 1149 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 1150 CORE_DIGITAL_SENSOR_ADDRESS[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 1151 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 5:0728bde67bdb 1152 #define BITP_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0 /* I2C Address or Write Address Command for SPI Sensor */
Vkadaba 5:0728bde67bdb 1153 #define BITM_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0x000000FF /* I2C Address or Write Address Command for SPI Sensor */
Vkadaba 5:0728bde67bdb 1154
Vkadaba 5:0728bde67bdb 1155 /* -------------------------------------------------------------------------------------------------------------------------
Vkadaba 6:9d393a9677f4 1156 CORE_DIGITAL_SENSOR_COMMS[n] Pos/Masks Description
Vkadaba 5:0728bde67bdb 1157 ------------------------------------------------------------------------------------------------------------------------- */
Vkadaba 5:0728bde67bdb 1158 #define BITP_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE 10 /* Configuration for Sensor SPI Protocol */
Vkadaba 5:0728bde67bdb 1159 #define BITP_CORE_DIGITAL_SENSOR_COMMS_I2C_CLOCK 5 /* Controls SCLK Frequency for I2C Sensors */
Vkadaba 5:0728bde67bdb 1160 #define BITP_CORE_DIGITAL_SENSOR_COMMS_SPI_CLOCK 1 /* Controls Clock Frequency for SPI Sensors */
Vkadaba 5:0728bde67bdb 1161 #define BITM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE 0x00000C00 /* Configuration for Sensor SPI Protocol */
Vkadaba 5:0728bde67bdb 1162 #define BITM_CORE_DIGITAL_SENSOR_COMMS_I2C_CLOCK 0x00000060 /* Controls SCLK Frequency for I2C Sensors */
Vkadaba 5:0728bde67bdb 1163 #define BITM_CORE_DIGITAL_SENSOR_COMMS_SPI_CLOCK 0x0000001E /* Controls Clock Frequency for SPI Sensors */
Vkadaba 32:52445bef314d 1164 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 0x00000000 /* SPI_Mode: Clock polarity = 0 Clock phase = 0 */
Vkadaba 32:52445bef314d 1165 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 0x00000400 /* SPI_Mode: Clock polarity = 0 Clock phase = 1 */
Vkadaba 32:52445bef314d 1166 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 0x00000800 /* SPI_Mode: Clock polarity = 1 Clock phase = 0 */
Vkadaba 32:52445bef314d 1167 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 0x00000C00 /* SPI_Mode: Clock polarity = 1 Clock phase = 1 */
Vkadaba 5:0728bde67bdb 1168 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_100K 0x00000000 /* I2C_Clock: 100kHz SCL */
Vkadaba 5:0728bde67bdb 1169 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_400K 0x00000020 /* I2C_Clock: 400kHz SCL */
Vkadaba 5:0728bde67bdb 1170 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED1 0x00000040 /* I2C_Clock: Reserved */
Vkadaba 5:0728bde67bdb 1171 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED2 0x00000060 /* I2C_Clock: Reserved */
Vkadaba 6:9d393a9677f4 1172 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_8MHZ 0x00000000 /* SPI_Clock: 8MHz */
Vkadaba 6:9d393a9677f4 1173 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_4MHZ 0x00000002 /* SPI_Clock: 4MHz */
Vkadaba 6:9d393a9677f4 1174 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_2MHZ 0x00000004 /* SPI_Clock: 2MHz */
Vkadaba 6:9d393a9677f4 1175 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_1MHZ 0x00000006 /* SPI_Clock: 1MHz */
Vkadaba 6:9d393a9677f4 1176 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_500KHZ 0x00000008 /* SPI_Clock: 500kHz */
Vkadaba 6:9d393a9677f4 1177 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_250KHZ 0x0000000A /* SPI_Clock: 250kHz */
Vkadaba 6:9d393a9677f4 1178 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_125KHZ 0x0000000C /* SPI_Clock: 125kHz */
Vkadaba 6:9d393a9677f4 1179 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_62P5KHZ 0x0000000E /* SPI_Clock: 62.5kHz */
Vkadaba 6:9d393a9677f4 1180 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_31P3KHZ 0x00000010 /* SPI_Clock: 31.25kHz */
Vkadaba 6:9d393a9677f4 1181 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_15P6KHZ 0x00000012 /* SPI_Clock: 15.625kHz */
Vkadaba 6:9d393a9677f4 1182 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_7P8KHZ 0x00000014 /* SPI_Clock: 7.8kHz */
Vkadaba 6:9d393a9677f4 1183 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_3P9KHZ 0x00000016 /* SPI_Clock: 3.9kHz */
Vkadaba 6:9d393a9677f4 1184 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_1P9KHZ 0x00000018 /* SPI_Clock: 1.95kHz */
Vkadaba 8:2f2775c34640 1185 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_977HZ 0x0000001A /* SPI_Clock: 977Hz */
Vkadaba 6:9d393a9677f4 1186 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_488HZ 0x0000001C /* SPI_Clock: 488Hz */
Vkadaba 6:9d393a9677f4 1187 #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_244HZ 0x0000001E /* SPI_Clock: 244Hz */
Vkadaba 5:0728bde67bdb 1188
Vkadaba 5:0728bde67bdb 1189
Vkadaba 32:52445bef314d 1190 /* SPI Parameters */
Vkadaba 32:52445bef314d 1191
Vkadaba 32:52445bef314d 1192 /***** SPI */
Vkadaba 32:52445bef314d 1193 #define PARAM_SPI_SPI_STANDARD "LPT" /* A part must declare which SPI Standard it follows, either ADI or LPT */
Vkadaba 32:52445bef314d 1194 #define PARAM_SPI_CHIP_GRADE_VALUE 0 /* This is used to indicate speed grades/linearity. */
Vkadaba 32:52445bef314d 1195 #define PARAM_SPI_CHIP_REVISION_VALUE 0 /* This is used to indicate the silicon revision */
Vkadaba 32:52445bef314d 1196 #define PARAM_SPI_HAS_M_S_REGISTERS 0 /* If a design uses Master-Slave registers this must be set to true to enable relevant control bit fields */
Vkadaba 32:52445bef314d 1197 #define PARAM_SPI_M_S_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS the M-S Transfer bit field */
Vkadaba 32:52445bef314d 1198 #define PARAM_SPI_STREAM_MODE_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS of the stream mode transfer bit field */
Vkadaba 32:52445bef314d 1199 #define PARAM_SPI_MSB_AND_LSB_FIRST_SUPPORT 0 /* Determines if the parts supports MSB and LSB first options */
Vkadaba 32:52445bef314d 1200 #define PARAM_SPI_WIRE_MODE_SUPPORT "_4_WIRE" /* Configures which hardware SPI modes are supported */
Vkadaba 32:52445bef314d 1201 #define PARAM_SPI_WIRE_MODE_DEFAULT "_4_WIRE" /* Sets the default hardware SPI mode */
Vkadaba 32:52445bef314d 1202 #define PARAM_SPI_MULTI_IO_CHANNELS 1 /* Defines the number of SDIO pins supported by the SPI in Multi-IO Mode. Should be 1,2,4, or 8. */
Vkadaba 32:52445bef314d 1203 #define PARAM_SPI_LPT_STANDARD_VERSION "REV1_0" /* This is a string from the LPT_STANDARD_VERSION_OPTIONS array for the active LPT SPI Standard version */
Vkadaba 32:52445bef314d 1204 #define PARAM_SPI_HAS_CSB_PIN 1 /* Does the part have a csb pin? */
Vkadaba 32:52445bef314d 1205 #define PARAM_SPI_BUS_MODE_SUPPORT 1 /* When set to true, Bus mode is supported. */
Vkadaba 32:52445bef314d 1206 #define PARAM_SPI_ISOLATED_3_WIRE_SUPPORT 0 /* Does the part support the 3-wire isolate mode of operation */
Vkadaba 32:52445bef314d 1207 #define PARAM_SPI_DAISY_CHAIN_MODE_SUPPORT 0 /* When set to true, Daisy chain mode is supported. */
Vkadaba 32:52445bef314d 1208 #define PARAM_SPI_CHECK_GTE_1_MODE_SUPPORTED 1 /* This is used to check that at least mode is enabled */
Vkadaba 32:52445bef314d 1209 #define PARAM_SPI_INTERFACE_MODE_SWITCH "None" /* Valid options are 'None', 'HW' or 'SW' */
Vkadaba 32:52445bef314d 1210 #define PARAM_SPI_CRC_SUPPORT "CRC_CONFIGURABLE" /* Set to true to enable bit fields related to CRC. */
Vkadaba 32:52445bef314d 1211 #define PARAM_SPI_CRC_SUPPORT_ENABLED 0 /* Verilog output parameter for 'define */
Vkadaba 32:52445bef314d 1212 #define PARAM_SPI_CRC_SUPPORT_ENABLE 1 /* Configures if CRC features are enabled in the module */
Vkadaba 32:52445bef314d 1213 #define PARAM_SPI_LPT_STANDARD_VERSION_VALUE 2 /* Index value of the active LPT SPI Standard version */
Vkadaba 32:52445bef314d 1214 #define PARAM_SPI_ADDRESS_MODE_SUPPORT "_15_BIT" /* Configures which addressing modes are supported */
Vkadaba 32:52445bef314d 1215 #define PARAM_SPI_ADDRESS_MODE_DEFAULT "_15_BIT" /* Sets the default addressing mode */
Vkadaba 32:52445bef314d 1216 #define PARAM_SPI_ADDRESS_BUS_WIDTH 15 /* Verilog output parameter for 'define */
Vkadaba 32:52445bef314d 1217 #define PARAM_SPI_SLOW_IFACE_CTRL_SUPPORT 0 /* Does the part support the Slow Interface Control feature */
Vkadaba 32:52445bef314d 1218 #define PARAM_SPI_SOFT_RESET_0_BF_EXISTS 0 /* Used to control if the SOFT_RESET_0 bit field exists */
Vkadaba 32:52445bef314d 1219 #define PARAM_SPI_SOFT_RESET_1_BF_EXISTS 0 /* Used to control if the SOFT_RESET_1 bit field exists */
Vkadaba 32:52445bef314d 1220 #define PARAM_SPI_SEND_STATUS_SUPPORT "SEND_STATUS_CONFIGURABLE" /* Determines if and how the part supports the SEND_STATUS feature */
Vkadaba 32:52445bef314d 1221 #define PARAM_SPI_SEND_STATUS_SUPPORT_ENABLE 1 /* This is used to enable various send status features */
Vkadaba 32:52445bef314d 1222 #define PARAM_SPI_SPI_STANDARD_VERSION_VALUE 2 /* Value for SPI Standard VERSION bit field */
Vkadaba 32:52445bef314d 1223 #define PARAM_SPI_ENTITY_ACCESS_SUPPORT "ENTITY_ACCESS_ALWAYS" /* Configures which entity access mode(s) are supported */
Vkadaba 32:52445bef314d 1224 #define PARAM_SPI_ENTITY_ACCESS_SUPPORT_ENABLE 1 /* This is used to enable/disable Strict Entity Access features */
Vkadaba 32:52445bef314d 1225 #define PARAM_SPI_ENTITY_ACCESS_DEFAULT 1 /* Sets the default entity access mode */
Vkadaba 32:52445bef314d 1226 #define PARAM_SPI_CHIP_INDEX_EXISTS 0 /* Used to control if the CHIP_INDEX register and related bit field exists */
Vkadaba 32:52445bef314d 1227 #define PARAM_SPI_OFFSET_DEV_INDEX_EXISTS 0 /* Used to control if the OFFSET_DEV_INDEX bit field and registers exists */
Vkadaba 32:52445bef314d 1228 #define PARAM_SPI_DEV_INDEX_EXISTS 0 /* Used to control if the DEV_INDEX bit field and register exists */
Vkadaba 32:52445bef314d 1229 #define PARAM_SPI_STATUS_BIT_0_EXISTS 0 /* Sets EXIST for Status Bit 0 */
Vkadaba 32:52445bef314d 1230 #define PARAM_SPI_STATUS_BIT_1_EXISTS 0 /* Sets EXIST for Status Bit 1 */
Vkadaba 32:52445bef314d 1231 #define PARAM_SPI_STATUS_BIT_2_EXISTS 0 /* Sets EXIST for Status Bit 2 */
Vkadaba 32:52445bef314d 1232 #define PARAM_SPI_STATUS_BIT_3_EXISTS 0 /* Sets EXIST for Status Bit 3 */
Vkadaba 32:52445bef314d 1233 #define PARAM_SPI_STATUS_BIT_0_SWNAME "Status_Bit_0" /* Software Name for Status Bit 0 */
Vkadaba 32:52445bef314d 1234 #define PARAM_SPI_STATUS_BIT_1_SWNAME "Status_Bit_1" /* Software Name for Status Bit 1 */
Vkadaba 32:52445bef314d 1235 #define PARAM_SPI_STATUS_BIT_2_SWNAME "Status_Bit_2" /* Software Name for Status Bit 2 */
Vkadaba 32:52445bef314d 1236 #define PARAM_SPI_STATUS_BIT_3_SWNAME "Status_Bit_3" /* Software Name for Status Bit 3 */
Vkadaba 32:52445bef314d 1237 #define PARAM_SPI_CHIP_TYPE "P_ADC" /* This is a string that corresponds to one of the values in the CHIP_TYPE_OPTIONS array and corresponds to the type of chip being developed */
Vkadaba 32:52445bef314d 1238 #define PARAM_SPI_CHIP_TYPE_VALUE 7 /* Integer value corresponding to selected CHIP_TYPE, and is used as bit field enum value */
Vkadaba 32:52445bef314d 1239 #define PARAM_SPI_PRODUCT_ID_VALUE 32 /* This value is used to identify a specific generic. */
Vkadaba 32:52445bef314d 1240 #define PARAM_SPI_PRODUCT_ID_TRIM_BITS 4 /* This defines the number of PRODUCT_ID bits that can be fuse/trimmed. */
Vkadaba 32:52445bef314d 1241
Vkadaba 6:9d393a9677f4 1242 #endif /* end ifndef _DEF_ADMW1001_REGISTERS_H */