1 year, 6 months ago.

An unaligned access error has occurred.

Hello , I have downloaded Mbed os workspace(TBSense2_Sensor_Demo) for keil v5. build a workspace on IAR like keil (with little bit modification like setting a device), it builds error free successfully. But problem is that after flashing to board its going to hard fault.

Here is debug log - ################### Tue Jul 02, 2019 18:03:43: IAR Embedded Workbench 8.20.2 (C:\Program Files (x86)\IAR Systems\ Embedded Workbench 8.0\arm\bin\armproc.dll) Tue Jul 02, 2019 18:03:43: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\debugger\SiliconLaboratories\Trace_GECKO_S1.dmac Tue Jul 02, 2019 18:03:43: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\SiliconLaboratories\FlashGECKOS1.mac Tue Jul 02, 2019 18:03:43: JLINK command: ProjectFile = C:\Users\User\Documents\IAR Embedded Workbench\arm\TBSense2_Sensor_Demo_ver_5_os\settings\ TBSense2_Sensor_Demo_ver_5_os_TBSense2_Sensor_Demo_ver_5_os.jlink, return = 0 Tue Jul 02, 2019 18:03:43: Device "EFR32MG12PXXXF1024" selected. Tue Jul 02, 2019 18:03:43: JTAG speed is initially set to: 1000 kHz Tue Jul 02, 2019 18:03:43: TotalIRLen = 4, IRPrint = 0x01 Tue Jul 02, 2019 18:03:43: JTAG chain detection found 1 devices: Tue Jul 02, 2019 18:03:43: #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP Tue Jul 02, 2019 18:03:43: TotalIRLen = 4, IRPrint = 0x01 Tue Jul 02, 2019 18:03:43: JTAG chain detection found 1 devices: Tue Jul 02, 2019 18:03:43: #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP Tue Jul 02, 2019 18:03:43: Scanning AP map to find all available APs Tue Jul 02, 2019 18:03:43: AP[1]: Stopped AP scan as end of AP map has been reached Tue Jul 02, 2019 18:03:43: AP[0]: AHB-AP (IDR: 0x24770011) Tue Jul 02, 2019 18:03:43: Iterating through AP map to find AHB-AP to use Tue Jul 02, 2019 18:03:43: AP[0]: Core found Tue Jul 02, 2019 18:03:43: AP[0]: AHB-AP ROM base: 0xE00FF000 Tue Jul 02, 2019 18:03:43: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM) Tue Jul 02, 2019 18:03:43: Found Cortex-M4 r0p1, Little endian. Tue Jul 02, 2019 18:03:43: FPUnit: 6 code (BP) slots and 2 literal slots Tue Jul 02, 2019 18:03:43: CoreSight components: Tue Jul 02, 2019 18:03:43: ROMTbl[0] @ E00FF000 Tue Jul 02, 2019 18:03:43: ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7 Tue Jul 02, 2019 18:03:43: ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT Tue Jul 02, 2019 18:03:43: ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB Tue Jul 02, 2019 18:03:43: ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM Tue Jul 02, 2019 18:03:43: ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite Tue Jul 02, 2019 18:03:43: ROMTbl[0][5]: E0041000, CID: B105900D, PID: 000BB925 ETM Tue Jul 02, 2019 18:03:43: Reset: Halt core after reset via DEMCR.VC_CORERESET. Tue Jul 02, 2019 18:03:43: Reset: Reset device via AIRCR.SYSRESETREQ. Tue Jul 02, 2019 18:03:43: Hardware reset with strategy 0 was performed Tue Jul 02, 2019 18:03:43: Initial reset was performed Tue Jul 02, 2019 18:03:43: Found 1 JTAG device, Total IRLen = 4: Tue Jul 02, 2019 18:03:43: #0 Id: 0x4BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP Tue Jul 02, 2019 18:03:44: Setting up GECKOS1 flash Tue Jul 02, 2019 18:03:44: 1024 bytes downloaded (4.00 Kbytes/sec) Tue Jul 02, 2019 18:03:44: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\SiliconLaboratories\FlashGECKOS1.out Tue Jul 02, 2019 18:03:44: Target reset Tue Jul 02, 2019 18:03:45: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\SiliconLaboratories\FlashGECKOS1.mac Tue Jul 02, 2019 18:03:45: Downloaded C:\Users\User\Documents\IAR Embedded Workbench\arm\ TBSense2_Sensor_Demo_ver_5_os\Debug\Exe\template_project.out to flash memory. Tue Jul 02, 2019 18:03:45: Reset: Halt core after reset via DEMCR.VC_CORERESET. Tue Jul 02, 2019 18:03:45: Reset: Reset device via AIRCR.SYSRESETREQ. Tue Jul 02, 2019 18:03:45: Hardware reset with strategy 0 was performed Tue Jul 02, 2019 18:03:48: 42706 bytes downloaded into FLASH (9.57 Kbytes/sec) Tue Jul 02, 2019 18:03:48: Loaded debugee: C:\Users\User\Documents\IAR Embedded Workbench\ arm\TBSense2_Sensor_Demo_ver_5_os\Debug\Exe\template_project.out Tue Jul 02, 2019 18:03:48: Reset: Halt core after reset via DEMCR.VC_CORERESET. Tue Jul 02, 2019 18:03:48: Reset: Reset device via AIRCR.SYSRESETREQ. Tue Jul 02, 2019 18:03:48: Hardware reset with strategy 0 was performed Tue Jul 02, 2019 18:03:48: Target reset Tue Jul 02, 2019 18:04:55: Ignored debugger specified MTB address. (Connected core never implements an MTB) Tue Jul 02, 2019 18:04:55: Breakpoint hit: Code @ mbed_boot.c:620.3, type: default (auto) Tue Jul 02, 2019 18:05:01: Breakpoint hit: Code @ irq_cm4f.s:95.1, type: default (auto) Tue Jul 02, 2019 18:05:18: Breakpoint hit: Code @ irq_cm4f.s:102.1, type: default (auto) Tue Jul 02, 2019 18:05:23: HardFault exception. Tue Jul 02, 2019 18:05:23: The processor has escalated a configurable-priority exception to HardFault. Tue Jul 02, 2019 18:05:23: An unaligned access error has occurred. Tue Jul 02, 2019 18:05:23: Tue Jul 02, 2019 18:05:23: Exception occured at: 0x99a6 Tue Jul 02, 2019 18:05:23: Tue Jul 02, 2019 18:05:23: See the call stack for more information. ###################

After little bit debugging , what i got is from arrow mentioned line, It goes in hard fault before main function -

from file Irq_cm4f.s>line no.92

SVC_ContextRestore

LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information

LDR R0,[R2,#TCB_SP_OFS] ; Load SP

ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN

TST LR,#0x10 ; Check if extended stack frame

IT EQ

VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31

LDMIA R0!,{R4-R11} ; Restore R4..R11 <<<<<<<----From here--

MSR PSP,R0

Extra Info :- Mbed os version

  1. define MBED_MAJOR_VERSION 5
  2. define MBED_MINOR_VERSION 6
  3. define MBED_PATCH_VERSION 3

IAR version- IAR Embedded Workbench 8.20.2

I didn't get ,why I'm facing such problem.How to resolve it. Any help appreciated.

Thanks

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