3 years, 3 months ago.

how to find vector number of STM32L462CEU6 in order to set NVIC_NUM_VECTOR in cmsis_nvic.h

Hi, I am adding the STM32L462CEU6 as a new target, since there is no current target based on L462CEU6 i wonder how to find the actual vector number for this MCU, i cannot find any reference to this count on STM HAL files, an idea anyone?

Here is the definition for an existing target (STM32L432), the file name is cmsis_nvic.h

#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H

// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187
// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
#define NVIC_NUM_VECTORS        98
#define NVIC_RAM_VECTOR_ADDRESS SRAM1_BASE    // Vectors positioned at start of SRAM1

#endif

1 Answer

3 years, 3 months ago.

Hello Hoel,

I have searched the STM documentation for an aswer, but I was no able to find an unambiguos solution.

  • The STM32F3 Series, STM32F4 Series, STM32L4 Series and STM32L4+ Series Cortex®-M4 programming manual on page 207, in chapter "4.3 Nested vectored interrupt controller (NVIC)", is talking about up to 81 interrups with advice to consult the the particular MCU's datasheet for more deatails. However, on page 38, in chapter "2.3.3 Exception handlers", it says that ISR of IRQ0 to IRQ81 are handling the exceptions. So there appear to be 82 (not 81) interrupts. It isn't clear whether one should add the 16 Cortex®-M4 interrupts to get the total number of interrupts = 82 + 16 = 98.
  • The STM32L462CE datasheet then on page 37, in chapter "3.14.1 Nested vectored interrupt controller (NVIC)", explains that the devices embed a nested vectored interrupt controller which is able to manage 16 priority levels and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4. This gives 83 interrupts in total.

Despite precious SRAM on embedded systems and the total number of interrupts indicated in the *The STM32L462CE datasheet is only 83, I would recommend to make the maximum room for interrupt vectors wich seems to be 98. (There wouldn't harm to reserve even a few more.)

Best regards,

Zoltan

Accepted Answer

Thank you Zoltan, The datasheet is indeed ambiguous, other L46x targets use 98 so i kept 98, it works fine.

posted by BIDAULT Hoel 15 Mar 2018