Mohamed Saleh

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8 years, 3 months ago.

Problem with cmsis_nvic.c

Hello,

I hope someone answer me this time, I asked before about "if I could enabling systick for OS as OS-clock" because the problem was that software jumps to "Hard Fault Handler" . So I tried to enable General Purpose timer instead, The problem still persist. So I followed the code by debugger and here's what I found:

(I am porting mbed to Tiva C TM4C123 launchpad, my compiler is GCC, I am using CDT for building, And GDB openOCD for debugging, and integrated all those tools on Eclipse)

it jumps to hard fault handler handler at line 

vectors[i] = old_vectors[i];

here's code which I use

#include "cmsis_nvic.h"

#define NVIC_RAM_VECTOR_ADDRESS (0x02000000)  // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash

void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
    uint32_t *vectors = (uint32_t*)SCB->VTOR;
    uint32_t i;

    // Copy and switch to dynamic vectors if the first time called
    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
        uint32_t *old_vectors = vectors;
        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
        for (i=0; i<NVIC_NUM_VECTORS; i++) {
            vectors[i] = old_vectors[i];
        }
        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
    }
    vectors[IRQn + 16] = vector;
}

uint32_t NVIC_GetVector(IRQn_Type IRQn) {
    uint32_t *vectors = (uint32_t*)SCB->VTOR;
    return vectors[IRQn + 16];
}

I have configures cmsis_nvic.h to 

#define NVIC_NUM_VECTORS      (10 + 66)   // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET  16

Can anyone please let me know what is going wrong here? or at least where should I debug or read ???

1 Answer

Erik -
8 years, 3 months ago.

In general: Either step through it with a debugger, or otherwise disable stuff until it does not crash anymore.

Specifically here, from the reference manual I get:

Quote:

The internal SRAM of the TM4C123GH6PM device is located at address 0x2000.0000 of the device memory map.

That is not what you have set the start of your SRAM to.

Accepted Answer
posted by Mohamed Saleh 29 Jul 2016