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7 years, 9 months ago.
PLL locking on 32.768Khz clock taking More Time in LPC1768
Hi,
Am working on LPC1768 with CPU clock freq:100MHZ. 1)We are using 2 clocks for PLL a)Ext clock(19.2Mhz) b)RTC clock (32.&68Khz)
With external clk it is locking in few seconds.
But when I use 32.768khz it is taking more time about 15-20 seconds PLL locking. In my application I need to switch PLL on both the clock depends on situation. Am using this code SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ SC->PLL0CFG = PLL0CFG_Val; SC->PLL0CON = 0x01; /* PLL0 Enable */ SC->PLL0FEED = 0xAA; SC->PLL0FEED = 0x55; for(lu32_Delay = 0;lu32_Delay < 0x1ff;lu32_Delay++); while (!(SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ SC->PLL0FEED = 0xAA; SC->PLL0FEED = 0x55; Please Help me urgently.
That it takes alot longer to lock with a 32.768kHz reference makes perfect sense: A PLL updates its oscillator frequency every period of the (divided) reference. There are alot fewer of those at 32.768kHz, so it takes longer to lock.
But while not familiar with the normal lock time of this PLL, this seems like really long.
posted by Erik - 13 Jul 2016