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4 years, 2 months ago.
Not a question, but some observations are noted here to inform others.
The X-NUCLEO-PLC01A1 board's VN8200XP (output stage, solid state relay) is configured in hardware with its watchdog timer enabled (WD_EN tied to 0.5*VREG). Every 80ms the watchdog timer must be reset, or the outputs will be disabled.
This can be observed in the HelloWorld_PLC01A1 example by increasing the main loop's wait_ms() delay from 10 to 1000 - the ouput mirror LEDs will be seen to pulse rather than staying illuminated to match the corresponding input. Change the delay back to 10ms & the outputs are steady, mirroring input signals.
The VNI8200XP's WD reset pin on this board is wired to the CLT01-38SQ7 input chip's CS, so to keep the outputs "alive" we must read the input frequently, or directly pulse that CS low with the provided function plc.plcInput().setInputSPI(0); followed by plc.plcInput().setInputSPI(1); to avoid the outputs being reset.