4 years ago.

Cutting the PCB causes clock issues


I seem to be having some issues.

Once cutting the ST Nucleo board my board still works using the jumper wires for programming however due to it not using the clock signal provided by the ST Link chip it seems to not run at the correct clock speed and locks up.

When running the output clock speed command it results as 96Mhz.

How do I fix and set it up to use the internal PLL for the clock?

Thanks - Ryan Walmsley

Question relating to:

Affordable and flexible platform to ease prototyping using a STM32F070RBT6 microcontroller.

1 Answer

4 years ago.

It seems to me that there is an error in the mbed library for F070RB.
I tested the clock for HSI and PLL using CubeMX for settings what are in the mbed.
I also goes 96MHz for settings what are in the mbed. So wrong.

I suggest use mbed-dev instead mbed library and change source file.

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/ system_stm32f0xx.c
SetSysClock_PLL_HSI (line431)

Now is:

  // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;

Comments suggest that HSI is divided by 2. And because the PLL is x12. But there is no divide by two, since it is RCC_PREDIV_DIV1. And there's no other divider before PLL.

I suggest to change:

RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;


RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL6;



RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;


RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV2;

Accepted Answer

Thanks for that. I'll try that in the morning and see if it works!

posted by Ryan Walmsley 12 Mar 2016


Can you give a bit of information on how to use mbed-dev instead?

posted by Ryan Walmsley 13 Mar 2016

Aha figured it out and all working :)

posted by Ryan Walmsley 13 Mar 2016

This bug is probably due to copy and paste from F030 to F070 device. The reference manual (see here) shows that the F030 has a div2 in the connection between the HSI and the PLL. That divider is missing in the F070. See fig10 and Fig11 on pages 90/91 in the reference manual. The F070 does have a pre-divider just before the PLL, which is different from the F030.

posted by Wim Huiskamp 13 Mar 2016