5 years, 7 months ago.

WIZwiki-W7500 SystemCoreClock at 20MHz instead of 48MHz

A quick first test with the new WIZwiki-W7500 platform shows that the clockfrequency is 20MHz, which is less than half the advertised value of 48MHz. Turns out that this is due to the fact that the PLL freq calculation register is not initialised and uses its reset value of 0x050200 instead. That means the PLL config values are: M=5, N=2, OD=1. So the SystemCoreClock = 8MHz * M / N * 1 / OD = 20 MHz

This bug should be fixed in the W7500 mbed source code, probably in system_W7500x.c, for example by adding:

CRG->PLL_FCR = 0x060100;      

I also noted that the internal Xtal (8MHz) is used instead of the (mounted) external Xtal (8 MHz). Any reason for that?

The code below provides the current settings:

#include "mbed.h"
 
Serial pc(USBTX, USBRX); // tx, rx

DigitalOut red(LED_RED);        // PC_8
DigitalOut green(LED_GREEN);    // PC_9
DigitalOut blue(LED_BLUE);      // PC_5
 
uint8_t M,N,OD;
int main() {
  pc.printf("Hello World from W7500!\n\r");
  pc.printf("CPU SystemCoreClock is %d Hz\r\n", SystemCoreClock);   

#ifdef SYSCLK_EXTERN_OSC
  pc.printf("SYSCLK_EXTERN_OSC = 1; EXTERN_XTAL = %d\n\r", EXTERN_XTAL);
#else  
  pc.printf("SYSCLK_EXTERN_OSC = 0; INTERN_XTAL = %d\n\r", INTERN_XTAL);
#endif      
 
  pc.printf("CRG->PLL_FCR = 0x%0X\n\r", CRG->PLL_FCR);  

  OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1));
   N = (CRG->PLL_FCR >>  8 ) & 0x3F;
   M = (CRG->PLL_FCR >> 16) & 0x3F;
   pc.printf("M = %d; N = %d; OD = %d\n\r", M, N, OD);  
   
  red = 1;  
  green = 1;  
  blue = 1;      
  
  while(1) {
    red = !red;
    wait(0.5);
    pc.putc('#'); 
  }
}

Question relating to:

WIZwiki-W7500 is a SoC platform board based on the W7500 chip = ARM Cortex-M0 that integrates 128KB Flash and hardwired TCP/IP core. If you use WIZwiki-W7500 board, you can easily …

5 Answers

5 years, 1 month ago.

Has this been fixed?

EDIT: issues reported on GitHub. (#1237)

And I'll answer myself: not fixed. CPU SystemCoreClock is 20000000 Hz

posted by Lorenzo De Rossi 01 Feb 2016

Oh common!

posted by Vladimir Akopyan 15 Feb 2016
5 years ago.

PLease, can you report this to github, and I'll tag reponsible ppl for wiznet port to have a look.

Thanks

Martin, I did raise this on github last year. See https://github.com/mbedmicro/mbed/issues/1237#issuecomment-120842504

Comment by hjjeon0608 was (3 Jul 2015) We set core clock as 20MHz on purpose not bug. Do I change the core clock to maximum frequency(48MHz)??

We mounted external Xtal for user to test. We think it is enough to use internal Xtal. And do I change also???

posted by Wim Huiskamp 03 Feb 2016
5 years ago.

Also waiting for this to happen

There is a discussion on github, please have a look https://github.com/mbedmicro/mbed/issues/1524

posted by Vladimir Akopyan 06 Mar 2016
4 years, 10 months ago.

Hello, it would be very nice to use 48MHz, because it affects WIZwiki 7500 and 7500P. When will you change this in the library? Would be awesome, thank you.

2 years, 7 months ago.

Has there been any progress on this issue?