9 years, 9 months ago.

Reading data bits on transceiver

I am doing an internship at a company and i am working on an embedded systems project named "ZigBee based internet of things"

I need to establish data communication between a microcontroller and a transceiver through SPI.

I have been successful in writing the code for transmitting the data out serially through SPI from the microcontroller to the transceiver (which I checked by connecting the SO, SCLK and SEN (chip select) pin to the oscilloscope) by initializing the respective registers and writing data to them, which is the WRITE operation.

The next part for me is to check whether the data being sent out is being received by the transceiver or not, which is to do the READ operation now according to the SPI timing diagram which I have attached in this mail by the name of SPI timing diagram, in which I am facing some problem. I need to send the address from which I need to read the data along with some dummy data. During the time the dummy data is being sent out, the original data is retrieved from the respective address. I have included the code which I used for writing to the registers and for transmitting the data out in main.c, UBEC_Init.c and UBEC_Init.h. I would really appreciate if you could guide me for the READ operation

Following is the code for WRITE operation:

MAIN.C

1. include "ZIGBEE_UBEC_INIT.h"

uint16_t addr; uint16_t data;

int main(void) {

addr=0x1234; data=0x5678;

USIC0_CH1->TCSR |= USIC_CH_TCSR_FLEMD_Msk; USIC0_CH1->RBCTR |= USIC_CH_RBCTR_FLEMD_Msk;

UzInit();

while(1) { write_SREG (addr, data); write_LREG (addr, data); read_SREG (addr); read_LREG (addr); }

return 0; }

****************

UBEC_INIT.C

1. include "ZIGBEE_UBEC_INIT.h"

bool TX;

void UzInit() { SOFTRST+0x07; Software Reset write_SREG (SOFTRST,0x07); SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

read_SREG (SOFTRST); BBREG2+0x80; Set CCA mode to ED write_SREG (BBREG2, 0x80); SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_SREG (BBREG6,0x40); value=BBREG6+ 0x40; Append RSSI value in Rx packets SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_SREG (RSSIHCCA,0x60);

write_SREG (SLPACK,0x5F); value=SLPACK+ 0x5F; 20MHz clock recovery time SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_LREG (RFCTL,0x02); read_LREG (RFCTL); value=RFCTL+0x02; RF channel setting SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD); value= 0x02; SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_LREG (RFCTL2,0x80); value=RFCTL2; RF optimized control SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD); value= 0x80; SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_LREG (RFCTL6,0x90); value=RFCTL6; RF optimized control SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD); value= 0x90; SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_LREG (RFCTL7,0x80); value=RFCTL7; RF optimized control SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD); value= 0x80; SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_LREG (RFCTL8,0x10); value=RFCTL7; RF optimized control SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD); value= 0x80; SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_LREG (SCLKDIV,0x01); value=SCLKDIV; RF optimized control SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD); value= 0x01; SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_LREG (RFCTL3, 0x40);

write_LREG (TESTMODE, 0x0F);

write_SREG (INTMSK,0x00); value=INTMSK+(0x32<<8); Enable all interrupt SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_SREG (RFSTATE,0x04); value=RFSTATE+ 0x04; RF Machine Reset SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_SREG (RFSTATE,0x00); value=RFSTATE+ 0x00; RF set to normal operation SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

write_SREG (RXMAC,0x03); value=RXMAC+ 0x03; Receive all MAC Packets SPI001_WriteData (&SPI001_Handle0, &value, SPI001_STANDARD);

}

void write_SREG (uint16_t addr, uint16_t data) { uint16_t value; value=(addr<<8)+(data & 0x00FF); USIC0_CH1->TBUF[15] = value; while(USIC0_CH1->TCSR & USIC_CH_TCSR_TDV_Msk); }

void write_LREG (uint16_t addr, uint16_t data) {

USIC0_CH1->TBUF[23]= addr; while(USIC0_CH1->TCSR & USIC_CH_TCSR_TDV_Msk);

USIC0_CH1->TBUF[23]= data<<8; while(USIC0_CH1->TCSR & USIC_CH_TCSR_TDV_Msk); }

uint8_t read_SREG (uint16_t addr) { uint16_t value; write_SREG (SOFTRST,0x1234); USIC0_CH1->RBUF[7] = value; return value;

}

uint8_t read_LREG (uint16_t addr) { uint16_t value;

USIC0_CH1->RBUF[7] = value; return value; }

************************

UBEC_INIT.H

1. ifndef ZIGBEE_UBEC_INIT_H_
2. define ZIGBEE_UBEC_INIT_H_

1. define SOFTRST 0x2A
2. define BBREG2 0x3A
3. define RSSIHCCA 0x3F
4. define BBREG6 0x3E
5. define INTMSK 0x32
6. define SLPACK 0x35
7. define RFSTATE 0x36
8. define RXMAC 0x00
9. define RFCTL 0x200
10. define RFCTL2 0x202
11. define RFCTL6 0x206
12. define RFCTL7 0x207
13. define RFCTL8 0x208
14. define RFCTL3 0x203
15. define SCLKDIV 0x220
16. define TESTMODE 0x22F

void write_SREG(uint16_t val1, uint16_t val2); void write_LREG(uint16_t val1, uint16_t val2);

uint8_t read_SREG(uint16_t addr); uint8_t read_LREG(uint16_t addr);

1. endif /* ZIGBEE_UBEC_INIT_H_ */