#include "mbed.h"

// DMA MUX Sources (partial list) - cannot find these defines elsewhere in mbed
#define DMA_MUX_SRC_SPI0_Receive (16)
#define DMA_MUX_SRC_SPI0_Transmit (17)
#define DMA_MUX_SRC_SPI1_Receive (18)
#define DMA_MUX_SRC_SPI1_Transmit (19)
#define DMA_MUX_SRC_I2C0 (22)
#define DMA_MUX_SRC_I2C1 (23)
#define DMA_MUX_SRC_TPM0_Channel_0 (24)
#define DMA_MUX_SRC_TPM0_Channel_1 (25)
#define DMA_MUX_SRC_TPM0_Channel_2 (26)
#define DMA_MUX_SRC_TPM0_Channel_3 (27)
#define DMA_MUX_SRC_TPM0_Channel_4 (28)
#define DMA_MUX_SRC_TPM0_Channel_5 (29)
#define DMA_MUX_SRC_TPM1_Channel_0 (32)
#define DMA_MUX_SRC_TPM1_Channel_1 (33)
#define DMA_MUX_SRC_TPM2_Channel_0 (34)
#define DMA_MUX_SRC_TPM2_Channel_1 (35)
#define DMA_MUX_SRC_ADC0 (40)
#define DMA_MUX_SRC_CMP0 (42)
#define DMA_MUX_SRC_DAC0 (45)

/**
 * Run a DMA Test using SPI0.  Attempts to read and write a fixed number of bytes, to/from provided buffers.
 *
 * @param dmaReadCh The DMA channel to configure for the SPI READ operation.
 * @param dmaWriteCh The DMA channel to configure for the SPI WRITE operation.
 * @param srcBuffer Data buffer of values to write out to SPI
 * @param destBuffer Data buffer in which to store values read from the SPI
 * @param length The length of both buffers
 */
void dma_test(const int dmaReadCh, const int dmaWriteCh, char *srcBuffer, char *destBuffer, int length) {
    //Enable DMA clocking
    SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK;    // Enable clock to DMA mux
    SIM->SCGC7 |= SIM_SCGC7_DMA_MASK;       // Enable clock to DMA

    // reset DMAMUX
    DMAMUX0->CHCFG[dmaReadCh] = 0;
    DMAMUX0->CHCFG[dmaWriteCh] = 0;

    DMA0->DMA[dmaReadCh].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
    DMA0->DMA[dmaWriteCh].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
//to be continued...

    // Set up one of the DMA channels to read from SPI0, and link to the other DMA channel to trigger the next write
    DMA0->DMA[dmaReadCh].SAR = (uint32_t)&(SPI0->D);// set source address: SPI0_Data register
    DMA0->DMA[dmaReadCh].DAR = (unsigned int)destBuffer; // set dest address: memory buffer
    DMA0->DMA[dmaReadCh].DSR_BCR |= DMA_DSR_BCR_BCR_MASK & length; // length of transfer
    DMA0->DMA[dmaReadCh].DCR = DMA_DCR_EINT_MASK | DMA_DCR_ERQ_MASK | DMA_DCR_CS_MASK | /*DMA_DCR_EADREQ_MASK | DMA_DCR_SINC_MASK | */
        DMA_DCR_SSIZE(0x01) | DMA_DCR_DINC_MASK | DMA_DCR_DSIZE(0x01) | DMA_DCR_START_MASK | DMA_DCR_D_REQ_MASK |
        DMA_DCR_LINKCC(0x10) | DMA_DCR_LCH1(dmaWriteCh);
        // 8-bit transfers, link to DMA1, etc

    // Set up another DMA channel to write to the SPI, in order to force Reads, and link to above
    DMA0->DMA[dmaWriteCh].SAR = (unsigned int)srcBuffer;// set source address: dummy memory buffer for writes
    DMA0->DMA[dmaWriteCh].DAR = (uint32_t)&(SPI0->D); // set dest address: SPI0_Data register
    DMA0->DMA[dmaWriteCh].DSR_BCR |= DMA_DSR_BCR_BCR_MASK & length; // length of transfer
    DMA0->DMA[dmaWriteCh].DCR = DMA_DCR_EINT_MASK | DMA_DCR_ERQ_MASK | DMA_DCR_CS_MASK | /*DMA_DCR_EADREQ_MASK | */ DMA_DCR_SINC_MASK |
        DMA_DCR_SSIZE(0x01) | /*DMA_DCR_DINC_MASK |*/ DMA_DCR_DSIZE(0x01) | DMA_DCR_START_MASK | DMA_DCR_D_REQ_MASK |
        DMA_DCR_LINKCC(0x10) | DMA_DCR_LCH1(dmaReadCh);
        // 8-bit transfers, link to DMA0, etc

    // Configure DMAMUX0
    DMAMUX0->CHCFG[dmaReadCh] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_TRIG_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_SPI0_Receive);
    DMAMUX0->CHCFG[dmaWriteCh] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_TRIG_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_SPI0_Transmit);
 
    // Enable DMA features within the SPI registers   
    SPI0->C1 |= SPI_C1_SPIE_MASK | SPI_C1_SPE_MASK | SPI_C1_SPTIE_MASK;
    SPI0->C2 |= SPI_C2_TXDMAE_MASK | SPI_C2_RXDMAE_MASK;
}