Reading over the watchdog timer section of the UM for the LPC17xx family it states - "Once the WDEN and/or WDRESET bits are set they can not be cleared by software. Both flags are cleared by an external reset or a Watchdog timer underflow. [page 568 - CH28 section 4.1]".  Since instructions are not executed during Sleep - how do you feed / kick / service the watchdog?  I thought that by using the PCLK this would be an issue since the PCLK should not be running during Sleep, consequently not decrementing the counter but this is not the case. "Watchdog reset or interrupt will occur any time the watchdog is running and has an operating clock source. Any clock source works in Sleep mode, and the IRC works in Deep Sleep mode. If a watchdog interrupt occurs in Sleep or Deep Sleep mode, it will wake up the device. [page 585 CH28 section 4.1]". 

My question is how do you sleep and not reset due to a watchdog timer timeout?  Will the ISR continuously fire during sleep?  Does this mean that the PLL0 will connect and reconnect every WDT timeout?

Any and all help is appreciated, Thanks!

Sam