EDIT: title should be driving an N-channel FET in a high side configuration.

I have already ordered some FETs and the 'correct' driver for the application (the LTC1155), however, I was curious as to what is technically wrong with driving an N-channel FET in a highside application as follows:

- connecting mbed pin to a driver such as the ULN2803 (darlington low side driver), with a pull up resistor. - connecting gate of FET between pull up resistor and low side driver. - 12V supply to the darlington driver - when off, the pull up resistor holds the gate voltage to 12V rail, so FET Vgs is 0 - when on, the darlington array holds the gate voltage to 0V rail, so FET Vgs is 1.9V (assuming .18 Rds and a 1ohm load, 12V 12A, for example with - http://www.fairchildsemi.com/ds/MT/MTP3055VL.pdf

Or... are my assumptions incorrect?!

Some years ago I saw a series of FET drive circuits in a "Design Ideas" section, I think it was EDN. In essence the simplest circuit used a logic level P-FET, but the goal was to use a regular N-FET. The circuit was intended to be "micropower", meaning pull-up resistors weren't suitable.

In the logic level P-FET case the enable signal simply needed inverting. +ve meant off, -ve on. They added a charge pump to develop a negative supply. An analog switch was then used to level-shift the signal to drive the gate negative.

The final circuit used a charge pump with external diodes to produce a positive rail more positive than the supply. This allowed the use of a N-type FET, to turn it on the gate is driven more positive than the supply. To turn it off the gate is switched to ground.

If you have a suitable positive supply you could use pull-up resistor to turn the FET on, and an open collector or open drain could turn it off.

The advantage of a device like the LTC is it contains the charge-pump, level shifters and an overload protection circuit. Trying to do all of that in discretes would take a bit of space.