## Oscillator question (out of specs??)

08 Apr 2011

Hi I’m confused and hope someone can help me out. Reading the data sheet (section 14.2) it describes two ways to clock the LPC1768. 1) Slave mode and 2) Oscillation mode. Looking at the MBED schematics mbed-005.1, the oscillator is not shown, but because there is a cap in series with pin 22 it makes me believe that they are using Slave mode. Well If that is the case I don't see the second cap (Cg on Fig 33) to attenuate the clock. Actually I used the scope and I get 3V pk. Which according to the data sheet that is it too much. The max should be 1.95 Vpk (Table 7) or 1.0 Vrms (page 68) Anyone out there using the slave mode?. Do you use Cg?

Jaime

08 Apr 2011

You raise an interesting point.

Since the input pin is driven from a 3.3V oscillator module, it looks like Cg should be at least 135pF. Then Vpk = 3.3V * 100pf/(100pf + 135pf) = 1.4V , which gives the desired 1.0 Vrms.

I guess the LPC1768 doesn't mind a little overdrive :-)

10 Apr 2011

In fact, my reading of the data sheet spec. for an external clock signal is that the several values given are ambiguous or slightly in conflict. I am forced to assume (yes, I used that word :-)) that the Pk and RMS values refer to an AC-coupled measurments of the of the signal. For such cases a sine wave of 1.4 V Pk would be 2.8 V Pk-to-Pk, and 1.0 V RMS. A square wave of 1.0 V RMS would be 1.0 V Pk and 2.0 V Pk-to-Pk. For the mbed, with a 12Mhz square-wave oscillator driving through a 100 pf capacitor, Cg should be 65 pf (or more) to limit the mbed pin to 1.0 V RMS.

It would probably be prudent to consider that adding (a non-zero) Cg will probably change the load seen by the oscillator's output from some fairly high impedance with a limited (stray) capacitance component to a load which is significantly capacitive. For Cg of 65 pf at 12Mhz through 100 pf, that load would have an impedance magnitude around 337 ohms. A conservative approach might be to connect the 12 MHZ oscillator's 3.3 V Pk-to-Pk output through the 100 pf coupling capacitor, then in series with a 1 k-ohm resistor and a 1.5 K-ohm resistor, then through another 100 pf capacitor to ground. The mbed clock-input pin would be connected to the junction of the two resistors.

The most likely disadvantages of slightly over-driving the mbed input are that it would activate currents through protective or parasitic diodes, or that the extra amplitude will drive extra current through the input’s capacitance to the power and ground rails (possibly causing corresponding voltage spikes). These would also add to the load on the oscillator’s output, and/or the oscillator’s current draw, and possibly to the mbed’s current draw.

With a properly limited edge slew-rate (to limit the capacative current spikes' magnatudes) there is little reason why a 3.3 V Pk-to-Pk square wave should not be used. Still, anyone want to hack-in the C-R+R-C network I just described (to see if it really works, helps with the ADC spikes, etc.)?

A possibly better network might be the 100 pf coupling capacitor to a 1.5 K-ohm resistor and then a 30 pf Cg to ground (with the mbed input tied to the un-grounded end of Cg). This would produce a roughly trapazoidal waveform, with limits on both the RMS value and the edge slew rates.

10 Apr 2011

The data sheet is so confusing that I thought some empirical measurements might be helpful.

The first question is, "What is the internal bias voltage at the XTAL1 input?". This is the center point around which the clock signal will swing after it passes through the 100pF coupling capacitor.

A scope showed the signal at XTAL1 swinging from about -0.4V to +2.4V. So it appears that the internal bias level is at the midpoint, or +1.0V.

The second question is, "How large an input signal can be allowed, given a 1.0V midpoint?"

The input level spec for the clock, Vi(XTAL1) is -0.8V minimum, +1.95V maximum. (Table 7, page 46). So the allowable input swing is 1.8V below the bias point, or 0.95V above the bias point.

For a signal that swings equally on both sides of the midpoint, the limit is given by the smaller of the two values above. So the maximum allowable input signal swing is +/- 0.95V, or 1.9Vpp. This equates to 950mV rms for an AC-coupled square wave; not so far off from the "1000mv (RMS)" maximum given on page 67 of the data sheet.

It looks like the mbed is being over driven a bit, with a +2.4V peak input. Since that is less than the supply voltage (3.3V), hopefully no protective diodes are being energized. Still, the overdrive can't be a Good Thing...

BTW, I suppose this overdrive is also present at the magic "mbed" chip, as it is also said to be in the ARM family.

11 Apr 2011

I agree, if following the specs it seems that the LPC1768 is being over-driven. It would be nice if the MBED designers would comment on that. Also, I have not found another circuit on the web using an oscillator with this micro. As a matter of fact this is the first time I see this configuration (Ci & Cg on Fig 33) when using oscillators. But I’m sure someone has the answer.