Mbed OS Reference | sx1272Regs-LoRa.h Source File

 /**
  / _____)             _              | |
 ( (____  _____ ____ _| |_ _____  ____| |__
  \____ \| ___ |    (_   _) ___ |/ ___)  _ \
  _____) ) ____| | | || |_| ____( (___| | | |
 (______/|_____)_|_|_| \__)_____)\____)_| |_|
     (C) 2015 Semtech
 
 Description: SX1272 LoRa modem registers and bits definitions
 
 License: Revised BSD License, see LICENSE.TXT file include in the project
 
 Maintainer: Miguel Luis and Gregory Cristian
 
 Copyright (c) 2017, Arm Limited and affiliates.
 
 SPDX-License-Identifier: BSD-3-Clause
 */
 #ifndef __SX1272_REGS_LORA_H__
 #define __SX1272_REGS_LORA_H__
 
 /*!
  * ============================================================================
  * SX1272 Internal registers Address
  * ============================================================================
  */
 #define REG_LR_FIFO                                 0x00
 // Common settings
 #define REG_LR_OPMODE                               0x01
 #define REG_LR_FRFMSB                               0x06
 #define REG_LR_FRFMID                               0x07
 #define REG_LR_FRFLSB                               0x08
 // Tx settings
 #define REG_LR_PACONFIG                             0x09
 #define REG_LR_PARAMP                               0x0A
 #define REG_LR_OCP                                  0x0B
 // Rx settings
 #define REG_LR_LNA                                  0x0C
 // LoRa registers
 #define REG_LR_FIFOADDRPTR                          0x0D
 #define REG_LR_FIFOTXBASEADDR                       0x0E
 #define REG_LR_FIFORXBASEADDR                       0x0F
 #define REG_LR_FIFORXCURRENTADDR                    0x10
 #define REG_LR_IRQFLAGSMASK                         0x11
 #define REG_LR_IRQFLAGS                             0x12
 #define REG_LR_RXNBBYTES                            0x13
 #define REG_LR_RXHEADERCNTVALUEMSB                  0x14
 #define REG_LR_RXHEADERCNTVALUELSB                  0x15
 #define REG_LR_RXPACKETCNTVALUEMSB                  0x16
 #define REG_LR_RXPACKETCNTVALUELSB                  0x17
 #define REG_LR_MODEMSTAT                            0x18
 #define REG_LR_PKTSNRVALUE                          0x19
 #define REG_LR_PKTRSSIVALUE                         0x1A
 #define REG_LR_RSSIVALUE                            0x1B
 #define REG_LR_HOPCHANNEL                           0x1C
 #define REG_LR_MODEMCONFIG1                         0x1D
 #define REG_LR_MODEMCONFIG2                         0x1E
 #define REG_LR_SYMBTIMEOUTLSB                       0x1F
 #define REG_LR_PREAMBLEMSB                          0x20
 #define REG_LR_PREAMBLELSB                          0x21
 #define REG_LR_PAYLOADLENGTH                        0x22
 #define REG_LR_PAYLOADMAXLENGTH                     0x23
 #define REG_LR_HOPPERIOD                            0x24
 #define REG_LR_FIFORXBYTEADDR                       0x25
 #define REG_LR_FEIMSB                               0x28
 #define REG_LR_FEIMID                               0x29
 #define REG_LR_FEILSB                               0x2A
 #define REG_LR_RSSIWIDEBAND                         0x2C
 #define REG_LR_DETECTOPTIMIZE                       0x31
 #define REG_LR_INVERTIQ                             0x33
 #define REG_LR_DETECTIONTHRESHOLD                   0x37
 #define REG_LR_SYNCWORD                             0x39
 #define REG_LR_INVERTIQ2                            0x3B
 
 // end of documented register in datasheet
 // I/O settings
 #define REG_LR_DIOMAPPING1                          0x40
 #define REG_LR_DIOMAPPING2                          0x41
 // Version
 #define REG_LR_VERSION                              0x42
 // Additional settings
 #define REG_LR_AGCREF                               0x43
 #define REG_LR_AGCTHRESH1                           0x44
 #define REG_LR_AGCTHRESH2                           0x45
 #define REG_LR_AGCTHRESH3                           0x46
 #define REG_LR_PLLHOP                               0x4B
 #define REG_LR_TCXO                                 0x58
 #define REG_LR_PADAC                                0x5A
 #define REG_LR_PLL                                  0x5C
 #define REG_LR_PLLLOWPN                             0x5E
 #define REG_LR_FORMERTEMP                           0x6C
 
 /*!
  * ============================================================================
  * SX1272 LoRa bits control definition
  * ============================================================================
  */
 
 /*!
  * RegFifo
  */
 
 /*!
  * RegOpMode
  */
 #define RFLR_OPMODE_LONGRANGEMODE_MASK              0x7F
 #define RFLR_OPMODE_LONGRANGEMODE_OFF               0x00 // Default
 #define RFLR_OPMODE_LONGRANGEMODE_ON                0x80
 
 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK            0xBF
 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE          0x40
 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE         0x00 // Default
 
 #define RFLR_OPMODE_MASK                            0xF8
 #define RFLR_OPMODE_SLEEP                           0x00
 #define RFLR_OPMODE_STANDBY                         0x01 // Default
 #define RFLR_OPMODE_SYNTHESIZER_TX                  0x02
 #define RFLR_OPMODE_TRANSMITTER                     0x03
 #define RFLR_OPMODE_SYNTHESIZER_RX                  0x04
 #define RFLR_OPMODE_RECEIVER                        0x05
 // LoRa specific modes
 #define RFLR_OPMODE_RECEIVER_SINGLE                 0x06
 #define RFLR_OPMODE_CAD                             0x07
 
 /*!
  * RegFrf (MHz)
  */
 #define RFLR_FRFMSB_915_MHZ                         0xE4  // Default
 #define RFLR_FRFMID_915_MHZ                         0xC0  // Default
 #define RFLR_FRFLSB_915_MHZ                         0x00  // Default
 
 /*!
  * RegPaConfig
  */
 #define RFLR_PACONFIG_PASELECT_MASK                 0x7F
 #define RFLR_PACONFIG_PASELECT_PABOOST              0x80
 #define RFLR_PACONFIG_PASELECT_RFO                  0x00 // Default
 
 #define RFLR_PACONFIG_OUTPUTPOWER_MASK              0xF0
 
 /*!
  * RegPaRamp
  */
 #define RFLR_PARAMP_LOWPNTXPLL_MASK                 0xE0
 #define RFLR_PARAMP_LOWPNTXPLL_OFF                  0x10 // Default
 #define RFLR_PARAMP_LOWPNTXPLL_ON                   0x00
 
 #define RFLR_PARAMP_MASK                            0xF0
 #define RFLR_PARAMP_3400_US                         0x00
 #define RFLR_PARAMP_2000_US                         0x01
 #define RFLR_PARAMP_1000_US                         0x02
 #define RFLR_PARAMP_0500_US                         0x03
 #define RFLR_PARAMP_0250_US                         0x04
 #define RFLR_PARAMP_0125_US                         0x05
 #define RFLR_PARAMP_0100_US                         0x06
 #define RFLR_PARAMP_0062_US                         0x07
 #define RFLR_PARAMP_0050_US                         0x08
 #define RFLR_PARAMP_0040_US                         0x09 // Default
 #define RFLR_PARAMP_0031_US                         0x0A
 #define RFLR_PARAMP_0025_US                         0x0B
 #define RFLR_PARAMP_0020_US                         0x0C
 #define RFLR_PARAMP_0015_US                         0x0D
 #define RFLR_PARAMP_0012_US                         0x0E
 #define RFLR_PARAMP_0010_US                         0x0F
 
 /*!
  * RegOcp
  */
 #define RFLR_OCP_MASK                               0xDF
 #define RFLR_OCP_ON                                 0x20 // Default
 #define RFLR_OCP_OFF                                0x00
 
 #define RFLR_OCP_TRIM_MASK                          0xE0
 #define RFLR_OCP_TRIM_045_MA                        0x00
 #define RFLR_OCP_TRIM_050_MA                        0x01
 #define RFLR_OCP_TRIM_055_MA                        0x02
 #define RFLR_OCP_TRIM_060_MA                        0x03
 #define RFLR_OCP_TRIM_065_MA                        0x04
 #define RFLR_OCP_TRIM_070_MA                        0x05
 #define RFLR_OCP_TRIM_075_MA                        0x06
 #define RFLR_OCP_TRIM_080_MA                        0x07
 #define RFLR_OCP_TRIM_085_MA                        0x08
 #define RFLR_OCP_TRIM_090_MA                        0x09
 #define RFLR_OCP_TRIM_095_MA                        0x0A
 #define RFLR_OCP_TRIM_100_MA                        0x0B  // Default
 #define RFLR_OCP_TRIM_105_MA                        0x0C
 #define RFLR_OCP_TRIM_110_MA                        0x0D
 #define RFLR_OCP_TRIM_115_MA                        0x0E
 #define RFLR_OCP_TRIM_120_MA                        0x0F
 #define RFLR_OCP_TRIM_130_MA                        0x10
 #define RFLR_OCP_TRIM_140_MA                        0x11
 #define RFLR_OCP_TRIM_150_MA                        0x12
 #define RFLR_OCP_TRIM_160_MA                        0x13
 #define RFLR_OCP_TRIM_170_MA                        0x14
 #define RFLR_OCP_TRIM_180_MA                        0x15
 #define RFLR_OCP_TRIM_190_MA                        0x16
 #define RFLR_OCP_TRIM_200_MA                        0x17
 #define RFLR_OCP_TRIM_210_MA                        0x18
 #define RFLR_OCP_TRIM_220_MA                        0x19
 #define RFLR_OCP_TRIM_230_MA                        0x1A
 #define RFLR_OCP_TRIM_240_MA                        0x1B
 
 /*!
  * RegLna
  */
 #define RFLR_LNA_GAIN_MASK                          0x1F
 #define RFLR_LNA_GAIN_G1                            0x20 // Default
 #define RFLR_LNA_GAIN_G2                            0x40
 #define RFLR_LNA_GAIN_G3                            0x60
 #define RFLR_LNA_GAIN_G4                            0x80
 #define RFLR_LNA_GAIN_G5                            0xA0
 #define RFLR_LNA_GAIN_G6                            0xC0
 
 #define RFLR_LNA_BOOST_MASK                         0xFC
 #define RFLR_LNA_BOOST_OFF                          0x00 // Default
 #define RFLR_LNA_BOOST_ON                           0x03
 
 /*!
  * RegFifoAddrPtr
  */
 #define RFLR_FIFOADDRPTR                            0x00 // Default
 
 /*!
  * RegFifoTxBaseAddr
  */
 #define RFLR_FIFOTXBASEADDR                         0x80 // Default
 
 /*!
  * RegFifoTxBaseAddr
  */
 #define RFLR_FIFORXBASEADDR                         0x00 // Default
 
 /*!
  * RegFifoRxCurrentAddr (Read Only)
  */
 
 /*!
  * RegIrqFlagsMask
  */
 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK                0x80
 #define RFLR_IRQFLAGS_RXDONE_MASK                   0x40
 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK          0x20
 #define RFLR_IRQFLAGS_VALIDHEADER_MASK              0x10
 #define RFLR_IRQFLAGS_TXDONE_MASK                   0x08
 #define RFLR_IRQFLAGS_CADDONE_MASK                  0x04
 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK       0x02
 #define RFLR_IRQFLAGS_CADDETECTED_MASK              0x01
 
 /*!
  * RegIrqFlags
  */
 #define RFLR_IRQFLAGS_RXTIMEOUT                     0x80
 #define RFLR_IRQFLAGS_RXDONE                        0x40
 #define RFLR_IRQFLAGS_PAYLOADCRCERROR               0x20
 #define RFLR_IRQFLAGS_VALIDHEADER                   0x10
 #define RFLR_IRQFLAGS_TXDONE                        0x08
 #define RFLR_IRQFLAGS_CADDONE                       0x04
 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL            0x02
 #define RFLR_IRQFLAGS_CADDETECTED                   0x01
 
 /*!
  * RegFifoRxNbBytes (Read Only)
  */
 
 /*!
  * RegRxHeaderCntValueMsb (Read Only)
  */
 
 /*!
  * RegRxHeaderCntValueLsb (Read Only)
  */
 
 /*!
  * RegRxPacketCntValueMsb (Read Only)
  */
 
 /*!
  * RegRxPacketCntValueLsb (Read Only)
  */
 
 /*!
  * RegModemStat (Read Only)
  */
 #define RFLR_MODEMSTAT_RX_CR_MASK                   0x1F
 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK            0xE0
 
 /*!
  * RegPktSnrValue (Read Only)
  */
 
 /*!
  * RegPktRssiValue (Read Only)
  */
 
 /*!
  * RegRssiValue (Read Only)
  */
 
 /*!
  * RegHopChannel (Read Only)
  */
 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK       0x7F
 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL               0x80
 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED            0x00 // Default
 
 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK           0xBF
 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON             0x40
 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF            0x00 // Default
 
 #define RFLR_HOPCHANNEL_CHANNEL_MASK                0x3F
 
 /*!
  * RegModemConfig1
  */
 #define RFLR_MODEMCONFIG1_BW_MASK                   0x3F
 #define RFLR_MODEMCONFIG1_BW_125_KHZ                0x00 // Default
 #define RFLR_MODEMCONFIG1_BW_250_KHZ                0x40
 #define RFLR_MODEMCONFIG1_BW_500_KHZ                0x80
 
 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK           0xC7
 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5            0x08
 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6            0x10 // Default
 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7            0x18
 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8            0x20
 
 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK       0xFB
 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON         0x04
 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF        0x00 // Default
 
 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK         0xFD
 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON           0x02
 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF          0x00 // Default
 
 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK  0xFE
 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON    0x01
 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF   0x00 // Default
 
 /*!
  * RegModemConfig2
  */
 #define RFLR_MODEMCONFIG2_SF_MASK                   0x0F
 #define RFLR_MODEMCONFIG2_SF_6                      0x60
 #define RFLR_MODEMCONFIG2_SF_7                      0x70 // Default
 #define RFLR_MODEMCONFIG2_SF_8                      0x80
 #define RFLR_MODEMCONFIG2_SF_9                      0x90
 #define RFLR_MODEMCONFIG2_SF_10                     0xA0
 #define RFLR_MODEMCONFIG2_SF_11                     0xB0
 #define RFLR_MODEMCONFIG2_SF_12                     0xC0
 
 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK     0xF7
 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON       0x08
 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF      0x00
 
 #define RFLR_MODEMCONFIG2_AGCAUTO_MASK              0xFB
 #define RFLR_MODEMCONFIG2_AGCAUTO_ON                0x04 // Default
 #define RFLR_MODEMCONFIG2_AGCAUTO_OFF               0x00
 
 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK       0xFC
 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB            0x00 // Default
 
 /*!
  * RegSymbTimeoutLsb
  */
 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT             0x64 // Default
 
 /*!
  * RegPreambleLengthMsb
  */
 #define RFLR_PREAMBLELENGTHMSB                      0x00 // Default
 
 /*!
  * RegPreambleLengthLsb
  */
 #define RFLR_PREAMBLELENGTHLSB                      0x08 // Default
 
 /*!
  * RegPayloadLength
  */
 #define RFLR_PAYLOADLENGTH                          0x0E // Default
 
 /*!
  * RegPayloadMaxLength
  */
 #define RFLR_PAYLOADMAXLENGTH                       0xFF // Default
 
 /*!
  * RegHopPeriod
  */
 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD            0x00 // Default
 
 /*!
  * RegFifoRxByteAddr (Read Only)
  */
 
 /*!
  * RegFeiMsb (Read Only)
  */
 
 /*!
  * RegFeiMid (Read Only)
  */
 
 /*!
  * RegFeiLsb (Read Only)
  */
 
 /*!
  * RegRssiWideband (Read Only)
  */
 
 /*!
  * RegDetectOptimize
  */
 #define RFLR_DETECTIONOPTIMIZE_MASK                 0xF8
 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12          0x03 // Default
 #define RFLR_DETECTIONOPTIMIZE_SF6                  0x05
 
 /*!
  * RegInvertIQ
  */
 #define RFLR_INVERTIQ_RX_MASK                       0xBF
 #define RFLR_INVERTIQ_RX_OFF                        0x00
 #define RFLR_INVERTIQ_RX_ON                         0x40
 #define RFLR_INVERTIQ_TX_MASK                       0xFE
 #define RFLR_INVERTIQ_TX_OFF                        0x01
 #define RFLR_INVERTIQ_TX_ON                         0x00
 
 /*!
  * RegDetectionThreshold
  */
 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12            0x0A // Default
 #define RFLR_DETECTIONTHRESH_SF6                    0x0C
 
 /*!
  * RegInvertIQ2
  */
 #define RFLR_INVERTIQ2_ON                           0x19
 #define RFLR_INVERTIQ2_OFF                          0x1D
 
 /*!
  * RegDioMapping1
  */
 #define RFLR_DIOMAPPING1_DIO0_MASK                  0x3F
 #define RFLR_DIOMAPPING1_DIO0_00                    0x00  // Default
 #define RFLR_DIOMAPPING1_DIO0_01                    0x40
 #define RFLR_DIOMAPPING1_DIO0_10                    0x80
 #define RFLR_DIOMAPPING1_DIO0_11                    0xC0
 
 #define RFLR_DIOMAPPING1_DIO1_MASK                  0xCF
 #define RFLR_DIOMAPPING1_DIO1_00                    0x00  // Default
 #define RFLR_DIOMAPPING1_DIO1_01                    0x10
 #define RFLR_DIOMAPPING1_DIO1_10                    0x20
 #define RFLR_DIOMAPPING1_DIO1_11                    0x30
 
 #define RFLR_DIOMAPPING1_DIO2_MASK                  0xF3
 #define RFLR_DIOMAPPING1_DIO2_00                    0x00  // Default
 #define RFLR_DIOMAPPING1_DIO2_01                    0x04
 #define RFLR_DIOMAPPING1_DIO2_10                    0x08
 #define RFLR_DIOMAPPING1_DIO2_11                    0x0C
 
 #define RFLR_DIOMAPPING1_DIO3_MASK                  0xFC
 #define RFLR_DIOMAPPING1_DIO3_00                    0x00  // Default
 #define RFLR_DIOMAPPING1_DIO3_01                    0x01
 #define RFLR_DIOMAPPING1_DIO3_10                    0x02
 #define RFLR_DIOMAPPING1_DIO3_11                    0x03
 
 /*!
  * RegDioMapping2
  */
 #define RFLR_DIOMAPPING2_DIO4_MASK                  0x3F
 #define RFLR_DIOMAPPING2_DIO4_00                    0x00  // Default
 #define RFLR_DIOMAPPING2_DIO4_01                    0x40
 #define RFLR_DIOMAPPING2_DIO4_10                    0x80
 #define RFLR_DIOMAPPING2_DIO4_11                    0xC0
 
 #define RFLR_DIOMAPPING2_DIO5_MASK                  0xCF
 #define RFLR_DIOMAPPING2_DIO5_00                    0x00  // Default
 #define RFLR_DIOMAPPING2_DIO5_01                    0x10
 #define RFLR_DIOMAPPING2_DIO5_10                    0x20
 #define RFLR_DIOMAPPING2_DIO5_11                    0x30
 
 #define RFLR_DIOMAPPING2_MAP_MASK                   0xFE
 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT         0x01
 #define RFLR_DIOMAPPING2_MAP_RSSI                   0x00  // Default
 
 /*!
  * RegVersion (Read Only)
  */
 
 /*!
  * RegAgcRef
  */
 
 /*!
  * RegAgcThresh1
  */
 
 /*!
  * RegAgcThresh2
  */
 
 /*!
  * RegAgcThresh3
  */
 
 /*!
  * RegPllHop
  */
 #define RFLR_PLLHOP_FASTHOP_MASK                    0x7F
 #define RFLR_PLLHOP_FASTHOP_ON                      0x80
 #define RFLR_PLLHOP_FASTHOP_OFF                     0x00 // Default
 
 /*!
  * RegTcxo
  */
 #define RFLR_TCXO_TCXOINPUT_MASK                    0xEF
 #define RFLR_TCXO_TCXOINPUT_ON                      0x10
 #define RFLR_TCXO_TCXOINPUT_OFF                     0x00  // Default
 
 /*!
  * RegPaDac
  */
 #define RFLR_PADAC_20DBM_MASK                       0xF8
 #define RFLR_PADAC_20DBM_ON                         0x07
 #define RFLR_PADAC_20DBM_OFF                        0x04  // Default
 
 /*!
  * RegPll
  */
 #define RFLR_PLL_BANDWIDTH_MASK                     0x3F
 #define RFLR_PLL_BANDWIDTH_75                       0x00
 #define RFLR_PLL_BANDWIDTH_150                      0x40
 #define RFLR_PLL_BANDWIDTH_225                      0x80
 #define RFLR_PLL_BANDWIDTH_300                      0xC0  // Default
 
 /*!
  * RegPllLowPn
  */
 #define RFLR_PLLLOWPN_BANDWIDTH_MASK                0x3F
 #define RFLR_PLLLOWPN_BANDWIDTH_75                  0x00
 #define RFLR_PLLLOWPN_BANDWIDTH_150                 0x40
 #define RFLR_PLLLOWPN_BANDWIDTH_225                 0x80
 #define RFLR_PLLLOWPN_BANDWIDTH_300                 0xC0  // Default
 
 /*!
  * RegFormerTemp
  */
 
 #endif // __SX1272_REGS_LORA_H__
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