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sl_eth_phy.h
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1 /***************************************************************************//**
2  * @file sl_eth_phy.h
3  *******************************************************************************
4  * @section License
5  * <b>(C) Copyright 2017 Silicon Labs, http://www.silabs.com</b>
6  *******************************************************************************
7  *
8  * SPDX-License-Identifier: Apache-2.0
9  *
10  * Licensed under the Apache License, Version 2.0 (the "License"); you may
11  * not use this file except in compliance with the License.
12  * You may obtain a copy of the License at
13  *
14  * http://www.apache.org/licenses/LICENSE-2.0
15  *
16  * Unless required by applicable law or agreed to in writing, software
17  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
18  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
19  * See the License for the specific language governing permissions and
20  * limitations under the License.
21  *
22  ******************************************************************************/
23 #ifndef __SL_ETH_PHY_H__
24 #define __SL_ETH_PHY_H__
25 
26 #define PHY_BMCR 0x00u /* Basic mode control reg. */
27 #define PHY_BMSR 0x01u /* Basic mode status reg. */
28 #define PHY_PHYSID1 0x02u /* PHYS ID 1 reg. */
29 #define PHY_PHYSID2 0x03u /* PHYS ID 2 reg. */
30 #define PHY_ANAR 0x04u /* Advertisement control reg. */
31 #define PHY_ANLPAR 0x05u /* Link partner ability reg. */
32 #define PHY_ANER 0x06u /* Expansion reg. */
33 #define PHY_ANNPTR 0x07u /* Next page transmit reg. */
34 
35 /* -------------- PHY_BMCR REGISTER BITS -------------- */
36 #define BMCR_CTST (0x1 << 7) /* Collision test. */
37 #define BMCR_FULLDPLX (0x1 << 8) /* Full duplex. */
38 #define BMCR_ANRESTART (0x1 << 9) /* Auto negotiation restart. */
39 #define BMCR_ISOLATE (0x1 << 10) /* Disconnect Phy from MII. */
40 #define BMCR_PDOWN (0x1 << 11) /* Power down. */
41 #define BMCR_ANENABLE (0x1 << 12) /* Enable auto negotiation. */
42 #define BMCR_SPEED100 (0x1 << 13) /* Select 100Mbps. */
43 #define BMCR_LOOPBACK (0x1 << 14) /* TXD loopback bits. */
44 #define BMCR_RESET (0x1 << 15) /* Reset. */
45 
46 /* -------------- PHY_BMSR REGISTER BITS -------------- */
47 #define BMSR_ERCAP (0x1 << 0) /* Ext-reg capability. */
48 #define BMSR_JCD (0x1 << 1) /* Jabber detected. */
49 #define BMSR_LSTATUS (0x1 << 2) /* Link status. */
50 #define BMSR_ANEGCAPABLE (0x1 << 3) /* Able to do auto-negotiation. */
51 #define BMSR_RFAULT (0x1 << 4) /* Remote fault detected. */
52 #define BMSR_ANEGCOMPLETE (0x1 << 5) /* Auto-negotiation complete. */
53 #define BMSR_10HALF (0x1 << 11) /* Can do 10mbps, half-duplex. */
54 #define BMSR_10FULL (0x1 << 12) /* Can do 10mbps, full-duplex. */
55 #define BMSR_100HALF (0x1 << 13) /* Can do 100mbps, half-duplex. */
56 #define BMSR_100FULL (0x1 << 14) /* Can do 100mbps, full-duplex. */
57 #define BMSR_100BASE4 (0x1 << 15) /* Can do 100mbps, 4k packets. */
58 
59 /* -------------- PHY_ANAR REGISTER BITS -------------- */
60 #define ANAR_SLCT 0x001Fu /* Selector bits. */
61 #define ANAR_CSMA DEF_BIT_04 /* Only selector supported. */
62 #define ANAR_10HALF DEF_BIT_05 /* Try for 10mbps half-duplex. */
63 #define ANAR_10FULL DEF_BIT_06 /* Try for 10mbps full-duplex. */
64 #define ANAR_100HALF DEF_BIT_07 /* Try for 100mbps half-duplex. */
65 #define ANAR_100FULL DEF_BIT_08 /* Try for 100mbps full-duplex. */
66 #define ANAR_100BASE4 DEF_BIT_09 /* Try for 100mbps 4k packets. */
67 #define ANAR_RFAULT DEF_BIT_13 /* Say we can detect faults. */
68 #define ANAR_LPACK DEF_BIT_14 /* Ack link partners response. */
69 #define ANAR_NPAGE DEF_BIT_15 /* Next page bit. */
70 
71 #define ANAR_FULL (ANAR_100FULL | ANAR_10FULL | ANAR_CSMA)
72 #define ANAR_ALL (ANAR_100BASE4 | ANAR_100FULL | ANAR_10FULL | ANAR_100HALF | ANAR_10HALF)
73 
74 /* ------------- PHY_ANLPAR REGISTER BITS ------------- */
75 #define ANLPAR_10HALF (0x1 << 5) /* Can do 10mbps half-duplex. */
76 #define ANLPAR_10FULL (0x1 << 6) /* Can do 10mbps full-duplex. */
77 #define ANLPAR_100HALF (0x1 << 7) /* Can do 100mbps half-duplex. */
78 #define ANLPAR_100FULL (0x1 << 8) /* Can do 100mbps full-duplex. */
79 #define ANLPAR_100BASE4 (0x1 << 9) /* Can do 100mbps 4k packets. */
80 #define ANLPAR_RFAULT (0x1 << 13) /* Link partner faulted. */
81 #define ANLPAR_LPACK (0x1 << 14) /* Link partner acked us. */
82 #define ANLPAR_NPAGE (0x1 << 15) /* Next page bit. */
83 
84 #define ANLPAR_DUPLEX (ANLPAR_10FULL | ANLPAR_100FULL)
85 #define ANLPAR_100 (ANLPAR_100FULL | ANLPAR_100HALF | ANLPAR_100BASE4)
86 
87 /* -------------- PHY_ANER REGISTER BITS -------------- */
88 #define ANER_NWAY (0x1 << 0) /* Can do N-way auto-negotiation. */
89 #define ANER_LCWP (0x1 << 1) /* Got new RX page code word. */
90 #define ANER_ENABLENPAGE (0x1 << 2) /* This enables npage words. */
91 #define ANER_NPCAPABLE (0x1 << 3) /* Link partner supports npage. */
92 #define ANER_MFAULTS (0x1 << 4) /* Multiple faults detected. */
93 
94 #endif
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