Macros | |
| #define | EMAC_NUM_RX_FRAG 4 |
| Num.of RX Fragments 4*1536= 6.0kB. More... | |
| #define | EMAC_NUM_TX_FRAG 3 |
| Num.of TX Fragments 3*1536= 4.6kB. More... | |
| #define | EMAC_ETH_MAX_FLEN 1536 |
| Max. More... | |
| #define | EMAC_TX_FRAME_TOUT 0x00100000 |
| Frame Transmit timeout count. More... | |
| #define | EMAC_MAC1_REC_EN 0x00000001 |
| Macro defines for MAC Configuration Register 1. More... | |
| #define | EMAC_MAC1_PASS_ALL 0x00000002 |
| Pass All Receive Frames. More... | |
| #define | EMAC_MAC1_RX_FLOWC 0x00000004 |
| RX Flow Control. More... | |
| #define | EMAC_MAC1_TX_FLOWC 0x00000008 |
| TX Flow Control. More... | |
| #define | EMAC_MAC1_LOOPB 0x00000010 |
| Loop Back Mode. More... | |
| #define | EMAC_MAC1_RES_TX 0x00000100 |
| Reset TX Logic. More... | |
| #define | EMAC_MAC1_RES_MCS_TX 0x00000200 |
| Reset MAC TX Control Sublayer. More... | |
| #define | EMAC_MAC1_RES_RX 0x00000400 |
| Reset RX Logic. More... | |
| #define | EMAC_MAC1_RES_MCS_RX 0x00000800 |
| Reset MAC RX Control Sublayer. More... | |
| #define | EMAC_MAC1_SIM_RES 0x00004000 |
| Simulation Reset. More... | |
| #define | EMAC_MAC1_SOFT_RES 0x00008000 |
| Soft Reset MAC. More... | |
| #define | EMAC_MAC2_FULL_DUP 0x00000001 |
| Macro defines for MAC Configuration Register 2. More... | |
| #define | EMAC_MAC2_FRM_LEN_CHK 0x00000002 |
| Frame Length Checking. More... | |
| #define | EMAC_MAC2_HUGE_FRM_EN 0x00000004 |
| Huge Frame Enable. More... | |
| #define | EMAC_MAC2_DLY_CRC 0x00000008 |
| Delayed CRC Mode. More... | |
| #define | EMAC_MAC2_CRC_EN 0x00000010 |
| Append CRC to every Frame. More... | |
| #define | EMAC_MAC2_PAD_EN 0x00000020 |
| Pad all Short Frames. More... | |
| #define | EMAC_MAC2_VLAN_PAD_EN 0x00000040 |
| VLAN Pad Enable. More... | |
| #define | EMAC_MAC2_ADET_PAD_EN 0x00000080 |
| Auto Detect Pad Enable. More... | |
| #define | EMAC_MAC2_PPREAM_ENF 0x00000100 |
| Pure Preamble Enforcement. More... | |
| #define | EMAC_MAC2_LPREAM_ENF 0x00000200 |
| Long Preamble Enforcement. More... | |
| #define | EMAC_MAC2_NO_BACKOFF 0x00001000 |
| No Backoff Algorithm. More... | |
| #define | EMAC_MAC2_BACK_PRESSURE 0x00002000 |
| Backoff Presurre / No Backoff. More... | |
| #define | EMAC_MAC2_EXCESS_DEF 0x00004000 |
| Excess Defer. More... | |
| #define | EMAC_IPGT_BBIPG(n) (n&0x7F) |
| Macro defines for Back-to-Back Inter-Packet-Gap Register. More... | |
| #define | EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15)) |
| Recommended value for Full Duplex of Programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. More... | |
| #define | EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12)) |
| Recommended value for Half Duplex of Programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. More... | |
| #define | EMAC_IPGR_NBBIPG_P2(n) (n&0x7F) |
| Macro defines for Non Back-to-Back Inter-Packet-Gap Register. More... | |
| #define | EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12)) |
| Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1. More... | |
| #define | EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8) |
| Programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. More... | |
| #define | EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C) |
| Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2. More... | |
| #define | EMAC_CLRT_MAX_RETX(n) (n&0x0F) |
| Macro defines for Collision Window/Retry Register. More... | |
| #define | EMAC_CLRT_COLL(n) ((n&0x3F)<<8) |
| Programmable field representing the slot time or collision window during which collisions occur in properly configured networks. More... | |
| #define | EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37))) |
| Default value for Collision Window / Retry register. More... | |
| #define | EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF) |
| Macro defines for Maximum Frame Register. More... | |
| #define | EMAC_SUPP_SPEED 0x00000100 |
| Macro defines for PHY Support Register. More... | |
| #define | EMAC_SUPP_RES_RMII 0x00000800 |
| Reset Reduced MII Logic. More... | |
| #define | EMAC_TEST_SHCUT_PQUANTA 0x00000001 |
| Macro defines for Test Register. More... | |
| #define | EMAC_TEST_TST_PAUSE 0x00000002 |
| Test Pause. More... | |
| #define | EMAC_TEST_TST_BACKP 0x00000004 |
| Test Back Pressure. More... | |
| #define | EMAC_MCFG_SCAN_INC 0x00000001 |
| Macro defines for MII Management Configuration Register. More... | |
| #define | EMAC_MCFG_SUPP_PREAM 0x00000002 |
| Suppress Preamble. More... | |
| #define | EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) |
| Clock Select Field. More... | |
| #define | EMAC_MCFG_RES_MII 0x00008000 |
| Reset MII Management Hardware. More... | |
| #define | EMAC_MCFG_MII_MAXCLK 2500000UL |
| MII Clock max. More... | |
| #define | EMAC_MCMD_READ 0x00000001 |
| Macro defines for MII Management Command Register. More... | |
| #define | EMAC_MCMD_SCAN 0x00000002 |
| MII Scan continuously. More... | |
| #define | EMAC_MII_WR_TOUT 0x00050000 |
| MII Write timeout count. More... | |
| #define | EMAC_MII_RD_TOUT 0x00050000 |
| MII Read timeout count. More... | |
| #define | EMAC_MADR_REG_ADR(n) (n&0x1F) |
| Macro defines for MII Management Address Register. More... | |
| #define | EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) |
| PHY Address Field. More... | |
| #define | EMAC_MWTD_DATA(n) (n&0xFFFF) |
| Macro defines for MII Management Write Data Register. More... | |
| #define | EMAC_MRDD_DATA(n) (n&0xFFFF) |
| Macro defines for MII Management Read Data Register. More... | |
| #define | EMAC_MIND_BUSY 0x00000001 |
| Macro defines for MII Management Indicators Register. More... | |
| #define | EMAC_MIND_SCAN 0x00000002 |
| MII Scanning in Progress. More... | |
| #define | EMAC_MIND_NOT_VAL 0x00000004 |
| MII Read Data not valid. More... | |
| #define | EMAC_MIND_MII_LINK_FAIL 0x00000008 |
| MII Link Failed. More... | |
| #define | EMAC_CR_RX_EN 0x00000001 |
| Macro defines for Command Register. More... | |
| #define | EMAC_CR_TX_EN 0x00000002 |
| Enable Transmit. More... | |
| #define | EMAC_CR_REG_RES 0x00000008 |
| Reset Host Registers. More... | |
| #define | EMAC_CR_TX_RES 0x00000010 |
| Reset Transmit Datapath. More... | |
| #define | EMAC_CR_RX_RES 0x00000020 |
| Reset Receive Datapath. More... | |
| #define | EMAC_CR_PASS_RUNT_FRM 0x00000040 |
| Pass Runt Frames. More... | |
| #define | EMAC_CR_PASS_RX_FILT 0x00000080 |
| Pass RX Filter. More... | |
| #define | EMAC_CR_TX_FLOW_CTRL 0x00000100 |
| TX Flow Control. More... | |
| #define | EMAC_CR_RMII 0x00000200 |
| Reduced MII Interface. More... | |
| #define | EMAC_CR_FULL_DUP 0x00000400 |
| Full Duplex. More... | |
| #define | EMAC_SR_RX_EN 0x00000001 |
| Macro defines for Status Register. More... | |
| #define | EMAC_SR_TX_EN 0x00000002 |
| Enable Transmit. More... | |
| #define | EMAC_TSV0_CRC_ERR 0x00000001 |
| Macro defines for Transmit Status Vector 0 Register. More... | |
| #define | EMAC_TSV0_LEN_CHKERR 0x00000002 |
| Length Check Error. More... | |
| #define | EMAC_TSV0_LEN_OUTRNG 0x00000004 |
| Length Out of Range. More... | |
| #define | EMAC_TSV0_DONE 0x00000008 |
| Tramsmission Completed. More... | |
| #define | EMAC_TSV0_MCAST 0x00000010 |
| Multicast Destination. More... | |
| #define | EMAC_TSV0_BCAST 0x00000020 |
| Broadcast Destination. More... | |
| #define | EMAC_TSV0_PKT_DEFER 0x00000040 |
| Packet Deferred. More... | |
| #define | EMAC_TSV0_EXC_DEFER 0x00000080 |
| Excessive Packet Deferral. More... | |
| #define | EMAC_TSV0_EXC_COLL 0x00000100 |
| Excessive Collision. More... | |
| #define | EMAC_TSV0_LATE_COLL 0x00000200 |
| Late Collision Occured. More... | |
| #define | EMAC_TSV0_GIANT 0x00000400 |
| Giant Frame. More... | |
| #define | EMAC_TSV0_UNDERRUN 0x00000800 |
| Buffer Underrun. More... | |
| #define | EMAC_TSV0_BYTES 0x0FFFF000 |
| Total Bytes Transferred. More... | |
| #define | EMAC_TSV0_CTRL_FRAME 0x10000000 |
| Control Frame. More... | |
| #define | EMAC_TSV0_PAUSE 0x20000000 |
| Pause Frame. More... | |
| #define | EMAC_TSV0_BACK_PRESS 0x40000000 |
| Backpressure Method Applied. More... | |
| #define | EMAC_TSV0_VLAN 0x80000000 |
| VLAN Frame. More... | |
| #define | EMAC_TSV1_BYTE_CNT 0x0000FFFF |
| Macro defines for Transmit Status Vector 1 Register. More... | |
| #define | EMAC_TSV1_COLL_CNT 0x000F0000 |
| Transmit Collision Count. More... | |
| #define | EMAC_RSV_BYTE_CNT 0x0000FFFF |
| Macro defines for Receive Status Vector Register. More... | |
| #define | EMAC_RSV_PKT_IGNORED 0x00010000 |
| Packet Previously Ignored. More... | |
| #define | EMAC_RSV_RXDV_SEEN 0x00020000 |
| RXDV Event Previously Seen. More... | |
| #define | EMAC_RSV_CARR_SEEN 0x00040000 |
| Carrier Event Previously Seen. More... | |
| #define | EMAC_RSV_REC_CODEV 0x00080000 |
| Receive Code Violation. More... | |
| #define | EMAC_RSV_CRC_ERR 0x00100000 |
| CRC Error. More... | |
| #define | EMAC_RSV_LEN_CHKERR 0x00200000 |
| Length Check Error. More... | |
| #define | EMAC_RSV_LEN_OUTRNG 0x00400000 |
| Length Out of Range. More... | |
| #define | EMAC_RSV_REC_OK 0x00800000 |
| Frame Received OK. More... | |
| #define | EMAC_RSV_MCAST 0x01000000 |
| Multicast Frame. More... | |
| #define | EMAC_RSV_BCAST 0x02000000 |
| Broadcast Frame. More... | |
| #define | EMAC_RSV_DRIB_NIBB 0x04000000 |
| Dribble Nibble. More... | |
| #define | EMAC_RSV_CTRL_FRAME 0x08000000 |
| Control Frame. More... | |
| #define | EMAC_RSV_PAUSE 0x10000000 |
| Pause Frame. More... | |
| #define | EMAC_RSV_UNSUPP_OPC 0x20000000 |
| Unsupported Opcode. More... | |
| #define | EMAC_RSV_VLAN 0x40000000 |
| VLAN Frame. More... | |
| #define | EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) |
| Macro defines for Flow Control Counter Register. More... | |
| #define | EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) |
| Pause Timer. More... | |
| #define | EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) |
| Macro defines for Flow Control Status Register. More... | |
| #define | EMAC_RFC_UCAST_EN 0x00000001 |
| Macro defines for Receive Filter Control Register. More... | |
| #define | EMAC_RFC_BCAST_EN 0x00000002 |
| Accept Broadcast Frames Enable. More... | |
| #define | EMAC_RFC_MCAST_EN 0x00000004 |
| Accept Multicast Frames Enable. More... | |
| #define | EMAC_RFC_UCAST_HASH_EN 0x00000008 |
| Accept Unicast Hash Filter Frames. More... | |
| #define | EMAC_RFC_MCAST_HASH_EN 0x00000010 |
| Accept Multicast Hash Filter Fram. More... | |
| #define | EMAC_RFC_PERFECT_EN 0x00000020 |
| Accept Perfect Match Enable. More... | |
| #define | EMAC_RFC_MAGP_WOL_EN 0x00001000 |
| Magic Packet Filter WoL Enable. More... | |
| #define | EMAC_RFC_PFILT_WOL_EN 0x00002000 |
| Perfect Filter WoL Enable. More... | |
| #define | EMAC_WOL_UCAST 0x00000001 |
| Macro defines for Receive Filter WoL Status/Clear Registers. More... | |
| #define | EMAC_WOL_BCAST 0x00000002 |
| Broadcast Frame caused WoL. More... | |
| #define | EMAC_WOL_MCAST 0x00000004 |
| Multicast Frame caused WoL. More... | |
| #define | EMAC_WOL_UCAST_HASH 0x00000008 |
| Unicast Hash Filter Frame WoL. More... | |
| #define | EMAC_WOL_MCAST_HASH 0x00000010 |
| Multicast Hash Filter Frame WoL. More... | |
| #define | EMAC_WOL_PERFECT 0x00000020 |
| Perfect Filter WoL. More... | |
| #define | EMAC_WOL_RX_FILTER 0x00000080 |
| RX Filter caused WoL. More... | |
| #define | EMAC_WOL_MAG_PACKET 0x00000100 |
| Magic Packet Filter caused WoL. More... | |
| #define | EMAC_WOL_BITMASK 0x01BF |
| Receive Filter WoL Status/Clear bitmasl value. More... | |
| #define | EMAC_INT_RX_OVERRUN 0x00000001 |
| Macro defines for Interrupt Status/Enable/Clear/Set Registers. More... | |
| #define | EMAC_INT_RX_ERR 0x00000002 |
| Receive Error. More... | |
| #define | EMAC_INT_RX_FIN 0x00000004 |
| RX Finished Process Descriptors. More... | |
| #define | EMAC_INT_RX_DONE 0x00000008 |
| Receive Done. More... | |
| #define | EMAC_INT_TX_UNDERRUN 0x00000010 |
| Transmit Underrun. More... | |
| #define | EMAC_INT_TX_ERR 0x00000020 |
| Transmit Error. More... | |
| #define | EMAC_INT_TX_FIN 0x00000040 |
| TX Finished Process Descriptors. More... | |
| #define | EMAC_INT_TX_DONE 0x00000080 |
| Transmit Done. More... | |
| #define | EMAC_INT_SOFT_INT 0x00001000 |
| Software Triggered Interrupt. More... | |
| #define | EMAC_INT_WAKEUP 0x00002000 |
| Wakeup Event Interrupt. More... | |
| #define | EMAC_PD_POWER_DOWN 0x80000000 |
| Macro defines for Power Down Register. More... | |
| #define | EMAC_RCTRL_SIZE(n) (n&0x7FF) |
| Macro defines for RX Descriptor Control Word. More... | |
| #define | EMAC_RCTRL_INT 0x80000000 |
| Generate RxDone Interrupt. More... | |
| #define | EMAC_RHASH_SA 0x000001FF |
| Macro defines for RX Status Hash CRC Word. More... | |
| #define | EMAC_RHASH_DA 0x001FF000 |
| Hash CRC for Destination Address. More... | |
| #define | EMAC_RINFO_SIZE 0x000007FF |
| Macro defines for RX Status Information Word. More... | |
| #define | EMAC_RINFO_CTRL_FRAME 0x00040000 |
| Control Frame. More... | |
| #define | EMAC_RINFO_VLAN 0x00080000 |
| VLAN Frame. More... | |
| #define | EMAC_RINFO_FAIL_FILT 0x00100000 |
| RX Filter Failed. More... | |
| #define | EMAC_RINFO_MCAST 0x00200000 |
| Multicast Frame. More... | |
| #define | EMAC_RINFO_BCAST 0x00400000 |
| Broadcast Frame. More... | |
| #define | EMAC_RINFO_CRC_ERR 0x00800000 |
| CRC Error in Frame. More... | |
| #define | EMAC_RINFO_SYM_ERR 0x01000000 |
| Symbol Error from PHY. More... | |
| #define | EMAC_RINFO_LEN_ERR 0x02000000 |
| Length Error. More... | |
| #define | EMAC_RINFO_RANGE_ERR 0x04000000 |
| Range Error (exceeded max. More... | |
| #define | EMAC_RINFO_ALIGN_ERR 0x08000000 |
| Alignment Error. More... | |
| #define | EMAC_RINFO_OVERRUN 0x10000000 |
| Receive overrun. More... | |
| #define | EMAC_RINFO_NO_DESCR 0x20000000 |
| No new Descriptor available. More... | |
| #define | EMAC_RINFO_LAST_FLAG 0x40000000 |
| Last Fragment in Frame. More... | |
| #define | EMAC_RINFO_ERR 0x80000000 |
| Error Occured (OR of all errors) More... | |
| #define | EMAC_TCTRL_SIZE 0x000007FF |
| Macro defines for TX Descriptor Control Word. More... | |
| #define | EMAC_TCTRL_OVERRIDE 0x04000000 |
| Override Default MAC Registers. More... | |
| #define | EMAC_TCTRL_HUGE 0x08000000 |
| Enable Huge Frame. More... | |
| #define | EMAC_TCTRL_PAD 0x10000000 |
| Pad short Frames to 64 bytes. More... | |
| #define | EMAC_TCTRL_CRC 0x20000000 |
| Append a hardware CRC to Frame. More... | |
| #define | EMAC_TCTRL_LAST 0x40000000 |
| Last Descriptor for TX Frame. More... | |
| #define | EMAC_TCTRL_INT 0x80000000 |
| Generate TxDone Interrupt. More... | |
| #define | EMAC_TINFO_COL_CNT 0x01E00000 |
| Macro defines for TX Status Information Word. More... | |
| #define | EMAC_TINFO_DEFER 0x02000000 |
| Packet Deferred (not an error) More... | |
| #define | EMAC_TINFO_EXCESS_DEF 0x04000000 |
| Excessive Deferral. More... | |
| #define | EMAC_TINFO_EXCESS_COL 0x08000000 |
| Excessive Collision. More... | |
| #define | EMAC_TINFO_LATE_COL 0x10000000 |
| Late Collision Occured. More... | |
| #define | EMAC_TINFO_UNDERRUN 0x20000000 |
| Transmit Underrun. More... | |
| #define | EMAC_TINFO_NO_DESCR 0x40000000 |
| No new Descriptor available. More... | |
| #define | EMAC_TINFO_ERR 0x80000000 |
| Error Occured (OR of all errors) More... | |
| #define | EMAC_PHY_RESP_TOUT 0x100000UL |
| PHY device reset time out definition. More... | |
| #define | EMAC_OLD_EMAC_MODULE_ID 0x39022000 |
| Rev. More... | |
| #define | EMAC_PHY_REG_BMCR 0x00 |
| Macro defines for DP83848C PHY Registers. More... | |
| #define | EMAC_PHY_REG_BMSR 0x01 |
| Basic Mode Status Register. More... | |
| #define | EMAC_PHY_REG_IDR1 0x02 |
| PHY Identifier 1. More... | |
| #define | EMAC_PHY_REG_IDR2 0x03 |
| PHY Identifier 2. More... | |
| #define | EMAC_PHY_REG_ANAR 0x04 |
| Auto-Negotiation Advertisement. More... | |
| #define | EMAC_PHY_REG_ANLPAR 0x05 |
| Auto-Neg. More... | |
| #define | EMAC_PHY_REG_ANER 0x06 |
| Auto-Neg. More... | |
| #define | EMAC_PHY_REG_ANNPTR 0x07 |
| Auto-Neg. More... | |
| #define | EMAC_PHY_REG_STS 0x10 |
| Macro defines for PHY Extended Registers. More... | |
| #define | EMAC_PHY_REG_MICR 0x11 |
| MII Interrupt Control Register. More... | |
| #define | EMAC_PHY_REG_MISR 0x12 |
| MII Interrupt Status Register. More... | |
| #define | EMAC_PHY_REG_FCSCR 0x14 |
| False Carrier Sense Counter. More... | |
| #define | EMAC_PHY_REG_RECR 0x15 |
| Receive Error Counter. More... | |
| #define | EMAC_PHY_REG_PCSR 0x16 |
| PCS Sublayer Config. More... | |
| #define | EMAC_PHY_REG_RBR 0x17 |
| RMII and Bypass Register. More... | |
| #define | EMAC_PHY_REG_LEDCR 0x18 |
| LED Direct Control Register. More... | |
| #define | EMAC_PHY_REG_PHYCR 0x19 |
| PHY Control Register. More... | |
| #define | EMAC_PHY_REG_10BTSCR 0x1A |
| 10Base-T Status/Control Register More... | |
| #define | EMAC_PHY_REG_CDCTRL1 0x1B |
| CD Test Control and BIST Extens. More... | |
| #define | EMAC_PHY_REG_EDCR 0x1D |
| Energy Detect Control Register. More... | |
| #define | EMAC_PHY_BMCR_RESET (1<<15) |
| Macro defines for PHY Basic Mode Control Register. More... | |
| #define | EMAC_PHY_BMCR_LOOPBACK (1<<14) |
| Loop back. More... | |
| #define | EMAC_PHY_BMCR_SPEED_SEL (1<<13) |
| Speed selection. More... | |
| #define | EMAC_PHY_BMCR_AN (1<<12) |
| Auto Negotiation. More... | |
| #define | EMAC_PHY_BMCR_POWERDOWN (1<<11) |
| Power down mode. More... | |
| #define | EMAC_PHY_BMCR_ISOLATE (1<<10) |
| Isolate. More... | |
| #define | EMAC_PHY_BMCR_RE_AN (1<<9) |
| Restart auto negotiation. More... | |
| #define | EMAC_PHY_BMCR_DUPLEX (1<<8) |
| Duplex mode. More... | |
| #define | EMAC_PHY_BMSR_100BE_T4 (1<<15) |
| Macro defines for PHY Basic Mode Status Status Register. More... | |
| #define | EMAC_PHY_BMSR_100TX_FULL (1<<14) |
| 100 base full duplex More... | |
| #define | EMAC_PHY_BMSR_100TX_HALF (1<<13) |
| 100 base half duplex More... | |
| #define | EMAC_PHY_BMSR_10BE_FULL (1<<12) |
| 10 base T full duplex More... | |
| #define | EMAC_PHY_BMSR_10BE_HALF (1<<11) |
| 10 base T half duplex More... | |
| #define | EMAC_PHY_BMSR_NOPREAM (1<<6) |
| MF Preamable Supress. More... | |
| #define | EMAC_PHY_BMSR_AUTO_DONE (1<<5) |
| Auto negotiation complete. More... | |
| #define | EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) |
| Remote fault. More... | |
| #define | EMAC_PHY_BMSR_NO_AUTO (1<<3) |
| Auto Negotiation ability. More... | |
| #define | EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) |
| Link status. More... | |
| #define | EMAC_PHY_SR_REMOTE_FAULT (1<<6) |
| Macro defines for PHY Status Register. More... | |
| #define | EMAC_PHY_SR_JABBER (1<<5) |
| Jabber detect. More... | |
| #define | EMAC_PHY_SR_AUTO_DONE (1<<4) |
| Auto Negotiation complete. More... | |
| #define | EMAC_PHY_SR_LOOPBACK (1<<3) |
| Loop back status. More... | |
| #define | EMAC_PHY_SR_DUP (1<<2) |
| Duplex status. More... | |
| #define | EMAC_PHY_SR_SPEED (1<<1) |
| Speed status. More... | |
| #define | EMAC_PHY_SR_LINK (1<<0) |
| Link Status. More... | |
| #define | EMAC_PHY_FULLD_100M 0x2100 |
| Full Duplex 100Mbit. More... | |
| #define | EMAC_PHY_HALFD_100M 0x2000 |
| Half Duplex 100Mbit. More... | |
| #define | EMAC_PHY_FULLD_10M 0x0100 |
| Full Duplex 10Mbit. More... | |
| #define | EMAC_PHY_HALFD_10M 0x0000 |
| Half Duplex 10MBit. More... | |
| #define | EMAC_PHY_AUTO_NEG 0x3000 |
| Select Auto Negotiation. More... | |
| #define | EMAC_DEF_ADR 0x0100 |
| Default PHY device address. More... | |
| #define | EMAC_DP83848C_ID 0x20005C90 |
| PHY Identifier. More... | |
| #define | EMAC_PHY_BMSR_LINK_STATUS (1<<2) |
| Link status. More... | |
| #define EMAC_CLRT_COLL | ( | n | ) | ((n&0x3F)<<8) |
Programmable field representing the slot time or collision window during which collisions occur in properly configured networks.
Definition at line 149 of file lpc17xx_emac.h.
| #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37))) |
Default value for Collision Window / Retry register.
Definition at line 151 of file lpc17xx_emac.h.
| #define EMAC_CLRT_MAX_RETX | ( | n | ) | (n&0x0F) |
Macro defines for Collision Window/Retry Register.
Programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions
Definition at line 146 of file lpc17xx_emac.h.
| #define EMAC_CR_FULL_DUP 0x00000400 |
Full Duplex.
Definition at line 232 of file lpc17xx_emac.h.
| #define EMAC_CR_PASS_RUNT_FRM 0x00000040 |
Pass Runt Frames.
Definition at line 228 of file lpc17xx_emac.h.
| #define EMAC_CR_PASS_RX_FILT 0x00000080 |
Pass RX Filter.
Definition at line 229 of file lpc17xx_emac.h.
| #define EMAC_CR_REG_RES 0x00000008 |
Reset Host Registers.
Definition at line 225 of file lpc17xx_emac.h.
| #define EMAC_CR_RMII 0x00000200 |
Reduced MII Interface.
Definition at line 231 of file lpc17xx_emac.h.
| #define EMAC_CR_RX_EN 0x00000001 |
| #define EMAC_CR_RX_RES 0x00000020 |
Reset Receive Datapath.
Definition at line 227 of file lpc17xx_emac.h.
| #define EMAC_CR_TX_EN 0x00000002 |
Enable Transmit.
Definition at line 224 of file lpc17xx_emac.h.
| #define EMAC_CR_TX_FLOW_CTRL 0x00000100 |
TX Flow Control.
Definition at line 230 of file lpc17xx_emac.h.
| #define EMAC_CR_TX_RES 0x00000010 |
Reset Transmit Datapath.
Definition at line 226 of file lpc17xx_emac.h.
| #define EMAC_DEF_ADR 0x0100 |
Default PHY device address.
Definition at line 484 of file lpc17xx_emac.h.
| #define EMAC_DP83848C_ID 0x20005C90 |
PHY Identifier.
Definition at line 485 of file lpc17xx_emac.h.
| #define EMAC_ETH_MAX_FLEN 1536 |
| #define EMAC_FCC_MIRR_CNT | ( | n | ) | (n&0xFFFF) |
Macro defines for Flow Control Counter Register.
Mirror Counter
Definition at line 290 of file lpc17xx_emac.h.
| #define EMAC_FCC_PAUSE_TIM | ( | n | ) | ((n&0xFFFF)<<16) |
Pause Timer.
Definition at line 291 of file lpc17xx_emac.h.
| #define EMAC_FCS_MIRR_CNT | ( | n | ) | (n&0xFFFF) |
Macro defines for Flow Control Status Register.
Mirror Counter Current
Definition at line 296 of file lpc17xx_emac.h.
| #define EMAC_INT_RX_DONE 0x00000008 |
Receive Done.
Definition at line 333 of file lpc17xx_emac.h.
| #define EMAC_INT_RX_ERR 0x00000002 |
Receive Error.
Definition at line 331 of file lpc17xx_emac.h.
| #define EMAC_INT_RX_FIN 0x00000004 |
RX Finished Process Descriptors.
Definition at line 332 of file lpc17xx_emac.h.
| #define EMAC_INT_RX_OVERRUN 0x00000001 |
Macro defines for Interrupt Status/Enable/Clear/Set Registers.
Overrun Error in RX Queue
Definition at line 330 of file lpc17xx_emac.h.
| #define EMAC_INT_SOFT_INT 0x00001000 |
Software Triggered Interrupt.
Definition at line 338 of file lpc17xx_emac.h.
| #define EMAC_INT_TX_DONE 0x00000080 |
Transmit Done.
Definition at line 337 of file lpc17xx_emac.h.
| #define EMAC_INT_TX_ERR 0x00000020 |
Transmit Error.
Definition at line 335 of file lpc17xx_emac.h.
| #define EMAC_INT_TX_FIN 0x00000040 |
TX Finished Process Descriptors.
Definition at line 336 of file lpc17xx_emac.h.
| #define EMAC_INT_TX_UNDERRUN 0x00000010 |
Transmit Underrun.
Definition at line 334 of file lpc17xx_emac.h.
| #define EMAC_INT_WAKEUP 0x00002000 |
Wakeup Event Interrupt.
Definition at line 339 of file lpc17xx_emac.h.
| #define EMAC_IPGR_NBBIPG_P1 | ( | n | ) | ((n&0x7F)<<8) |
Programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'.
Definition at line 137 of file lpc17xx_emac.h.
| #define EMAC_IPGR_NBBIPG_P2 | ( | n | ) | (n&0x7F) |
Macro defines for Non Back-to-Back Inter-Packet-Gap Register.
Programmable field representing the Non-Back-to-Back Inter-Packet-Gap
Definition at line 132 of file lpc17xx_emac.h.
| #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C) |
Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2.
Definition at line 139 of file lpc17xx_emac.h.
| #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12)) |
Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1.
Definition at line 134 of file lpc17xx_emac.h.
| #define EMAC_IPGT_BBIPG | ( | n | ) | (n&0x7F) |
Macro defines for Back-to-Back Inter-Packet-Gap Register.
Programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next
Definition at line 118 of file lpc17xx_emac.h.
| #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15)) |
Recommended value for Full Duplex of Programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next.
Definition at line 122 of file lpc17xx_emac.h.
| #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12)) |
Recommended value for Half Duplex of Programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next.
Definition at line 126 of file lpc17xx_emac.h.
| #define EMAC_MAC1_LOOPB 0x00000010 |
Loop Back Mode.
Definition at line 88 of file lpc17xx_emac.h.
| #define EMAC_MAC1_PASS_ALL 0x00000002 |
Pass All Receive Frames.
Definition at line 85 of file lpc17xx_emac.h.
| #define EMAC_MAC1_REC_EN 0x00000001 |
Macro defines for MAC Configuration Register 1.
Receive Enable
Definition at line 84 of file lpc17xx_emac.h.
| #define EMAC_MAC1_RES_MCS_RX 0x00000800 |
Reset MAC RX Control Sublayer.
Definition at line 92 of file lpc17xx_emac.h.
| #define EMAC_MAC1_RES_MCS_TX 0x00000200 |
Reset MAC TX Control Sublayer.
Definition at line 90 of file lpc17xx_emac.h.
| #define EMAC_MAC1_RES_RX 0x00000400 |
Reset RX Logic.
Definition at line 91 of file lpc17xx_emac.h.
| #define EMAC_MAC1_RES_TX 0x00000100 |
Reset TX Logic.
Definition at line 89 of file lpc17xx_emac.h.
| #define EMAC_MAC1_RX_FLOWC 0x00000004 |
RX Flow Control.
Definition at line 86 of file lpc17xx_emac.h.
| #define EMAC_MAC1_SIM_RES 0x00004000 |
Simulation Reset.
Definition at line 93 of file lpc17xx_emac.h.
| #define EMAC_MAC1_SOFT_RES 0x00008000 |
Soft Reset MAC.
Definition at line 94 of file lpc17xx_emac.h.
| #define EMAC_MAC1_TX_FLOWC 0x00000008 |
TX Flow Control.
Definition at line 87 of file lpc17xx_emac.h.
| #define EMAC_MAC2_ADET_PAD_EN 0x00000080 |
Auto Detect Pad Enable.
Definition at line 106 of file lpc17xx_emac.h.
| #define EMAC_MAC2_BACK_PRESSURE 0x00002000 |
Backoff Presurre / No Backoff.
Definition at line 110 of file lpc17xx_emac.h.
| #define EMAC_MAC2_CRC_EN 0x00000010 |
Append CRC to every Frame.
Definition at line 103 of file lpc17xx_emac.h.
| #define EMAC_MAC2_DLY_CRC 0x00000008 |
Delayed CRC Mode.
Definition at line 102 of file lpc17xx_emac.h.
| #define EMAC_MAC2_EXCESS_DEF 0x00004000 |
Excess Defer.
Definition at line 111 of file lpc17xx_emac.h.
| #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 |
Frame Length Checking.
Definition at line 100 of file lpc17xx_emac.h.
| #define EMAC_MAC2_FULL_DUP 0x00000001 |
Macro defines for MAC Configuration Register 2.
Full-Duplex Mode
Definition at line 99 of file lpc17xx_emac.h.
| #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 |
Huge Frame Enable.
Definition at line 101 of file lpc17xx_emac.h.
| #define EMAC_MAC2_LPREAM_ENF 0x00000200 |
Long Preamble Enforcement.
Definition at line 108 of file lpc17xx_emac.h.
| #define EMAC_MAC2_NO_BACKOFF 0x00001000 |
No Backoff Algorithm.
Definition at line 109 of file lpc17xx_emac.h.
| #define EMAC_MAC2_PAD_EN 0x00000020 |
Pad all Short Frames.
Definition at line 104 of file lpc17xx_emac.h.
| #define EMAC_MAC2_PPREAM_ENF 0x00000100 |
Pure Preamble Enforcement.
Definition at line 107 of file lpc17xx_emac.h.
| #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 |
VLAN Pad Enable.
Definition at line 105 of file lpc17xx_emac.h.
| #define EMAC_MADR_PHY_ADR | ( | n | ) | ((n&0x1F)<<8) |
PHY Address Field.
Definition at line 194 of file lpc17xx_emac.h.
| #define EMAC_MADR_REG_ADR | ( | n | ) | (n&0x1F) |
Macro defines for MII Management Address Register.
MII Register Address field
Definition at line 193 of file lpc17xx_emac.h.
| #define EMAC_MAXF_MAXFRMLEN | ( | n | ) | (n&0xFFFF) |
Macro defines for Maximum Frame Register.
Represents a maximum receive frame of 1536 octets
Definition at line 157 of file lpc17xx_emac.h.
| #define EMAC_MCFG_CLK_SEL | ( | n | ) | ((n&0x0F)<<2) |
Clock Select Field.
Definition at line 177 of file lpc17xx_emac.h.
| #define EMAC_MCFG_MII_MAXCLK 2500000UL |
MII Clock max.
Definition at line 179 of file lpc17xx_emac.h.
| #define EMAC_MCFG_RES_MII 0x00008000 |
Reset MII Management Hardware.
Definition at line 178 of file lpc17xx_emac.h.
| #define EMAC_MCFG_SCAN_INC 0x00000001 |
Macro defines for MII Management Configuration Register.
Scan Increment PHY Address
Definition at line 175 of file lpc17xx_emac.h.
| #define EMAC_MCFG_SUPP_PREAM 0x00000002 |
Suppress Preamble.
Definition at line 176 of file lpc17xx_emac.h.
| #define EMAC_MCMD_READ 0x00000001 |
Macro defines for MII Management Command Register.
MII Read
Definition at line 184 of file lpc17xx_emac.h.
| #define EMAC_MCMD_SCAN 0x00000002 |
MII Scan continuously.
Definition at line 185 of file lpc17xx_emac.h.
| #define EMAC_MII_RD_TOUT 0x00050000 |
MII Read timeout count.
Definition at line 188 of file lpc17xx_emac.h.
| #define EMAC_MII_WR_TOUT 0x00050000 |
MII Write timeout count.
Definition at line 187 of file lpc17xx_emac.h.
| #define EMAC_MIND_BUSY 0x00000001 |
Macro defines for MII Management Indicators Register.
MII is Busy
Definition at line 209 of file lpc17xx_emac.h.
| #define EMAC_MIND_MII_LINK_FAIL 0x00000008 |
MII Link Failed.
Definition at line 212 of file lpc17xx_emac.h.
| #define EMAC_MIND_NOT_VAL 0x00000004 |
MII Read Data not valid.
Definition at line 211 of file lpc17xx_emac.h.
| #define EMAC_MIND_SCAN 0x00000002 |
MII Scanning in Progress.
Definition at line 210 of file lpc17xx_emac.h.
| #define EMAC_MRDD_DATA | ( | n | ) | (n&0xFFFF) |
Macro defines for MII Management Read Data Register.
Data field for MMI Management Read Data register
Definition at line 204 of file lpc17xx_emac.h.
| #define EMAC_MWTD_DATA | ( | n | ) | (n&0xFFFF) |
Macro defines for MII Management Write Data Register.
Data field for MMI Management Write Data register
Definition at line 199 of file lpc17xx_emac.h.
| #define EMAC_NUM_RX_FRAG 4 |
Num.of RX Fragments 4*1536= 6.0kB.
Definition at line 75 of file lpc17xx_emac.h.
| #define EMAC_NUM_TX_FRAG 3 |
Num.of TX Fragments 3*1536= 4.6kB.
Definition at line 76 of file lpc17xx_emac.h.
| #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 |
| #define EMAC_PD_POWER_DOWN 0x80000000 |
Macro defines for Power Down Register.
Power Down MAC
Definition at line 344 of file lpc17xx_emac.h.
| #define EMAC_PHY_AUTO_NEG 0x3000 |
Select Auto Negotiation.
Definition at line 482 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMCR_AN (1<<12) |
Auto Negotiation.
Definition at line 447 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMCR_DUPLEX (1<<8) |
Duplex mode.
Definition at line 451 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMCR_ISOLATE (1<<10) |
Isolate.
Definition at line 449 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMCR_LOOPBACK (1<<14) |
Loop back.
Definition at line 445 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMCR_POWERDOWN (1<<11) |
Power down mode.
Definition at line 448 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMCR_RE_AN (1<<9) |
Restart auto negotiation.
Definition at line 450 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMCR_RESET (1<<15) |
Macro defines for PHY Basic Mode Control Register.
Reset bit
Definition at line 444 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) |
Speed selection.
Definition at line 446 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMSR_100BE_T4 (1<<15) |
Macro defines for PHY Basic Mode Status Status Register.
100 base T4
Definition at line 456 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMSR_100TX_FULL (1<<14) |
100 base full duplex
Definition at line 457 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMSR_100TX_HALF (1<<13) |
100 base half duplex
Definition at line 458 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMSR_10BE_FULL (1<<12) |
10 base T full duplex
Definition at line 459 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMSR_10BE_HALF (1<<11) |
10 base T half duplex
Definition at line 460 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) |
Auto negotiation complete.
Definition at line 462 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) |
Link status.
Definition at line 465 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) |
Link status.
Definition at line 489 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMSR_NO_AUTO (1<<3) |
Auto Negotiation ability.
Definition at line 464 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMSR_NOPREAM (1<<6) |
MF Preamable Supress.
Definition at line 461 of file lpc17xx_emac.h.
| #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) |
Remote fault.
Definition at line 463 of file lpc17xx_emac.h.
| #define EMAC_PHY_FULLD_100M 0x2100 |
Full Duplex 100Mbit.
Definition at line 478 of file lpc17xx_emac.h.
| #define EMAC_PHY_FULLD_10M 0x0100 |
Full Duplex 10Mbit.
Definition at line 480 of file lpc17xx_emac.h.
| #define EMAC_PHY_HALFD_100M 0x2000 |
Half Duplex 100Mbit.
Definition at line 479 of file lpc17xx_emac.h.
| #define EMAC_PHY_HALFD_10M 0x0000 |
Half Duplex 10MBit.
Definition at line 481 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_10BTSCR 0x1A |
10Base-T Status/Control Register
Definition at line 437 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_ANAR 0x04 |
Auto-Negotiation Advertisement.
Definition at line 419 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_ANER 0x06 |
| #define EMAC_PHY_REG_ANLPAR 0x05 |
| #define EMAC_PHY_REG_ANNPTR 0x07 |
| #define EMAC_PHY_REG_BMCR 0x00 |
Macro defines for DP83848C PHY Registers.
Basic Mode Control Register
Definition at line 415 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_BMSR 0x01 |
Basic Mode Status Register.
Definition at line 416 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_CDCTRL1 0x1B |
CD Test Control and BIST Extens.
Definition at line 438 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_EDCR 0x1D |
Energy Detect Control Register.
Definition at line 439 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_FCSCR 0x14 |
False Carrier Sense Counter.
Definition at line 431 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_IDR1 0x02 |
PHY Identifier 1.
Definition at line 417 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_IDR2 0x03 |
PHY Identifier 2.
Definition at line 418 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_LEDCR 0x18 |
LED Direct Control Register.
Definition at line 435 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_MICR 0x11 |
MII Interrupt Control Register.
Definition at line 429 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_MISR 0x12 |
MII Interrupt Status Register.
Definition at line 430 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_PCSR 0x16 |
| #define EMAC_PHY_REG_PHYCR 0x19 |
PHY Control Register.
Definition at line 436 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_RBR 0x17 |
RMII and Bypass Register.
Definition at line 434 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_RECR 0x15 |
Receive Error Counter.
Definition at line 432 of file lpc17xx_emac.h.
| #define EMAC_PHY_REG_STS 0x10 |
Macro defines for PHY Extended Registers.
Status Register
Definition at line 428 of file lpc17xx_emac.h.
| #define EMAC_PHY_RESP_TOUT 0x100000UL |
PHY device reset time out definition.
Definition at line 407 of file lpc17xx_emac.h.
| #define EMAC_PHY_SR_AUTO_DONE (1<<4) |
Auto Negotiation complete.
Definition at line 472 of file lpc17xx_emac.h.
| #define EMAC_PHY_SR_DUP (1<<2) |
Duplex status.
Definition at line 474 of file lpc17xx_emac.h.
| #define EMAC_PHY_SR_JABBER (1<<5) |
Jabber detect.
Definition at line 471 of file lpc17xx_emac.h.
| #define EMAC_PHY_SR_LINK (1<<0) |
Link Status.
Definition at line 476 of file lpc17xx_emac.h.
| #define EMAC_PHY_SR_LOOPBACK (1<<3) |
Loop back status.
Definition at line 473 of file lpc17xx_emac.h.
| #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) |
| #define EMAC_PHY_SR_SPEED (1<<1) |
Speed status.
Definition at line 475 of file lpc17xx_emac.h.
| #define EMAC_RCTRL_INT 0x80000000 |
Generate RxDone Interrupt.
Definition at line 351 of file lpc17xx_emac.h.
| #define EMAC_RCTRL_SIZE | ( | n | ) | (n&0x7FF) |
Macro defines for RX Descriptor Control Word.
Buffer size field
Definition at line 350 of file lpc17xx_emac.h.
| #define EMAC_RFC_BCAST_EN 0x00000002 |
Accept Broadcast Frames Enable.
Definition at line 304 of file lpc17xx_emac.h.
| #define EMAC_RFC_MAGP_WOL_EN 0x00001000 |
Magic Packet Filter WoL Enable.
Definition at line 309 of file lpc17xx_emac.h.
| #define EMAC_RFC_MCAST_EN 0x00000004 |
Accept Multicast Frames Enable.
Definition at line 305 of file lpc17xx_emac.h.
| #define EMAC_RFC_MCAST_HASH_EN 0x00000010 |
Accept Multicast Hash Filter Fram.
Definition at line 307 of file lpc17xx_emac.h.
| #define EMAC_RFC_PERFECT_EN 0x00000020 |
Accept Perfect Match Enable.
Definition at line 308 of file lpc17xx_emac.h.
| #define EMAC_RFC_PFILT_WOL_EN 0x00002000 |
Perfect Filter WoL Enable.
Definition at line 310 of file lpc17xx_emac.h.
| #define EMAC_RFC_UCAST_EN 0x00000001 |
Macro defines for Receive Filter Control Register.
Accept Unicast Frames Enable
Definition at line 303 of file lpc17xx_emac.h.
| #define EMAC_RFC_UCAST_HASH_EN 0x00000008 |
Accept Unicast Hash Filter Frames.
Definition at line 306 of file lpc17xx_emac.h.
| #define EMAC_RHASH_DA 0x001FF000 |
Hash CRC for Destination Address.
Definition at line 357 of file lpc17xx_emac.h.
| #define EMAC_RHASH_SA 0x000001FF |
Macro defines for RX Status Hash CRC Word.
Hash CRC for Source Address
Definition at line 356 of file lpc17xx_emac.h.
| #define EMAC_RINFO_ALIGN_ERR 0x08000000 |
Alignment Error.
Definition at line 372 of file lpc17xx_emac.h.
| #define EMAC_RINFO_BCAST 0x00400000 |
Broadcast Frame.
Definition at line 367 of file lpc17xx_emac.h.
| #define EMAC_RINFO_CRC_ERR 0x00800000 |
CRC Error in Frame.
Definition at line 368 of file lpc17xx_emac.h.
| #define EMAC_RINFO_CTRL_FRAME 0x00040000 |
Control Frame.
Definition at line 363 of file lpc17xx_emac.h.
| #define EMAC_RINFO_ERR 0x80000000 |
Error Occured (OR of all errors)
Definition at line 376 of file lpc17xx_emac.h.
| #define EMAC_RINFO_FAIL_FILT 0x00100000 |
RX Filter Failed.
Definition at line 365 of file lpc17xx_emac.h.
| #define EMAC_RINFO_LAST_FLAG 0x40000000 |
Last Fragment in Frame.
Definition at line 375 of file lpc17xx_emac.h.
| #define EMAC_RINFO_LEN_ERR 0x02000000 |
Length Error.
Definition at line 370 of file lpc17xx_emac.h.
| #define EMAC_RINFO_MCAST 0x00200000 |
Multicast Frame.
Definition at line 366 of file lpc17xx_emac.h.
| #define EMAC_RINFO_NO_DESCR 0x20000000 |
No new Descriptor available.
Definition at line 374 of file lpc17xx_emac.h.
| #define EMAC_RINFO_OVERRUN 0x10000000 |
Receive overrun.
Definition at line 373 of file lpc17xx_emac.h.
| #define EMAC_RINFO_RANGE_ERR 0x04000000 |
| #define EMAC_RINFO_SIZE 0x000007FF |
Macro defines for RX Status Information Word.
Data size in bytes
Definition at line 362 of file lpc17xx_emac.h.
| #define EMAC_RINFO_SYM_ERR 0x01000000 |
Symbol Error from PHY.
Definition at line 369 of file lpc17xx_emac.h.
| #define EMAC_RINFO_VLAN 0x00080000 |
VLAN Frame.
Definition at line 364 of file lpc17xx_emac.h.
| #define EMAC_RSV_BCAST 0x02000000 |
Broadcast Frame.
Definition at line 280 of file lpc17xx_emac.h.
| #define EMAC_RSV_BYTE_CNT 0x0000FFFF |
Macro defines for Receive Status Vector Register.
Receive Byte Count
Definition at line 270 of file lpc17xx_emac.h.
| #define EMAC_RSV_CARR_SEEN 0x00040000 |
Carrier Event Previously Seen.
Definition at line 273 of file lpc17xx_emac.h.
| #define EMAC_RSV_CRC_ERR 0x00100000 |
CRC Error.
Definition at line 275 of file lpc17xx_emac.h.
| #define EMAC_RSV_CTRL_FRAME 0x08000000 |
Control Frame.
Definition at line 282 of file lpc17xx_emac.h.
| #define EMAC_RSV_DRIB_NIBB 0x04000000 |
Dribble Nibble.
Definition at line 281 of file lpc17xx_emac.h.
| #define EMAC_RSV_LEN_CHKERR 0x00200000 |
Length Check Error.
Definition at line 276 of file lpc17xx_emac.h.
| #define EMAC_RSV_LEN_OUTRNG 0x00400000 |
Length Out of Range.
Definition at line 277 of file lpc17xx_emac.h.
| #define EMAC_RSV_MCAST 0x01000000 |
Multicast Frame.
Definition at line 279 of file lpc17xx_emac.h.
| #define EMAC_RSV_PAUSE 0x10000000 |
Pause Frame.
Definition at line 283 of file lpc17xx_emac.h.
| #define EMAC_RSV_PKT_IGNORED 0x00010000 |
Packet Previously Ignored.
Definition at line 271 of file lpc17xx_emac.h.
| #define EMAC_RSV_REC_CODEV 0x00080000 |
Receive Code Violation.
Definition at line 274 of file lpc17xx_emac.h.
| #define EMAC_RSV_REC_OK 0x00800000 |
Frame Received OK.
Definition at line 278 of file lpc17xx_emac.h.
| #define EMAC_RSV_RXDV_SEEN 0x00020000 |
RXDV Event Previously Seen.
Definition at line 272 of file lpc17xx_emac.h.
| #define EMAC_RSV_UNSUPP_OPC 0x20000000 |
Unsupported Opcode.
Definition at line 284 of file lpc17xx_emac.h.
| #define EMAC_RSV_VLAN 0x40000000 |
VLAN Frame.
Definition at line 285 of file lpc17xx_emac.h.
| #define EMAC_SR_RX_EN 0x00000001 |
| #define EMAC_SR_TX_EN 0x00000002 |
Enable Transmit.
Definition at line 238 of file lpc17xx_emac.h.
| #define EMAC_SUPP_RES_RMII 0x00000800 |
Reset Reduced MII Logic.
Definition at line 163 of file lpc17xx_emac.h.
| #define EMAC_SUPP_SPEED 0x00000100 |
Macro defines for PHY Support Register.
Reduced MII Logic Current Speed
Definition at line 162 of file lpc17xx_emac.h.
| #define EMAC_TCTRL_CRC 0x20000000 |
Append a hardware CRC to Frame.
Definition at line 387 of file lpc17xx_emac.h.
| #define EMAC_TCTRL_HUGE 0x08000000 |
Enable Huge Frame.
Definition at line 385 of file lpc17xx_emac.h.
| #define EMAC_TCTRL_INT 0x80000000 |
Generate TxDone Interrupt.
Definition at line 389 of file lpc17xx_emac.h.
| #define EMAC_TCTRL_LAST 0x40000000 |
Last Descriptor for TX Frame.
Definition at line 388 of file lpc17xx_emac.h.
| #define EMAC_TCTRL_OVERRIDE 0x04000000 |
Override Default MAC Registers.
Definition at line 384 of file lpc17xx_emac.h.
| #define EMAC_TCTRL_PAD 0x10000000 |
Pad short Frames to 64 bytes.
Definition at line 386 of file lpc17xx_emac.h.
| #define EMAC_TCTRL_SIZE 0x000007FF |
Macro defines for TX Descriptor Control Word.
Size of data buffer in bytes
Definition at line 383 of file lpc17xx_emac.h.
| #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 |
Macro defines for Test Register.
Shortcut Pause Quanta
Definition at line 168 of file lpc17xx_emac.h.
| #define EMAC_TEST_TST_BACKP 0x00000004 |
Test Back Pressure.
Definition at line 170 of file lpc17xx_emac.h.
| #define EMAC_TEST_TST_PAUSE 0x00000002 |
Test Pause.
Definition at line 169 of file lpc17xx_emac.h.
| #define EMAC_TINFO_COL_CNT 0x01E00000 |
Macro defines for TX Status Information Word.
Collision Count
Definition at line 394 of file lpc17xx_emac.h.
| #define EMAC_TINFO_DEFER 0x02000000 |
Packet Deferred (not an error)
Definition at line 395 of file lpc17xx_emac.h.
| #define EMAC_TINFO_ERR 0x80000000 |
Error Occured (OR of all errors)
Definition at line 401 of file lpc17xx_emac.h.
| #define EMAC_TINFO_EXCESS_COL 0x08000000 |
Excessive Collision.
Definition at line 397 of file lpc17xx_emac.h.
| #define EMAC_TINFO_EXCESS_DEF 0x04000000 |
Excessive Deferral.
Definition at line 396 of file lpc17xx_emac.h.
| #define EMAC_TINFO_LATE_COL 0x10000000 |
Late Collision Occured.
Definition at line 398 of file lpc17xx_emac.h.
| #define EMAC_TINFO_NO_DESCR 0x40000000 |
No new Descriptor available.
Definition at line 400 of file lpc17xx_emac.h.
| #define EMAC_TINFO_UNDERRUN 0x20000000 |
Transmit Underrun.
Definition at line 399 of file lpc17xx_emac.h.
| #define EMAC_TSV0_BACK_PRESS 0x40000000 |
Backpressure Method Applied.
Definition at line 258 of file lpc17xx_emac.h.
| #define EMAC_TSV0_BCAST 0x00000020 |
Broadcast Destination.
Definition at line 248 of file lpc17xx_emac.h.
| #define EMAC_TSV0_BYTES 0x0FFFF000 |
Total Bytes Transferred.
Definition at line 255 of file lpc17xx_emac.h.
| #define EMAC_TSV0_CRC_ERR 0x00000001 |
Macro defines for Transmit Status Vector 0 Register.
CRC error
Definition at line 243 of file lpc17xx_emac.h.
| #define EMAC_TSV0_CTRL_FRAME 0x10000000 |
Control Frame.
Definition at line 256 of file lpc17xx_emac.h.
| #define EMAC_TSV0_DONE 0x00000008 |
Tramsmission Completed.
Definition at line 246 of file lpc17xx_emac.h.
| #define EMAC_TSV0_EXC_COLL 0x00000100 |
Excessive Collision.
Definition at line 251 of file lpc17xx_emac.h.
| #define EMAC_TSV0_EXC_DEFER 0x00000080 |
Excessive Packet Deferral.
Definition at line 250 of file lpc17xx_emac.h.
| #define EMAC_TSV0_GIANT 0x00000400 |
Giant Frame.
Definition at line 253 of file lpc17xx_emac.h.
| #define EMAC_TSV0_LATE_COLL 0x00000200 |
Late Collision Occured.
Definition at line 252 of file lpc17xx_emac.h.
| #define EMAC_TSV0_LEN_CHKERR 0x00000002 |
Length Check Error.
Definition at line 244 of file lpc17xx_emac.h.
| #define EMAC_TSV0_LEN_OUTRNG 0x00000004 |
Length Out of Range.
Definition at line 245 of file lpc17xx_emac.h.
| #define EMAC_TSV0_MCAST 0x00000010 |
Multicast Destination.
Definition at line 247 of file lpc17xx_emac.h.
| #define EMAC_TSV0_PAUSE 0x20000000 |
Pause Frame.
Definition at line 257 of file lpc17xx_emac.h.
| #define EMAC_TSV0_PKT_DEFER 0x00000040 |
Packet Deferred.
Definition at line 249 of file lpc17xx_emac.h.
| #define EMAC_TSV0_UNDERRUN 0x00000800 |
Buffer Underrun.
Definition at line 254 of file lpc17xx_emac.h.
| #define EMAC_TSV0_VLAN 0x80000000 |
VLAN Frame.
Definition at line 259 of file lpc17xx_emac.h.
| #define EMAC_TSV1_BYTE_CNT 0x0000FFFF |
Macro defines for Transmit Status Vector 1 Register.
Transmit Byte Count
Definition at line 264 of file lpc17xx_emac.h.
| #define EMAC_TSV1_COLL_CNT 0x000F0000 |
Transmit Collision Count.
Definition at line 265 of file lpc17xx_emac.h.
| #define EMAC_TX_FRAME_TOUT 0x00100000 |
Frame Transmit timeout count.
Definition at line 78 of file lpc17xx_emac.h.
| #define EMAC_WOL_BCAST 0x00000002 |
Broadcast Frame caused WoL.
Definition at line 316 of file lpc17xx_emac.h.
| #define EMAC_WOL_BITMASK 0x01BF |
Receive Filter WoL Status/Clear bitmasl value.
Definition at line 323 of file lpc17xx_emac.h.
| #define EMAC_WOL_MAG_PACKET 0x00000100 |
Magic Packet Filter caused WoL.
Definition at line 322 of file lpc17xx_emac.h.
| #define EMAC_WOL_MCAST 0x00000004 |
Multicast Frame caused WoL.
Definition at line 317 of file lpc17xx_emac.h.
| #define EMAC_WOL_MCAST_HASH 0x00000010 |
Multicast Hash Filter Frame WoL.
Definition at line 319 of file lpc17xx_emac.h.
| #define EMAC_WOL_PERFECT 0x00000020 |
Perfect Filter WoL.
Definition at line 320 of file lpc17xx_emac.h.
| #define EMAC_WOL_RX_FILTER 0x00000080 |
RX Filter caused WoL.
Definition at line 321 of file lpc17xx_emac.h.
| #define EMAC_WOL_UCAST 0x00000001 |
Macro defines for Receive Filter WoL Status/Clear Registers.
Unicast Frame caused WoL
Definition at line 315 of file lpc17xx_emac.h.
| #define EMAC_WOL_UCAST_HASH 0x00000008 |
Unicast Hash Filter Frame WoL.
Definition at line 318 of file lpc17xx_emac.h.
