Keil Studio Cloud
Mistake on this page?
Report an issue in GitHub or email us
gpio_irq_fpga_test.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2019 ARM Limited
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 
18 /** \addtogroup hal_gpioirq_tests */
19 /** @{*/
20 
21 #ifndef MBED_FPGA_GPIO_IRQ_TEST_H
22 #define MBED_FPGA_GPIO_IRQ_TEST_H
23 
24 #if DEVICE_INTERRUPTIN
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
30 /** Test that the GPIO IRQ can be initialized/de-initialized using all possible
31  * GPIO IRQ pins.
32  *
33  * Given board provides GPIO IRQ support.
34  * When GPIO IRQ is initialized (and then de-initialized) using valid GPIO IRQ pin.
35  * Then the operation is successfull.
36  *
37  */
38 void fpga_gpio_irq_test(PinName pin);
39 
40 /** Test that the gpio interrupt is generated correctly.
41  *
42  * Given board provides interrupt-in feature.
43  * When gpio interrupt is configured to fire on rasing/falling/both edge(s).
44  * Then on rasing/falling/any edge registered interrupt handler is called.
45  *
46  */
47 void fpga_gpio_irq_init_free_test(PinName pin);
48 
49 /**@}*/
50 
51 #ifdef __cplusplus
52 }
53 #endif
54 
55 #endif
56 
57 #endif
58 /**@}*/
fpga_gpio_irq_test
void fpga_gpio_irq_test(PinName pin)
Test that the GPIO IRQ can be initialized/de-initialized using all possible GPIO IRQ pins...
fpga_gpio_irq_init_free_test
void fpga_gpio_irq_init_free_test(PinName pin)
Test that the gpio interrupt is generated correctly.
Important Information for this Arm website

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.