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shci.h
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1 /**
2  ******************************************************************************
3  * @file shci.h
4  * @author MCD Application Team
5  * @brief HCI command for the system channel
6  ******************************************************************************
7  * @attention
8  *
9  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
10  * All rights reserved.</center></h2>
11  *
12  * This software component is licensed by ST under BSD 3-Clause license,
13  * the "License"; You may not use this file except in compliance with the
14  * License. You may obtain a copy of the License at:
15  * opensource.org/licenses/BSD-3-Clause
16  *
17  ******************************************************************************
18  */
19 
20 
21 /* Define to prevent recursive inclusion -------------------------------------*/
22 #ifndef __SHCI_H
23 #define __SHCI_H
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
29  /* Includes ------------------------------------------------------------------*/
30 #include "mbox_def.h" /* Requested to expose the MB_WirelessFwInfoTable_t structure */
31 
32  /* Exported types ------------------------------------------------------------*/
33 
34  /* SYSTEM EVENT */
35  typedef enum
36  {
37  WIRELESS_FW_RUNNING = 0x00,
38  FUS_FW_RUNNING = 0x01,
39  } SHCI_SysEvt_Ready_Rsp_t;
40 
41  /* ERROR CODES
42  *
43  * These error codes are detected on CPU2 side and are send back to the CPU1 via a system
44  * notification message. It is up to the application running on CPU1 to manage these errors
45  *
46  * These errors can be generated by all layers (low level driver, stack, framework infrastructure, etc..)
47  */
48  typedef enum
49  {
50  ERR_BLE_INIT = 0, /* This event is currently not reported by the CPU2 */
51  ERR_THREAD_LLD_FATAL_ERROR = 125, /* The LLD driver used on 802_15_4 detected a fatal error */
52  ERR_THREAD_UNKNOWN_CMD = 126, /* The command send by the CPU1 to control the Thread stack is unknown */
53  ERR_ZIGBEE_UNKNOWN_CMD = 200, /* The command send by the CPU1 to control the Zigbee stack is unknown */
54  } SCHI_SystemErrCode_t;
55 
56 #define SHCI_EVTCODE ( 0xFF )
57 #define SHCI_SUB_EVT_CODE_BASE ( 0x9200 )
58 
59  /**
60  * THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU1 DEFINITION
61  */
62  typedef enum
63  {
64  SHCI_SUB_EVT_CODE_READY = SHCI_SUB_EVT_CODE_BASE,
65  SHCI_SUB_EVT_ERROR_NOTIF,
66  SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE,
67  SHCI_SUB_EVT_THREAD_NVM_RAM_UPDATE,
68  SHCI_SUB_EVT_NVM_START_WRITE,
69  SHCI_SUB_EVT_NVM_END_WRITE,
70  SHCI_SUB_EVT_NVM_START_ERASE,
71  SHCI_SUB_EVT_NVM_END_ERASE,
72  SHCI_SUB_EVT_CODE_CONCURRENT_802154_EVT,
73  } SHCI_SUB_EVT_CODE_t;
74 
75  /**
76  * SHCI_SUB_EVT_CODE_READY
77  * This notifies the CPU1 that the CPU2 is now ready to receive commands
78  * It reports as well which firmware is running on CPU2 : The wireless stack of the FUS (previously named RSS)
79  */
80  typedef PACKED_STRUCT{
81  SHCI_SysEvt_Ready_Rsp_t sysevt_ready_rsp;
82  } SHCI_C2_Ready_Evt_t;
83 
84  /**
85  * SHCI_SUB_EVT_ERROR_NOTIF
86  * This reports to the CPU1 some error form the CPU2
87  */
88  typedef PACKED_STRUCT{
89  SCHI_SystemErrCode_t errorCode;
90  } SHCI_C2_ErrorNotif_Evt_t;
91 
92  /**
93  * SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE
94  * This notifies the CPU1 which part of the BLE NVM RAM has been updated so that only the modified
95  * section could be written in Flash/NVM
96  * StartAddress : Start address of the section that has been modified
97  * Size : Size (in bytes) of the section that has been modified
98  */
99  typedef PACKED_STRUCT{
100  uint32_t StartAddress;
101  uint32_t Size;
102  } SHCI_C2_BleNvmRamUpdate_Evt_t;
103 
104  /**
105  * SHCI_SUB_EVT_THREAD_NVM_RAM_UPDATE
106  * This notifies the CPU1 which part of the OT NVM RAM has been updated so that only the modified
107  * section could be written in Flash/NVM
108  * StartAddress : Start address of the section that has been modified
109  * Size : Size (in bytes) of the section that has been modified
110  */
111  typedef PACKED_STRUCT{
112  uint32_t StartAddress;
113  uint32_t Size;
114  } SHCI_C2_ThreadNvmRamUpdate_Evt_t;
115 
116  /**
117  * SHCI_SUB_EVT_NVM_START_WRITE
118  * This notifies the CPU1 that the CPU2 has started a write procedure in Flash
119  * NumberOfWords : The number of 64bits data the CPU2 needs to write in Flash.
120  * For each 64bits data, the algorithm as described in AN5289 is executed.
121  * When this number is reported to 0, it means the Number of 64bits to be written
122  * was unknown when the procedure has started.
123  * When all data are written, the SHCI_SUB_EVT_NVM_END_WRITE event is reported
124  */
125  typedef PACKED_STRUCT{
126  uint32_t NumberOfWords;
127  } SHCI_C2_NvmStartWrite_Evt_t;
128 
129  /**
130  * SHCI_SUB_EVT_NVM_END_WRITE
131  * This notifies the CPU1 that the CPU2 has written all expected data in Flash
132  */
133 
134  /**
135  * SHCI_SUB_EVT_NVM_START_ERASE
136  * This notifies the CPU1 that the CPU2 has started a erase procedure in Flash
137  * NumberOfSectors : The number of sectors the CPU2 needs to erase in Flash.
138  * For each sector, the algorithm as described in AN5289 is executed.
139  * When this number is reported to 0, it means the Number of sectors to be erased
140  * was unknown when the procedure has started.
141  * When all sectors are erased, the SHCI_SUB_EVT_NVM_END_ERASE event is reported
142  */
143  typedef PACKED_STRUCT{
144  uint32_t NumberOfSectors;
145  } SHCI_C2_NvmStartErase_Evt_t;
146 
147  /**
148  * SHCI_SUB_EVT_NVM_END_ERASE
149  * This notifies the CPU1 that the CPU2 has erased all expected flash sectors
150  */
151 
152  /* SYSTEM COMMAND */
153  typedef PACKED_STRUCT
154  {
155  /**
156  * MetaData holds :
157  * 2*32bits for chaining list
158  * 1*32bits with BLE header (type + Opcode + Length)
159  */
160  uint32_t MetaData[3];
161  } SHCI_Header_t;
162 
163  typedef enum
164  {
165  SHCI_Success = 0x00,
166  SHCI_UNKNOWN_CMD = 0x01,
167  SHCI_ERR_UNSUPPORTED_FEATURE = 0x11,
168  SHCI_ERR_INVALID_HCI_CMD_PARAMS = 0x12,
169  SHCI_ERR_INVALID_PARAMS = 0x42,
170  SHCI_FUS_CMD_NOT_SUPPORTED = 0xFF,
171  } SHCI_CmdStatus_t;
172 
173  typedef enum
174  {
175  SHCI_8BITS = 0x01,
176  SHCI_16BITS = 0x02,
177  SHCI_32BITS = 0x04,
178  } SHCI_Busw_t;
179 
180 #define SHCI_OGF ( 0x3F )
181 #define SHCI_OCF_BASE ( 0x50 )
182 
183  /**
184  * THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU2 DEFINITION
185  */
186  typedef enum
187  {
188  SHCI_OCF_C2_RESERVED1 = SHCI_OCF_BASE,
189  SHCI_OCF_C2_RESERVED2,
190  SHCI_OCF_C2_FUS_GET_STATE,
191  SHCI_OCF_C2_FUS_RESERVED1,
192  SHCI_OCF_C2_FUS_FW_UPGRADE,
193  SHCI_OCF_C2_FUS_FW_DELETE,
194  SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY,
195  SHCI_OCF_C2_FUS_LOCK_AUTH_KEY,
196  SHCI_OCF_C2_FUS_STORE_USR_KEY,
197  SHCI_OCF_C2_FUS_LOAD_USR_KEY,
198  SHCI_OCF_C2_FUS_START_WS,
199  SHCI_OCF_C2_FUS_RESERVED2,
200  SHCI_OCF_C2_FUS_RESERVED3,
201  SHCI_OCF_C2_FUS_LOCK_USR_KEY,
202  SHCI_OCF_C2_FUS_UNLOAD_USR_KEY,
203  SHCI_OCF_C2_FUS_ACTIVATE_ANTIROLLBACK,
204  SHCI_OCF_C2_FUS_RESERVED7,
205  SHCI_OCF_C2_FUS_RESERVED8,
206  SHCI_OCF_C2_FUS_RESERVED9,
207  SHCI_OCF_C2_FUS_RESERVED10,
208  SHCI_OCF_C2_FUS_RESERVED11,
209  SHCI_OCF_C2_FUS_RESERVED12,
210  SHCI_OCF_C2_BLE_INIT,
211  SHCI_OCF_C2_THREAD_INIT,
212  SHCI_OCF_C2_DEBUG_INIT,
213  SHCI_OCF_C2_FLASH_ERASE_ACTIVITY,
214  SHCI_OCF_C2_CONCURRENT_SET_MODE,
215  SHCI_OCF_C2_FLASH_STORE_DATA,
216  SHCI_OCF_C2_FLASH_ERASE_DATA,
217  SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER,
218  SHCI_OCF_C2_MAC_802_15_4_INIT,
219  SHCI_OCF_C2_REINIT,
220  SHCI_OCF_C2_ZIGBEE_INIT,
221  SHCI_OCF_C2_LLD_TESTS_INIT,
222  SHCI_OCF_C2_EXTPA_CONFIG,
223  SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL,
224  SHCI_OCF_C2_BLE_LLD_INIT,
225  SHCI_OCF_C2_CONFIG,
226  SHCI_OCF_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME,
227  SHCI_OCF_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION,
228  SHCI_OCF_C2_802_15_4_DEINIT,
229  } SHCI_OCF_t;
230 
231 #define SHCI_OPCODE_C2_FUS_GET_STATE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_STATE)
232 /** No command parameters */
233 /** Response parameters*/
234 /** It responds a 1 byte value holding FUS State error code when the FUS State value is 0xFF (FUS_STATE_VALUE_ERROR) */
235  typedef enum
236  {
237  FUS_STATE_ERROR_NO_ERROR = 0x00,
238  FUS_STATE_ERROR_IMG_NOT_FOUND = 0x01,
239  FUS_STATE_ERROR_IMG_CORRUPT = 0x02,
240  FUS_STATE_ERROR_IMG_NOT_AUTHENTIC = 0x03,
241  FUS_STATE_ERROR_IMG_NOT_ENOUGH_SPACE = 0x04,
242  FUS_STATE_ERROR_IMAGE_USRABORT = 0x05,
243  FUS_STATE_ERROR_IMAGE_ERSERROR = 0x06,
244  FUS_STATE_ERROR_IMAGE_WRTERROR = 0x07,
245  FUS_STATE_ERROR_AUTH_TAG_ST_NOTFOUND = 0x08,
246  FUS_STATE_ERROR_AUTH_TAG_CUST_NOTFOUND = 0x09,
247  FUS_STATE_ERROR_AUTH_KEY_LOCKED = 0x0A,
248  FUS_STATE_ERROR_FW_ROLLBACK_ERROR = 0x11,
249  FUS_STATE_ERROR_STATE_NOT_RUNNING = 0xFE,
250  FUS_STATE_ERROR_ERR_UNKNOWN = 0xFF,
251  } SHCI_FUS_GetState_ErrorCode_t;
252 
253  enum
254  {
255  FUS_STATE_VALUE_IDLE = 0x00,
256  FUS_STATE_VALUE_FW_UPGRD_ONGOING = 0x10,
257  FUS_STATE_VALUE_FW_UPGRD_ONGOING_END = 0x1F, /* All values between 0x10 and 0x1F has the same meaning */
258  FUS_STATE_VALUE_FUS_UPGRD_ONGOING = 0x20,
259  FUS_STATE_VALUE_FUS_UPGRD_ONGOING_END = 0x2F, /* All values between 0x20 and 0x2F has the same meaning */
260  FUS_STATE_VALUE_SERVICE_ONGOING = 0x30,
261  FUS_STATE_VALUE_SERVICE_ONGOING_END = 0x3F, /* All values between 0x30 and 0x3F has the same meaning */
262  FUS_STATE_VALUE_ERROR = 0xFF,
263  };
264 
265 #define SHCI_OPCODE_C2_FUS_RESERVED1 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED1)
266 /** No command parameters */
267 /** No response parameters*/
268 
269 #define SHCI_OPCODE_C2_FUS_FW_UPGRADE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_UPGRADE)
270  /** No structure for command parameters */
271  /** No response parameters*/
272 
273 #define SHCI_OPCODE_C2_FUS_FW_DELETE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_DELETE)
274 /** No command parameters */
275 /** No response parameters*/
276 
277 #define SHCI_OPCODE_C2_FUS_UPDATE_AUTH_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY)
278  typedef PACKED_STRUCT{
279  uint8_t KeySize;
280  uint8_t KeyData[64];
281  } SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t;
282 
283  /** No response parameters*/
284 
285 #define SHCI_OPCODE_C2_FUS_LOCK_AUTH_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_AUTH_KEY)
286 /** No command parameters */
287 /** No response parameters*/
288 
289 #define SHCI_OPCODE_C2_FUS_STORE_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_STORE_USR_KEY)
290  /** Command parameters */
291  /* List of supported key type */
292  enum
293  {
294  KEYTYPE_NONE = 0x00,
295  KEYTYPE_SIMPLE = 0x01,
296  KEYTYPE_MASTER = 0x02,
297  KEYTYPE_ENCRYPTED = 0x03,
298  };
299 
300  /* List of supported key size */
301  enum
302  {
303  KEYSIZE_16 = 16,
304  KEYSIZE_32 = 32,
305  };
306 
307  typedef PACKED_STRUCT{
308  uint8_t KeyType;
309  uint8_t KeySize;
310  uint8_t KeyData[32 + 12];
311  } SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t;
312 
313  /** Response parameters*/
314  /** It responds a 1 byte value holding the index given for the stored key */
315 
316 #define SHCI_OPCODE_C2_FUS_LOAD_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOAD_USR_KEY)
317  /** Command parameters */
318  /** 1 byte holding the key index value */
319 
320  /** No response parameters*/
321 
322 #define SHCI_OPCODE_C2_FUS_START_WS (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_START_WS)
323 /** No command parameters */
324 /** No response parameters*/
325 
326 #define SHCI_OPCODE_C2_FUS_RESERVED2 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED2)
327 /** No command parameters */
328 /** No response parameters*/
329 
330 #define SHCI_OPCODE_C2_FUS_RESERVED3 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED3)
331 /** No command parameters */
332 /** No response parameters*/
333 
334 #define SHCI_OPCODE_C2_FUS_LOCK_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_USR_KEY)
335  /** Command parameters */
336  /** 1 byte holding the key index value */
337 
338  /** No response parameters*/
339 
340 #define SHCI_OPCODE_C2_FUS_UNLOAD_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UNLOAD_USR_KEY)
341 /** No command parameters */
342 /** 1 byte holding the key index value */
343 
344 #define SHCI_OPCODE_C2_FUS_ACTIVATE_ANTIROLLBACK (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_ACTIVATE_ANTIROLLBACK)
345 /** No command parameters */
346 /** No response parameters*/
347 
348 #define SHCI_OPCODE_C2_FUS_RESERVED7 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED7)
349 /** No command parameters */
350 /** No response parameters*/
351 
352 #define SHCI_OPCODE_C2_FUS_RESERVED8 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED8)
353 /** No command parameters */
354 /** No response parameters*/
355 
356 #define SHCI_OPCODE_C2_FUS_RESERVED9 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED9)
357 /** No command parameters */
358 /** No response parameters*/
359 
360 #define SHCI_OPCODE_C2_FUS_RESERVED10 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED10)
361 /** No command parameters */
362 /** No response parameters*/
363 
364 #define SHCI_OPCODE_C2_FUS_RESERVED11 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED11)
365 /** No command parameters */
366 /** No response parameters*/
367 
368 #define SHCI_OPCODE_C2_FUS_RESERVED12 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED12)
369 /** No command parameters */
370 /** No response parameters*/
371 
372 #define SHCI_OPCODE_C2_BLE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_INIT)
373  /** THE ORDER SHALL NOT BE CHANGED */
374  typedef PACKED_STRUCT{
375  uint8_t* pBleBufferAddress; /**< NOT USED - shall be set to 0 */
376  uint32_t BleBufferSize; /**< NOT USED - shall be set to 0 */
377 
378  /**
379  * NumAttrRecord
380  * Maximum number of attribute records related to all the required characteristics (excluding the services)
381  * that can be stored in the GATT database, for the specific BLE user application.
382  * For each characteristic, the number of attribute records goes from two to five depending on the characteristic properties:
383  * - minimum of two (one for declaration and one for the value)
384  * - add one more record for each additional property: notify or indicate, broadcast, extended property.
385  * The total calculated value must be increased by 9, due to the records related to the standard attribute profile and
386  * GAP service characteristics, and automatically added when initializing GATT and GAP layers
387  * - Min value: <number of user attributes> + 9
388  * - Max value: depending on the GATT database defined by user application
389  */
390  uint16_t NumAttrRecord;
391 
392  /**
393  * NumAttrServ
394  * Defines the maximum number of services that can be stored in the GATT database. Note that the GAP and GATT services
395  * are automatically added at initialization so this parameter must be the number of user services increased by two.
396  * - Min value: <number of user service> + 2
397  * - Max value: depending GATT database defined by user application
398  */
399  uint16_t NumAttrServ;
400 
401  /**
402  * AttrValueArrSize
403  * NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure )
404  *
405  * Size of the storage area for the attribute values.
406  * Each characteristic contributes to the attrValueArrSize value as follows:
407  * - Characteristic value length plus:
408  * + 5 bytes if characteristic UUID is 16 bits
409  * + 19 bytes if characteristic UUID is 128 bits
410  * + 2 bytes if characteristic has a server configuration descriptor
411  * + 2 bytes * NumOfLinks if the characteristic has a client configuration descriptor
412  * + 2 bytes if the characteristic has extended properties
413  * Each descriptor contributes to the attrValueArrSize value as follows:
414  * - Descriptor length
415  */
416  uint16_t AttrValueArrSize;
417 
418  /**
419  * NumOfLinks
420  * Maximum number of BLE links supported
421  * - Min value: 1
422  * - Max value: 8
423  */
424  uint8_t NumOfLinks;
425 
426  /**
427  * ExtendedPacketLengthEnable
428  * Disable/enable the extended packet length BLE 5.0 feature
429  * - Disable: 0
430  * - Enable: 1
431  */
432  uint8_t ExtendedPacketLengthEnable;
433 
434  /**
435  * PrWriteListSize
436  * NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure )
437  *
438  * Maximum number of supported prepare write request
439  * - Min value: given by the macro DEFAULT_PREP_WRITE_LIST_SIZE
440  * - Max value: a value higher than the minimum required can be specified, but it is not recommended
441  */
442  uint8_t PrWriteListSize;
443 
444  /**
445  * MblockCount
446  * NOTE: This parameter is overwritten by the CPU2 with an hardcoded optimal value when the parameter "Options" is set to "LL_only"
447  * ( see Options description in that structure )
448  *
449  * Number of allocated memory blocks for the BLE stack
450  * - Min value: given by the macro MBLOCKS_CALC
451  * - Max value: a higher value can improve data throughput performance, but uses more memory
452  */
453  uint8_t MblockCount;
454 
455  /**
456  * AttMtu
457  * NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure )
458  *
459  * Maximum ATT MTU size supported
460  * - Min value: 23
461  * - Max value: 512
462  */
463  uint16_t AttMtu;
464 
465  /**
466  * SlaveSca
467  * The sleep clock accuracy (ppm value) that used in BLE connected slave mode to calculate the window widening
468  * (in combination with the sleep clock accuracy sent by master in CONNECT_REQ PDU),
469  * refer to BLE 5.0 specifications - Vol 6 - Part B - chap 4.5.7 and 4.2.2
470  * - Min value: 0
471  * - Max value: 500 (worst possible admitted by specification)
472  */
473  uint16_t SlaveSca;
474 
475  /**
476  * MasterSca
477  * The sleep clock accuracy handled in master mode. It is used to determine the connection and advertising events timing.
478  * It is transmitted to the slave in CONNEC_REQ PDU used by the slave to calculate the window widening,
479  * see SlaveSca and Bluetooth Core Specification v5.0 Vol 6 - Part B - chap 4.5.7 and 4.2.2
480  * Possible values:
481  * - 251 ppm to 500 ppm: 0
482  * - 151 ppm to 250 ppm: 1
483  * - 101 ppm to 150 ppm: 2
484  * - 76 ppm to 100 ppm: 3
485  * - 51 ppm to 75 ppm: 4
486  * - 31 ppm to 50 ppm: 5
487  * - 21 ppm to 30 ppm: 6
488  * - 0 ppm to 20 ppm: 7
489  */
490  uint8_t MasterSca;
491 
492  /**
493  * LsSource
494  * Source for the 32 kHz slow speed clock.
495  * - External crystal LSE: 0 - No calibration
496  * - Others:1 - As the accuracy of this oscillator can vary depending upon external conditions (temperature),
497  * it is calibrated every second to ensure correct behavior of timing sensitive BLE operations
498  */
499  uint8_t LsSource;
500 
501  /**
502  * MaxConnEventLength
503  * This parameter determines the maximum duration of a slave connection event. When this duration is reached the slave closes
504  * the current connections event (whatever is the CE_length parameter specified by the master in HCI_CREATE_CONNECTION HCI command),
505  * expressed in units of 625/256 us (~2.44 us)
506  * - Min value: 0 (if 0 is specified, the master and slave perform only a single TX-RX exchange per connection event)
507  * - Max value: 1638400 (4000 ms). A higher value can be specified (max 0xFFFFFFFF) but results in a maximum connection time
508  * of 4000 ms as specified. In this case the parameter is not applied, and the predicted CE length calculated on slave is not shortened
509  */
510  uint32_t MaxConnEventLength;
511 
512  /**
513  * HsStartupTime
514  * Startup time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us).
515  * - Min value: 0
516  * - Max value: 820 (~2 ms). A higher value can be specified, but the value that implemented in stack is forced to ~2 ms
517  */
518  uint16_t HsStartupTime;
519 
520  /**
521  * ViterbiEnable
522  * Viterbi implementation in BLE LL reception.
523  * - 0: Enable
524  * - 1: Disable
525  */
526  uint8_t ViterbiEnable;
527 
528  /**
529  * Options flags
530  * - bit 0: 1: LL only 0: LL + host
531  * - bit 1: 1: no service change desc. 0: with service change desc.
532  * - bit 2: 1: device name Read-Only 0: device name R/W
533  * - bit 7: 1: LE Power Class 1 0: LE Power Classe 2-3
534  * - other bits: reserved ( shall be set to 0)
535  */
536  uint8_t Options;
537 
538  /**
539  * HwVersion
540  * Reserved for future use - shall be set to 0
541  */
542  uint8_t HwVersion;
543 
544  /**
545  * Maximum number of connection-oriented channels in initiator mode.
546  * Range: 0 .. 64
547  */
548  uint8_t max_coc_initiator_nbr;
549 
550  /**
551  * Minimum transmit power in dBm supported by the Controller.
552  * Range: -127 .. 20
553  */
554  int8_t min_tx_power;
555 
556  /**
557  * Maximum transmit power in dBm supported by the Controller.
558  * Range: -127 .. 20
559  */
560  int8_t max_tx_power;
561  } SHCI_C2_Ble_Init_Cmd_Param_t;
562 
563  typedef PACKED_STRUCT{
564  SHCI_Header_t Header; /** Does not need to be initialized by the user */
565  SHCI_C2_Ble_Init_Cmd_Param_t Param;
566  } SHCI_C2_Ble_Init_Cmd_Packet_t;
567 
568  /**
569  * Options
570  * Each definition below may be added together to build the Options value
571  * WARNING : Only one definition per bit shall be added to build the Options value
572  */
573 #define SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY (1<<0)
574 #define SHCI_C2_BLE_INIT_OPTIONS_LL_HOST (0<<0)
575 
576 #define SHCI_C2_BLE_INIT_OPTIONS_NO_SVC_CHANGE_DESC (1<<1)
577 #define SHCI_C2_BLE_INIT_OPTIONS_WITH_SVC_CHANGE_DESC (0<<1)
578 
579 #define SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RO (1<<2)
580 #define SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RW (0<<2)
581 
582 #define SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_1 (1<<7)
583 #define SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3 (0<<7)
584 
585 
586 #define SHCI_OPCODE_C2_THREAD_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_THREAD_INIT)
587 /** No command parameters */
588 /** No response parameters*/
589 
590 #define SHCI_OPCODE_C2_DEBUG_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_DEBUG_INIT)
591  /** Command parameters */
592  typedef PACKED_STRUCT
593  {
594  uint8_t thread_config;
595  uint8_t ble_config;
596  uint8_t mac_802_15_4_config;
597  uint8_t zigbee_config;
598  } SHCI_C2_DEBUG_TracesConfig_t;
599 
600  typedef PACKED_STRUCT
601  {
602  uint8_t ble_dtb_cfg;
603  uint8_t reserved[3];
604  } SHCI_C2_DEBUG_GeneralConfig_t;
605 
606  typedef PACKED_STRUCT{
607  uint8_t *pGpioConfig;
608  uint8_t *pTracesConfig;
609  uint8_t *pGeneralConfig;
610  uint8_t GpioConfigSize;
611  uint8_t TracesConfigSize;
612  uint8_t GeneralConfigSize;
613  } SHCI_C2_DEBUG_init_Cmd_Param_t;
614 
615  typedef PACKED_STRUCT{
616  SHCI_Header_t Header; /** Does not need to be initialized by the user */
617  SHCI_C2_DEBUG_init_Cmd_Param_t Param;
618  } SHCI_C2_DEBUG_Init_Cmd_Packet_t;
619  /** No response parameters*/
620 
621 #define SHCI_OPCODE_C2_FLASH_ERASE_ACTIVITY (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_ACTIVITY)
622  /** Command parameters */
623  typedef enum
624  {
625  ERASE_ACTIVITY_OFF = 0x00,
626  ERASE_ACTIVITY_ON = 0x01,
627  } SHCI_EraseActivity_t;
628 
629  /** No response parameters*/
630 
631 #define SHCI_OPCODE_C2_CONCURRENT_SET_MODE (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_SET_MODE)
632 /** command parameters */
633  typedef enum
634  {
635  BLE_ENABLE,
636  THREAD_ENABLE,
637  ZIGBEE_ENABLE,
638  MAC_ENABLE,
639  } SHCI_C2_CONCURRENT_Mode_Param_t;
640  /** No response parameters*/
641 
642 #define SHCI_OPCODE_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME)
643 /** command parameters */
644  typedef PACKED_STRUCT
645  {
646  uint32_t relative_time;
647  } SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t;
648  /** No response parameters*/
649 
650 #define SHCI_OPCODE_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION)
651  /** No command parameters */
652  /** No response parameters*/
653 
654 #define SHCI_OPCODE_C2_FLASH_STORE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_STORE_DATA)
655 #define SHCI_OPCODE_C2_FLASH_ERASE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_DATA)
656 /** command parameters */
657  typedef enum
658  {
659  BLE_IP,
660  THREAD_IP,
661  ZIGBEE_IP,
662  } SHCI_C2_FLASH_Ip_t;
663  /** No response parameters*/
664 
665 #define SHCI_OPCODE_C2_RADIO_ALLOW_LOW_POWER (( SHCI_OGF << 10) + SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER)
666 
667 #define SHCI_OPCODE_C2_MAC_802_15_4_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_MAC_802_15_4_INIT)
668 
669 #define SHCI_OPCODE_C2_REINIT (( SHCI_OGF << 10) + SHCI_OCF_C2_REINIT)
670 
671 #define SHCI_OPCODE_C2_ZIGBEE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_ZIGBEE_INIT)
672 
673 #define SHCI_OPCODE_C2_LLD_TESTS_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_TESTS_INIT)
674 
675 #define SHCI_OPCODE_C2_BLE_LLD_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_LLD_INIT)
676 
677 #define SHCI_OPCODE_C2_EXTPA_CONFIG (( SHCI_OGF << 10) + SHCI_OCF_C2_EXTPA_CONFIG)
678  /** Command parameters */
679  enum
680  {
681  EXT_PA_ENABLED_LOW,
682  EXT_PA_ENABLED_HIGH,
683  }/* gpio_polarity */;
684 
685  enum
686  {
687  EXT_PA_DISABLED,
688  EXT_PA_ENABLED,
689  }/* gpio_status */;
690 
691  typedef PACKED_STRUCT{
692  uint32_t gpio_port;
693  uint16_t gpio_pin_number;
694  uint8_t gpio_polarity;
695  uint8_t gpio_status;
696  } SHCI_C2_EXTPA_CONFIG_Cmd_Param_t;
697 
698  /** No response parameters*/
699 
700 #define SHCI_OPCODE_C2_SET_FLASH_ACTIVITY_CONTROL (( SHCI_OGF << 10) + SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL)
701  /** Command parameters */
702  typedef enum
703  {
704  FLASH_ACTIVITY_CONTROL_PES,
705  FLASH_ACTIVITY_CONTROL_SEM7,
706  }SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t;
707 
708  /** No response parameters*/
709 
710 #define SHCI_OPCODE_C2_CONFIG (( SHCI_OGF << 10) + SHCI_OCF_C2_CONFIG)
711  /** Command parameters */
712  typedef PACKED_STRUCT{
713  uint8_t PayloadCmdSize;
714  uint8_t Config1;
715  uint8_t EvtMask1;
716  uint8_t Spare1;
717  uint32_t BleNvmRamAddress;
718  uint32_t ThreadNvmRamAddress;
719  } SHCI_C2_CONFIG_Cmd_Param_t;
720 
721 #define SHCI_OPCODE_C2_802_15_4_DEINIT (( SHCI_OGF << 10) + SHCI_OCF_C2_802_15_4_DEINIT)
722 
723 /**
724  * PayloadCmdSize
725  * Value that shall be used
726  */
727 #define SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE (sizeof(SHCI_C2_CONFIG_Cmd_Param_t) - 1)
728 
729 /**
730  * Config1
731  * Each definition below may be added together to build the Config1 value
732  * WARNING : Only one definition per bit shall be added to build the Config1 value
733  */
734 #define SHCI_C2_CONFIG_CONFIG1_BIT0_BLE_NVM_DATA_TO_INTERNAL_FLASH (0<<0)
735 #define SHCI_C2_CONFIG_CONFIG1_BIT0_BLE_NVM_DATA_TO_SRAM (1<<0)
736 #define SHCI_C2_CONFIG_CONFIG1_BIT1_THREAD_NVM_DATA_TO_INTERNAL_FLASH (0<<1)
737 #define SHCI_C2_CONFIG_CONFIG1_BIT1_THREAD_NVM_DATA_TO_SRAM (1<<1)
738 
739 /**
740  * EvtMask1
741  * Each definition below may be added together to build the EvtMask1 value
742  */
743 #define SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE (1<<0)
744 #define SHCI_C2_CONFIG_EVTMASK1_BIT1_BLE_NVM_RAM_UPDATE_ENABLE (1<<1)
745 #define SHCI_C2_CONFIG_EVTMASK1_BIT2_THREAD_NVM_RAM_UPDATE_ENABLE (1<<2)
746 #define SHCI_C2_CONFIG_EVTMASK1_BIT3_NVM_START_WRITE_ENABLE (1<<3)
747 #define SHCI_C2_CONFIG_EVTMASK1_BIT4_NVM_END_WRITE_ENABLE (1<<4)
748 #define SHCI_C2_CONFIG_EVTMASK1_BIT5_NVM_START_ERASE_ENABLE (1<<5)
749 #define SHCI_C2_CONFIG_EVTMASK1_BIT6_NVM_END_ERASE_ENABLE (1<<6)
750 
751 /**
752  * BleNvmRamAddress
753  * The buffer shall have a size of BLE_NVM_SRAM_SIZE number of 32bits
754  * The buffer shall be allocated in SRAM2
755  */
756 #define BLE_NVM_SRAM_SIZE (507)
757 
758 /**
759  * ThreadNvmRamAddress
760  * The buffer shall have a size of THREAD_NVM_SRAM_SIZE number of 32bits
761  * The buffer shall be allocated in SRAM2
762  */
763 #define THREAD_NVM_SRAM_SIZE (1016)
764 
765 
766  /** No response parameters*/
767 
768  /* Exported type --------------------------------------------------------*/
769 #define FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD (0xA94656B9)
770 
771 /*
772  * At startup, the informations relative to the wireless binary are stored in RAM trough a structure defined by
773  * MB_WirelessFwInfoTable_t.This structure contains 4 fields (Version,MemorySize, Stack_info and a reserved part)
774  * each of those coded on 32 bits as shown on the table below:
775  *
776  *
777  * |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |
778  * -------------------------------------------------------------------------------------------------
779  * Version | Major version | Minor version | Sub version | Branch |ReleaseType|
780  * -------------------------------------------------------------------------------------------------
781  * MemorySize | SRAM2B (kB) | SRAM2A (kB) | SRAM1 (kB) | FLASH (4kb) |
782  * -------------------------------------------------------------------------------------------------
783  * Info stack | Reserved | Reserved | Reserved | Type (MAC,Thread,BLE) |
784  * -------------------------------------------------------------------------------------------------
785  * Reserved | Reserved | Reserved | Reserved | Reserved |
786  * -------------------------------------------------------------------------------------------------
787  *
788  */
789 
790 /* Field Version */
791 #define INFO_VERSION_MAJOR_OFFSET 24
792 #define INFO_VERSION_MAJOR_MASK 0xff000000
793 #define INFO_VERSION_MINOR_OFFSET 16
794 #define INFO_VERSION_MINOR_MASK 0x00ff0000
795 #define INFO_VERSION_SUB_OFFSET 8
796 #define INFO_VERSION_SUB_MASK 0x0000ff00
797 #define INFO_VERSION_BRANCH_OFFSET 4
798 #define INFO_VERSION_BRANCH_MASK 0x0000000f0
799 #define INFO_VERSION_TYPE_OFFSET 0
800 #define INFO_VERSION_TYPE_MASK 0x00000000f
801 
802 #define INFO_VERSION_TYPE_RELEASE 1
803 
804 /* Field Memory */
805 #define INFO_SIZE_SRAM2B_OFFSET 24
806 #define INFO_SIZE_SRAM2B_MASK 0xff000000
807 #define INFO_SIZE_SRAM2A_OFFSET 16
808 #define INFO_SIZE_SRAM2A_MASK 0x00ff0000
809 #define INFO_SIZE_SRAM1_OFFSET 8
810 #define INFO_SIZE_SRAM1_MASK 0x0000ff00
811 #define INFO_SIZE_FLASH_OFFSET 0
812 #define INFO_SIZE_FLASH_MASK 0x000000ff
813 
814 /* Field stack information */
815 #define INFO_STACK_TYPE_OFFSET 0
816 #define INFO_STACK_TYPE_MASK 0x000000ff
817 #define INFO_STACK_TYPE_NONE 0
818 
819 #define INFO_STACK_TYPE_BLE_FULL 0x01
820 #define INFO_STACK_TYPE_BLE_HCI 0x02
821 #define INFO_STACK_TYPE_BLE_LIGHT 0x03
822 #define INFO_STACK_TYPE_BLE_BEACON 0x04
823 #define INFO_STACK_TYPE_THREAD_FTD 0x10
824 #define INFO_STACK_TYPE_THREAD_MTD 0x11
825 #define INFO_STACK_TYPE_ZIGBEE_FFD 0x30
826 #define INFO_STACK_TYPE_ZIGBEE_RFD 0x31
827 #define INFO_STACK_TYPE_MAC 0x40
828 #define INFO_STACK_TYPE_BLE_THREAD_FTD_STATIC 0x50
829 #define INFO_STACK_TYPE_BLE_THREAD_FTD_DYAMIC 0x51
830 #define INFO_STACK_TYPE_802154_LLD_TESTS 0x60
831 #define INFO_STACK_TYPE_802154_PHY_VALID 0x61
832 #define INFO_STACK_TYPE_BLE_PHY_VALID 0x62
833 #define INFO_STACK_TYPE_BLE_LLD_TESTS 0x63
834 #define INFO_STACK_TYPE_BLE_RLV 0x64
835 #define INFO_STACK_TYPE_802154_RLV 0x65
836 #define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_STATIC 0x70
837 #define INFO_STACK_TYPE_BLE_ZIGBEE_RFD_STATIC 0x71
838 #define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_DYNAMIC 0x78
839 #define INFO_STACK_TYPE_BLE_ZIGBEE_RFD_DYNAMIC 0x79
840 #define INFO_STACK_TYPE_RLV 0x80
841 #define INFO_STACK_TYPE_BLE_MAC_STATIC 0x90
842 
843 typedef struct {
844 /**
845  * Wireless Info
846  */
847  uint8_t VersionMajor;
848  uint8_t VersionMinor;
849  uint8_t VersionSub;
850  uint8_t VersionBranch;
851  uint8_t VersionReleaseType;
852  uint8_t MemorySizeSram2B; /*< Multiple of 1K */
853  uint8_t MemorySizeSram2A; /*< Multiple of 1K */
854  uint8_t MemorySizeSram1; /*< Multiple of 1K */
855  uint8_t MemorySizeFlash; /*< Multiple of 4K */
856  uint8_t StackType;
857 /**
858  * Fus Info
859  */
860  uint8_t FusVersionMajor;
861  uint8_t FusVersionMinor;
862  uint8_t FusVersionSub;
863  uint8_t FusMemorySizeSram2B; /*< Multiple of 1K */
864  uint8_t FusMemorySizeSram2A; /*< Multiple of 1K */
865  uint8_t FusMemorySizeFlash; /*< Multiple of 4K */
866 }WirelessFwInfo_t;
867 
868 
869 /* Exported functions ------------------------------------------------------- */
870 
871  /**
872  * SHCI_C2_FUS_GetState
873  * @brief Read the FUS State
874  * If the user is not interested by the Error code response, a null value may
875  * be passed as parameter
876  *
877  * Note: This command is fully supported only by the FUS.
878  * When the wireless firmware receives that command, it responds SHCI_FUS_CMD_NOT_SUPPORTED the first time.
879  * When the wireless firmware receives that command a second time, it reboots the full device with the FUS running on CPU2
880  *
881  * @param p_rsp : return the error code when the FUS State Value = 0xFF
882  * @retval FUS State Values
883  */
884  uint8_t SHCI_C2_FUS_GetState( SHCI_FUS_GetState_ErrorCode_t *p_rsp );
885 
886  /**
887  * SHCI_C2_FUS_FwUpgrade
888  * @brief Request the FUS to install the CPU2 firmware update
889  * Note: This command is only supported by the FUS.
890  *
891  * @param fw_src_add: Address of the firmware image location
892  * @param fw_dest_add: Address of the firmware destination
893  * @retval Status
894  */
895  SHCI_CmdStatus_t SHCI_C2_FUS_FwUpgrade( uint32_t fw_src_add, uint32_t fw_dest_add );
896 
897  /**
898  * SHCI_C2_FUS_FwDelete
899  * @brief Delete the wireless stack on CPU2
900  * Note: This command is only supported by the FUS.
901  *
902  * @param None
903  * @retval Status
904  */
905  SHCI_CmdStatus_t SHCI_C2_FUS_FwDelete( void );
906 
907  /**
908  * SHCI_C2_FUS_UpdateAuthKey
909  * @brief Request the FUS to update the authentication key
910  * Note: This command is only supported by the FUS.
911  *
912  * @param pCmdPacket
913  * @retval Status
914  */
915  SHCI_CmdStatus_t SHCI_C2_FUS_UpdateAuthKey( SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t *pParam );
916 
917  /**
918  * SHCI_C2_FUS_LockAuthKey
919  * @brief Request the FUS to prevent any future update of the authentication key
920  * Note: This command is only supported by the FUS.
921  *
922  * @param None
923  * @retval Status
924  */
925  SHCI_CmdStatus_t SHCI_C2_FUS_LockAuthKey( void );
926 
927  /**
928  * SHCI_C2_FUS_StoreUsrKey
929  * @brief Request the FUS to store the user key
930  * Note: This command is supported by both the FUS and the wireless stack.
931  *
932  * @param pParam : command parameter
933  * @param p_key_index : Index allocated by the FUS to the stored key
934  *
935  * @retval Status
936  */
937  SHCI_CmdStatus_t SHCI_C2_FUS_StoreUsrKey( SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t *pParam, uint8_t *p_key_index );
938 
939  /**
940  * SHCI_C2_FUS_LoadUsrKey
941  * @brief Request the FUS to load the user key into the AES
942  * Note: This command is supported by both the FUS and the wireless stack.
943  *
944  * @param key_index : index of the user key to load in AES1
945  * @retval Status
946  */
947  SHCI_CmdStatus_t SHCI_C2_FUS_LoadUsrKey( uint8_t key_index );
948 
949  /**
950  * SHCI_C2_FUS_StartWs
951  * @brief Request the FUS to reboot on the wireless stack
952  * Note: This command is only supported by the FUS.
953  *
954  * @param None
955  * @retval Status
956  */
957  SHCI_CmdStatus_t SHCI_C2_FUS_StartWs( void );
958 
959  /**
960  * SHCI_C2_FUS_LockUsrKey
961  * @brief Request the FUS to lock the user key so that it cannot be updated later on
962  * Note: This command is supported by both the FUS and the wireless stack.
963  *
964  * @param key_index : index of the user key to lock
965  * @retval Status
966  */
967  SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey( uint8_t key_index );
968 
969  /**
970  * SHCI_C2_FUS_UnloadUsrKey
971  * @brief Request the FUS to Unload the user key so that the CPU1 may use the AES with another Key
972  * Note: This command is supported by both the FUS and the wireless stack.
973  *
974  * @param key_index : index of the user key to unload
975  * @retval Status
976  */
977  SHCI_CmdStatus_t SHCI_C2_FUS_UnloadUsrKey( uint8_t key_index );
978 
979  /**
980  * SHCI_C2_FUS_ActivateAntiRollback
981  * @brief Request the FUS to enable the AntiRollback feature so that it is not possible to update the wireless firmware
982  * with an older version than the current one.
983  * Note:
984  * - This command is only supported by the FUS.
985  * - Once this feature is enabled, it is not possible anymore to disable it.
986  *
987  * @param None
988  * @retval Status
989  */
990  SHCI_CmdStatus_t SHCI_C2_FUS_ActivateAntiRollback( void );
991 
992  /**
993  * SHCI_C2_BLE_Init
994  * @brief Provides parameters and starts the BLE Stack
995  *
996  * @param pCmdPacket : Parameters are described SHCI_C2_Ble_Init_Cmd_Packet_t declaration
997  * @retval Status
998  */
999  SHCI_CmdStatus_t SHCI_C2_BLE_Init( SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket );
1000 
1001  /**
1002  * SHCI_C2_THREAD_Init
1003  * @brief Starts the THREAD Stack
1004  *
1005  * @param None
1006  * @retval Status
1007  */
1008  SHCI_CmdStatus_t SHCI_C2_THREAD_Init( void );
1009 
1010  /**
1011  * SHCI_C2_LLDTESTS_Init
1012  * @brief Starts the LLD tests CLI
1013  *
1014  * @param param_size : Nb of bytes
1015  * @param p_param : pointeur with data to give from M4 to M0
1016  * @retval Status
1017  */
1018  SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init( uint8_t param_size, uint8_t * p_param );
1019 
1020  /**
1021  * SHCI_C2_BLE_LLD_Init
1022  * @brief Starts the LLD tests BLE
1023  *
1024  * @param param_size : Nb of bytes
1025  * @param p_param : pointeur with data to give from M4 to M0
1026  * @retval Status
1027  */
1028  SHCI_CmdStatus_t SHCI_C2_BLE_LLD_Init( uint8_t param_size, uint8_t * p_param );
1029 
1030  /**
1031  * SHCI_C2_ZIGBEE_Init
1032  * @brief Starts the Zigbee Stack
1033  *
1034  * @param None
1035  * @retval Status
1036  */
1037  SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init( void );
1038 
1039  /**
1040  * SHCI_C2_DEBUG_Init
1041  * @brief Starts the Traces
1042  *
1043  * @param None
1044  * @retval Status
1045  */
1046  SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket );
1047 
1048  /**
1049  * SHCI_C2_FLASH_EraseActivity
1050  * @brief Provides the information of the start and the end of a flash erase window on the CPU1
1051  *
1052  * @param erase_activity: Start/End of erase activity
1053  * @retval Status
1054  */
1055  SHCI_CmdStatus_t SHCI_C2_FLASH_EraseActivity( SHCI_EraseActivity_t erase_activity );
1056 
1057  /**
1058  * SHCI_C2_CONCURRENT_SetMode
1059  * @brief Enable/Disable Thread on CPU2 (M0+)
1060  *
1061  * @param Mode: BLE or Thread enable flag
1062  * @retval Status
1063  */
1064  SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode( SHCI_C2_CONCURRENT_Mode_Param_t Mode );
1065 
1066  /**
1067  * SHCI_C2_CONCURRENT_GetNextBleEvtTime
1068  * @brief Get the next BLE event date (relative time)
1069  *
1070  * @param Command Packet
1071  * @retval None
1072  */
1073  SHCI_CmdStatus_t SHCI_C2_CONCURRENT_GetNextBleEvtTime( SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t *pParam );
1074 
1075  /**
1076  * SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification
1077  * @brief Activate the next 802.15.4 event notification (one shot)
1078  *
1079  * @param None
1080  * @retval None
1081  */
1082  SHCI_CmdStatus_t SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification( void );
1083 
1084  /**
1085  * SHCI_C2_FLASH_StoreData
1086  * @brief Store Data in Flash
1087  *
1088  * @param Ip: BLE or THREAD
1089  * @retval Status
1090  */
1091  SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData( SHCI_C2_FLASH_Ip_t Ip );
1092 
1093  /**
1094  * SHCI_C2_FLASH_EraseData
1095  * @brief Erase Data in Flash
1096  *
1097  * @param Ip: BLE or THREAD
1098  * @retval Status
1099  */
1100  SHCI_CmdStatus_t SHCI_C2_FLASH_EraseData( SHCI_C2_FLASH_Ip_t Ip );
1101 
1102  /**
1103  * SHCI_C2_RADIO_AllowLowPower
1104  * @brief Allow or forbid IP_radio (802_15_4 or BLE) to enter in low power mode.
1105  *
1106  * @param Ip: BLE or 802_15_5
1107  * @param FlagRadioLowPowerOn: True or false
1108  * @retval Status
1109  */
1110  SHCI_CmdStatus_t SHCI_C2_RADIO_AllowLowPower( SHCI_C2_FLASH_Ip_t Ip,uint8_t FlagRadioLowPowerOn);
1111 
1112 
1113  /**
1114  * SHCI_C2_MAC_802_15_4_Init
1115  * @brief Starts the MAC 802.15.4 on M0
1116  *
1117  * @param None
1118  * @retval Status
1119  */
1120  SHCI_CmdStatus_t SHCI_C2_MAC_802_15_4_Init( void );
1121 
1122  /**
1123  * SHCI_GetWirelessFwInfo
1124  * @brief This function read back the informations relative to the wireless binary loaded.
1125  * Refer yourself to MB_WirelessFwInfoTable_t structure to get the significance
1126  * of the different parameters returned.
1127  * @param pWirelessInfo : Pointer to WirelessFwInfo_t.
1128  *
1129  * @retval SHCI_Success
1130  */
1131  SHCI_CmdStatus_t SHCI_GetWirelessFwInfo( WirelessFwInfo_t* pWirelessInfo );
1132 
1133  /**
1134  * SHCI_C2_Reinit
1135  * @brief This is required to allow the CPU1 to fake a set C2BOOT when it has already been set.
1136  * In order to fake a C2BOOT, the CPU1 shall :
1137  * - Send SHCI_C2_Reinit()
1138  * - call SEV instruction
1139  * WARNING:
1140  * This function is intended to be used by the SBSFU
1141  *
1142  * @param None
1143  * @retval Status
1144  */
1145  SHCI_CmdStatus_t SHCI_C2_Reinit( void );
1146 
1147  /**
1148  * SHCI_C2_ExtpaConfig
1149  * @brief Send the Ext PA configuration
1150  * When the CPU2 receives the command, it controls the Ext PA as requested by the configuration
1151  * This configures only which IO is used to enable/disable the ExtPA and the associated polarity
1152  * This command has no effect on the other IO that is used to control the mode of the Ext PA (Rx/Tx)
1153  *
1154  * @param gpio_port: GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WBxx family
1155  * @param gpio_pin_number: This parameter can be one of GPIO_PIN_x (= LL_GPIO_PIN_x) where x can be (0..15).
1156  * @param gpio_polarity: This parameter can be either
1157  * - EXT_PA_ENABLED_LOW: ExtPA is enabled when GPIO is low
1158  * - EXT_PA_ENABLED_HIGH: ExtPA is enabled when GPIO is high
1159  * @param gpio_status: This parameter can be either
1160  * - EXT_PA_DISABLED: Stop driving the ExtPA
1161  * - EXT_PA_ENABLED: Drive the ExtPA according to radio activity
1162  * (ON before the Event and OFF at the end of the event)
1163  * @retval Status
1164  */
1165  SHCI_CmdStatus_t SHCI_C2_ExtpaConfig(uint32_t gpio_port, uint16_t gpio_pin_number, uint8_t gpio_polarity, uint8_t gpio_status);
1166 
1167  /**
1168  * SHCI_C2_SetFlashActivityControl
1169  * @brief Set the mechanism to be used on CPU2 to prevent the CPU1 to either write or erase in flash
1170  *
1171  * @param Source: It can be one of the following list
1172  * - FLASH_ACTIVITY_CONTROL_PES : The CPU2 set the PES bit to prevent the CPU1 to either read or write in flash
1173  * - FLASH_ACTIVITY_CONTROL_SEM7 : The CPU2 gets the semaphore 7 to prevent the CPU1 to either read or write in flash.
1174  * This requires the CPU1 to first get semaphore 7 before erasing or writing the flash.
1175  *
1176  * @retval Status
1177  */
1178  SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl(SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source);
1179 
1180  /**
1181  * SHCI_C2_Config
1182  * @brief Send the system configuration to the CPU2
1183  *
1184  * @param pCmdPacket: address of the buffer holding following parameters
1185  * uint8_t PayloadCmdSize : Size of the payload - shall be SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE
1186  * uint8_t Config1 :
1187  * - bit0 : 0 - BLE NVM Data data are flushed in internal secure flash
1188  * 1 - BLE NVM Data are written in SRAM cache pointed by BleNvmRamAddress
1189  * - bit1 : 0 - THREAD NVM Data data are flushed in internal secure flash
1190  * 1 - THREAD NVM Data are written in SRAM cache pointed by ThreadNvmRamAddress
1191  * - bit2 to bit7 : Unused, shall be set to 0
1192  * uint8_t EvtMask1 :
1193  * When a bit is set to 0, the event is not reported
1194  * bit0 : Asynchronous Event with Sub Evt Code 0x9201 (= SHCI_SUB_EVT_ERROR_NOTIF)
1195  * ...
1196  * bit31 : Asynchronous Event with Sub Evt Code 0x9220
1197  * uint8_t Spare1 : Unused, shall be set to 0
1198  * uint32_t BleNvmRamAddress :
1199  * Only considered when Config1.bit0 = 1
1200  * When set to 0, data are kept in internal SRAM on CPU2
1201  * Otherwise, data are copied in the cache pointed by BleNvmRamAddress
1202  * The size of the buffer shall be BLE_NVM_SRAM_SIZE (number of 32bits)
1203  * The buffer shall be allocated in SRAM2
1204  * uint32_t ThreadNvmRamAddress :
1205  * Only considered when Config1.bit1 = 1
1206  * When set to 0, data are kept in internal SRAM on CPU2
1207  * Otherwise, data are copied in the cache pointed by ThreadNvmRamAddress
1208  * The size of the buffer shall be THREAD_NVM_SRAM_SIZE (number of 32bits)
1209  * The buffer shall be allocated in SRAM2
1210  *
1211  * Please check macro definition to be used for this function
1212  * They are defined in this file next to the definition of SHCI_OPCODE_C2_CONFIG
1213  *
1214  * @retval Status
1215  */
1216  SHCI_CmdStatus_t SHCI_C2_Config(SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket);
1217 
1218  /**
1219  * SHCI_C2_802_15_4_DeInit
1220  * @brief Deinit 802.15.4 layer (to be used before entering StandBy mode)
1221  *
1222  * @param None
1223  * @retval Status
1224  */
1225  SHCI_CmdStatus_t SHCI_C2_802_15_4_DeInit( void );
1226 
1227  #ifdef __cplusplus
1228 }
1229 #endif
1230 
1231 #endif /*__SHCI_H */
1232 
1233 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
WirelessFwInfo_t::VersionMajor
uint8_t VersionMajor
Wireless Info.
Definition: shci.h:847
SHCI_C2_FUS_UnloadUsrKey
SHCI_CmdStatus_t SHCI_C2_FUS_UnloadUsrKey(uint8_t key_index)
SHCI_C2_FUS_UnloadUsrKey.
Param
SHCI_C2_Ble_Init_Cmd_Param_t Param
Does not need to be initialized by the user.
Definition: shci.h:565
SHCI_C2_RADIO_AllowLowPower
SHCI_CmdStatus_t SHCI_C2_RADIO_AllowLowPower(SHCI_C2_FLASH_Ip_t Ip, uint8_t FlagRadioLowPowerOn)
SHCI_C2_RADIO_AllowLowPower.
SHCI_C2_DEBUG_Init
SHCI_CmdStatus_t SHCI_C2_DEBUG_Init(SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket)
SHCI_C2_DEBUG_Init.
SHCI_C2_BLE_Init
SHCI_CmdStatus_t SHCI_C2_BLE_Init(SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket)
SHCI_C2_BLE_Init.
SHCI_OCF_t
SHCI_OCF_t
THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU2 DEFINITION.
Definition: shci.h:186
HwVersion
uint8_t HwVersion
HwVersion Reserved for future use - shall be set to 0.
Definition: shci.h:542
SHCI_C2_FUS_LoadUsrKey
SHCI_CmdStatus_t SHCI_C2_FUS_LoadUsrKey(uint8_t key_index)
SHCI_C2_FUS_LoadUsrKey.
SHCI_C2_ThreadNvmRamUpdate_Evt_t
__packed struct @6 SHCI_C2_ThreadNvmRamUpdate_Evt_t
SHCI_SUB_EVT_THREAD_NVM_RAM_UPDATE This notifies the CPU1 which part of the OT NVM RAM has been updat...
BleBufferSize
uint32_t BleBufferSize
NOT USED - shall be set to 0.
Definition: shci.h:376
SHCI_C2_802_15_4_DeInit
SHCI_CmdStatus_t SHCI_C2_802_15_4_DeInit(void)
SHCI_C2_802_15_4_DeInit.
SHCI_C2_SetFlashActivityControl
SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl(SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source)
SHCI_C2_SetFlashActivityControl.
SHCI_C2_Config
SHCI_CmdStatus_t SHCI_C2_Config(SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket)
SHCI_C2_Config.
max_coc_initiator_nbr
uint8_t max_coc_initiator_nbr
Maximum number of connection-oriented channels in initiator mode.
Definition: shci.h:548
SHCI_C2_BleNvmRamUpdate_Evt_t
__packed struct @5 SHCI_C2_BleNvmRamUpdate_Evt_t
SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE This notifies the CPU1 which part of the BLE NVM RAM has been updated...
SHCI_C2_CONFIG_Cmd_Param_t
__packed struct @25 SHCI_C2_CONFIG_Cmd_Param_t
Command parameters.
SHCI_Header_t
__packed struct @9 SHCI_Header_t
SHCI_SUB_EVT_NVM_END_ERASE This notifies the CPU1 that the CPU2 has erased all expected flash sectors...
SHCI_C2_FUS_GetState
uint8_t SHCI_C2_FUS_GetState(SHCI_FUS_GetState_ErrorCode_t *p_rsp)
SHCI_C2_FUS_GetState.
SHCI_C2_LLDTESTS_Init
SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init(uint8_t param_size, uint8_t *p_param)
SHCI_C2_LLDTESTS_Init.
ViterbiEnable
uint8_t ViterbiEnable
ViterbiEnable Viterbi implementation in BLE LL reception.
Definition: shci.h:526
MaxConnEventLength
uint32_t MaxConnEventLength
MaxConnEventLength This parameter determines the maximum duration of a slave connection event...
Definition: shci.h:510
SHCI_C2_ExtpaConfig
SHCI_CmdStatus_t SHCI_C2_ExtpaConfig(uint32_t gpio_port, uint16_t gpio_pin_number, uint8_t gpio_polarity, uint8_t gpio_status)
SHCI_C2_ExtpaConfig.
SHCI_C2_THREAD_Init
SHCI_CmdStatus_t SHCI_C2_THREAD_Init(void)
SHCI_C2_THREAD_Init.
ExtendedPacketLengthEnable
uint8_t ExtendedPacketLengthEnable
ExtendedPacketLengthEnable Disable/enable the extended packet length BLE 5.0 feature.
Definition: shci.h:432
NumOfLinks
uint8_t NumOfLinks
NumOfLinks Maximum number of BLE links supported.
Definition: shci.h:424
SHCI_C2_FLASH_StoreData
SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData(SHCI_C2_FLASH_Ip_t Ip)
SHCI_C2_FLASH_StoreData.
HsStartupTime
uint16_t HsStartupTime
HsStartupTime Startup time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us...
Definition: shci.h:518
SHCI_C2_CONCURRENT_Mode_Param_t
SHCI_C2_CONCURRENT_Mode_Param_t
command parameters
Definition: shci.h:633
SHCI_C2_DEBUG_TracesConfig_t
__packed struct @17 SHCI_C2_DEBUG_TracesConfig_t
Command parameters.
SHCI_C2_Ble_Init_Cmd_Param_t
__packed struct @15 SHCI_C2_Ble_Init_Cmd_Param_t
THE ORDER SHALL NOT BE CHANGED.
SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification(void)
SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification.
SHCI_C2_FUS_StoreUsrKey
SHCI_CmdStatus_t SHCI_C2_FUS_StoreUsrKey(SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t *pParam, uint8_t *p_key_index)
SHCI_C2_FUS_StoreUsrKey.
SHCI_C2_MAC_802_15_4_Init
SHCI_CmdStatus_t SHCI_C2_MAC_802_15_4_Init(void)
SHCI_C2_MAC_802_15_4_Init.
max_tx_power
int8_t max_tx_power
Maximum transmit power in dBm supported by the Controller.
Definition: shci.h:560
NumAttrRecord
uint16_t NumAttrRecord
NumAttrRecord Maximum number of attribute records related to all the required characteristics (exclud...
Definition: shci.h:390
SHCI_C2_FUS_FwDelete
SHCI_CmdStatus_t SHCI_C2_FUS_FwDelete(void)
SHCI_C2_FUS_FwDelete.
SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t
SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t
Command parameters.
Definition: shci.h:702
SHCI_C2_FUS_StartWs
SHCI_CmdStatus_t SHCI_C2_FUS_StartWs(void)
SHCI_C2_FUS_StartWs.
WirelessFwInfo_t::FusVersionMajor
uint8_t FusVersionMajor
Fus Info.
Definition: shci.h:860
MetaData
uint32_t MetaData[3]
MetaData holds : 2*32bits for chaining list 1*32bits with BLE header (type + Opcode + Length) ...
Definition: shci.h:160
SHCI_C2_FLASH_Ip_t
SHCI_C2_FLASH_Ip_t
command parameters
Definition: shci.h:657
min_tx_power
int8_t min_tx_power
Minimum transmit power in dBm supported by the Controller.
Definition: shci.h:554
AttrValueArrSize
uint16_t AttrValueArrSize
AttrValueArrSize NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "...
Definition: shci.h:416
SHCI_C2_FLASH_EraseData
SHCI_CmdStatus_t SHCI_C2_FLASH_EraseData(SHCI_C2_FLASH_Ip_t Ip)
SHCI_C2_FLASH_EraseData.
mbox_def.h
Mailbox definition.
SHCI_GetWirelessFwInfo
SHCI_CmdStatus_t SHCI_GetWirelessFwInfo(WirelessFwInfo_t *pWirelessInfo)
SHCI_GetWirelessFwInfo.
pBleBufferAddress
uint8_t * pBleBufferAddress
NOT USED - shall be set to 0.
Definition: shci.h:375
SHCI_C2_FUS_FwUpgrade
SHCI_CmdStatus_t SHCI_C2_FUS_FwUpgrade(uint32_t fw_src_add, uint32_t fw_dest_add)
SHCI_C2_FUS_FwUpgrade.
MasterSca
uint8_t MasterSca
MasterSca The sleep clock accuracy handled in master mode.
Definition: shci.h:490
AttMtu
uint16_t AttMtu
AttMtu NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" (...
Definition: shci.h:463
SlaveSca
uint16_t SlaveSca
SlaveSca The sleep clock accuracy (ppm value) that used in BLE connected slave mode to calculate the ...
Definition: shci.h:473
SHCI_C2_FUS_ActivateAntiRollback
SHCI_CmdStatus_t SHCI_C2_FUS_ActivateAntiRollback(void)
SHCI_C2_FUS_ActivateAntiRollback.
PrWriteListSize
uint8_t PrWriteListSize
PrWriteListSize NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "L...
Definition: shci.h:442
SHCI_C2_CONCURRENT_SetMode
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode(SHCI_C2_CONCURRENT_Mode_Param_t Mode)
SHCI_C2_CONCURRENT_SetMode.
WirelessFwInfo_t
Definition: shci.h:843
SHCI_EraseActivity_t
SHCI_EraseActivity_t
Command parameters.
Definition: shci.h:623
SHCI_C2_CONCURRENT_GetNextBleEvtTime
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_GetNextBleEvtTime(SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t *pParam)
SHCI_C2_CONCURRENT_GetNextBleEvtTime.
MblockCount
uint8_t MblockCount
MblockCount NOTE: This parameter is overwritten by the CPU2 with an hardcoded optimal value when the ...
Definition: shci.h:453
SHCI_C2_BLE_LLD_Init
SHCI_CmdStatus_t SHCI_C2_BLE_LLD_Init(uint8_t param_size, uint8_t *p_param)
SHCI_C2_BLE_LLD_Init.
SHCI_FUS_GetState_ErrorCode_t
SHCI_FUS_GetState_ErrorCode_t
No command parameters.
Definition: shci.h:235
SHCI_C2_Reinit
SHCI_CmdStatus_t SHCI_C2_Reinit(void)
SHCI_C2_Reinit.
SHCI_C2_FUS_LockAuthKey
SHCI_CmdStatus_t SHCI_C2_FUS_LockAuthKey(void)
SHCI_C2_FUS_LockAuthKey.
NumAttrServ
uint16_t NumAttrServ
NumAttrServ Defines the maximum number of services that can be stored in the GATT database...
Definition: shci.h:399
Options
uint8_t Options
Options flags.
Definition: shci.h:536
SHCI_C2_FUS_UpdateAuthKey
SHCI_CmdStatus_t SHCI_C2_FUS_UpdateAuthKey(SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t *pParam)
SHCI_C2_FUS_UpdateAuthKey.
SHCI_C2_ZIGBEE_Init
SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init(void)
SHCI_C2_ZIGBEE_Init.
SHCI_C2_Ready_Evt_t
__packed struct @3 SHCI_C2_Ready_Evt_t
SHCI_SUB_EVT_CODE_READY This notifies the CPU1 that the CPU2 is now ready to receive commands It repo...
SHCI_C2_FUS_LockUsrKey
SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey(uint8_t key_index)
SHCI_C2_FUS_LockUsrKey.
SHCI_C2_NvmStartWrite_Evt_t
__packed struct @7 SHCI_C2_NvmStartWrite_Evt_t
SHCI_SUB_EVT_NVM_START_WRITE This notifies the CPU1 that the CPU2 has started a write procedure in Fl...
SHCI_C2_ErrorNotif_Evt_t
__packed struct @4 SHCI_C2_ErrorNotif_Evt_t
SHCI_SUB_EVT_ERROR_NOTIF This reports to the CPU1 some error form the CPU2.
SHCI_SUB_EVT_CODE_t
SHCI_SUB_EVT_CODE_t
THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU1 DEFINITION.
Definition: shci.h:62
SHCI_C2_FLASH_EraseActivity
SHCI_CmdStatus_t SHCI_C2_FLASH_EraseActivity(SHCI_EraseActivity_t erase_activity)
SHCI_C2_FLASH_EraseActivity.
SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t
__packed struct @21 SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t
command parameters
LsSource
uint8_t LsSource
LsSource Source for the 32 kHz slow speed clock.
Definition: shci.h:499
SHCI_C2_NvmStartErase_Evt_t
__packed struct @8 SHCI_C2_NvmStartErase_Evt_t
SHCI_SUB_EVT_NVM_END_WRITE This notifies the CPU1 that the CPU2 has written all expected data in Flas...
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