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qspi_test_utils.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018-2018 ARM Limited
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 #ifndef MBED_QSPI_TEST_UTILS_H
18 #define MBED_QSPI_TEST_UTILS_H
19 
20 #include "flash_configs/flash_configs.h"
21 #include "unity/unity.h"
22 
23 #define QSPI_NONE (-1)
24 
25 enum QspiStatus {
26  sOK,
27  sError,
28  sTimeout,
29  sUnknown
30 };
31 
32 class QspiCommand {
33 public:
34  void configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width,
35  qspi_bus_width_t alt_width, qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
36  int dummy_cycles = 0);
37 
38  void set_dummy_cycles(int dummy_cycles);
39 
40  void build(int instruction, int address = QSPI_NONE, int alt = QSPI_NONE);
41 
42  qspi_command_t *get();
43 
44 private:
45  qspi_command_t _cmd;
46 };
47 
48 struct Qspi {
49  qspi_t handle;
50  QspiCommand cmd;
51 };
52 
53 // MODE_Command_Address_Data_Alt
54 #define MODE_1_1_1 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE
55 #define MODE_1_1_2 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
56 #define MODE_1_2_2 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
57 #define MODE_2_2_2 QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
58 #define MODE_1_1_4 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
59 #define MODE_1_4_4 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
60 #define MODE_4_4_4 QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
61 
62 #define WRITE_1_1_1 MODE_1_1_1, QSPI_CMD_WRITE_1IO
63 #ifdef QSPI_CMD_WRITE_2IO
64 #define WRITE_1_2_2 MODE_1_2_2, QSPI_CMD_WRITE_2IO
65 #endif
66 #ifdef QSPI_CMD_WRITE_1I4O // Quad page program - command: 0x32
67 #define WRITE_1_1_4 MODE_1_1_4, QSPI_CMD_WRITE_1I4O
68 #endif
69 #ifdef QSPI_CMD_WRITE_4IO
70 #define WRITE_1_4_4 MODE_1_4_4, QSPI_CMD_WRITE_4IO
71 #endif
72 #ifdef QSPI_CMD_WRITE_DPI
73 #define WRITE_2_2_2 MODE_2_2_2, QSPI_CMD_WRITE_DPI
74 #endif
75 #ifdef QSPI_CMD_WRITE_QPI
76 #define WRITE_4_4_4 MODE_4_4_4, QSPI_CMD_WRITE_QPI
77 #endif
78 
79 
80 #define READ_1_1_1 MODE_1_1_1, QSPI_CMD_READ_1IO, QSPI_READ_1IO_DUMMY_CYCLE
81 #ifdef QSPI_CMD_READ_1I2O
82 #define READ_1_1_2 MODE_1_1_2, QSPI_CMD_READ_1I2O, QSPI_READ_1I2O_DUMMY_CYCLE
83 #endif
84 #ifdef QSPI_CMD_READ_2IO
85 #define READ_1_2_2 MODE_1_2_2, QSPI_CMD_READ_2IO, QSPI_READ_2IO_DUMMY_CYCLE
86 #endif
87 #ifdef QSPI_CMD_READ_1I4O
88 #define READ_1_1_4 MODE_1_1_4, QSPI_CMD_READ_1I4O, QSPI_READ_1I4O_DUMMY_CYCLE
89 #endif
90 #ifdef QSPI_CMD_READ_4IO
91 #define READ_1_4_4 MODE_1_4_4, QSPI_CMD_READ_4IO, QSPI_READ_4IO_DUMMY_CYCLE
92 #endif
93 
94 #ifdef QSPI_CMD_READ_DPI
95 #define READ_2_2_2 MODE_2_2_2, QSPI_CMD_READ_DPI, QSPI_READ_2IO_DUMMY_CYCLE
96 #endif
97 #ifdef QSPI_CMD_READ_QPI
98 #define READ_4_4_4 MODE_4_4_4, QSPI_CMD_READ_QPI, QSPI_READ_4IO_DUMMY_CYCLE
99 #endif
100 
101 #define ADDR_SIZE_8 QSPI_CFG_ADDR_SIZE_8
102 #define ADDR_SIZE_16 QSPI_CFG_ADDR_SIZE_16
103 #define ADDR_SIZE_24 QSPI_CFG_ADDR_SIZE_24
104 #define ADDR_SIZE_32 QSPI_CFG_ADDR_SIZE_32
105 
106 #define ALT_SIZE_8 QSPI_CFG_ALT_SIZE_8
107 #define ALT_SIZE_16 QSPI_CFG_ALT_SIZE_16
108 #define ALT_SIZE_24 QSPI_CFG_ALT_SIZE_24
109 #define ALT_SIZE_32 QSPI_CFG_ALT_SIZE_32
110 
111 #define STATUS_REG QSPI_CMD_RDSR
112 #define CONFIG_REG0 QSPI_CMD_RDCR0
113 #ifdef QSPI_CMD_RDCR1
114 #define CONFIG_REG1 QSPI_CMD_RDCR1
115 #endif
116 #ifdef QSPI_CMD_RDCR2
117 #define CONFIG_REG2 QSPI_CMD_RDCR2
118 #endif
119 #define SECURITY_REG QSPI_CMD_RDSCUR
120 
121 #ifndef QSPI_CONFIG_REG_1_SIZE
122 #define QSPI_CONFIG_REG_1_SIZE 0
123 #endif
124 
125 #ifndef QSPI_CONFIG_REG_2_SIZE
126 #define QSPI_CONFIG_REG_2_SIZE 0
127 #endif
128 
129 
130 #define SECTOR_ERASE QSPI_CMD_ERASE_SECTOR
131 #define BLOCK_ERASE QSPI_CMD_ERASE_BLOCK_64
132 
133 
134 #define SECTOR_ERASE_MAX_TIME QSPI_ERASE_SECTOR_MAX_TIME
135 #define BLOCK32_ERASE_MAX_TIME QSPI_ERASE_BLOCK_32_MAX_TIME
136 #define BLOCK64_ERASE_MAX_TIME QSPI_ERASE_BLOCK_64_MAX_TIME
137 #define PAGE_PROG_MAX_TIME QSPI_PAGE_PROG_MAX_TIME
138 #define WRSR_MAX_TIME QSPI_WRSR_MAX_TIME
139 #define WAIT_MAX_TIME QSPI_WAIT_MAX_TIME
140 
141 
142 
143 qspi_status_t read_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q);
144 qspi_status_t write_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q);
145 
146 QspiStatus flash_wait_for(uint32_t time_us, Qspi &qspi);
147 
148 void flash_init(Qspi &qspi);
149 
150 qspi_status_t write_enable(Qspi &qspi);
151 qspi_status_t write_disable(Qspi &qspi);
152 
153 void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str = NULL);
154 
155 qspi_status_t mode_enable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
156 qspi_status_t mode_disable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
157 
158 qspi_status_t fast_mode_enable(Qspi &qspi);
159 qspi_status_t fast_mode_disable(Qspi &qspi);
160 
161 qspi_status_t erase(uint32_t erase_cmd, uint32_t flash_addr, Qspi &qspi);
162 
163 bool is_extended_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
164 bool is_dual_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
165 bool is_quad_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
166 
167 #define WAIT_FOR(timeout, q) TEST_ASSERT_EQUAL_MESSAGE(sOK, flash_wait_for(timeout, q), "flash_wait_for failed!!!")
168 
169 
170 #endif // MBED_QSPI_TEST_UTILS_H
qspi_command
QSPI command.
Definition: qspi_api.h:92
qspi_t
struct qspi_s qspi_t
QSPI HAL object.
Definition: qspi_api.h:40
qspi_address_size_t
enum qspi_address_size qspi_address_size_t
Address size in bits.
qspi_alt_size_t
uint8_t qspi_alt_size_t
Alternative size in bits.
Definition: qspi_api.h:79
qspi_bus_width_t
enum qspi_bus_width qspi_bus_width_t
QSPI Bus width.
flash_init
int32_t flash_init(flash_t *obj)
Initialize the flash peripheral and the flash_t object.
qspi_status_t
enum qspi_status qspi_status_t
QSPI return status.
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