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SPITester.h
1 /*
2  * Copyright (c) 2019, Arm Limited and affiliates.
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 
18 #ifndef SPI_TESTER_H
19 #define SPI_TESTER_H
20 
21 #include "MbedTester.h"
22 
23 class SPITester: public MbedTester {
24 public:
25 
26  enum SpiMode {
27  Mode0 = 0,
28  Mode1 = 1,
29  Mode2 = 2,
30  Mode3 = 3
31  };
32 
33  enum SpiBitOrder {
34  MSBFirst = 0,
35  LSBFirst = 1
36  };
37 
38  enum SpiDuplex {
39  FullDuplex = 0,
40  HalfDuplex = 1
41  };
42 
43  SPITester(const PinList *form_factor, const PinList *exclude_pins)
44  : MbedTester(form_factor, exclude_pins)
45  {
46 
47  }
48 
49 protected:
50  /*
51  * Read the number of transfers which have occurred
52  *
53  * return The number of SPI transfers that have completed since
54  * spi was reset.
55  */
56  uint16_t get_transfer_count(uint32_t addr_transfers, uint32_t size_transfers);
57 
58  /*
59  * Read a checksum of data send to the tester
60  *
61  * param addr_checksum Address of the FPGA checksum reg.
62  * param size_checksum Size of the FPGA checksum reg.
63  *
64  * return The sum of all bytes sent to the tester since reset.
65  */
66  uint32_t get_receive_checksum(uint32_t addr_checksum, uint32_t size_checksum);
67 
68  /*
69  * Set the clock mode of the spi_slave module.
70  *
71  * param mode Spi clock mode
72  * param addr_spi_ctrl Address of the FPGA spi control reg.
73  * param size_spi_ctrl Size of the FPGA FPGA spi control reg.
74  * param offset_clk_mode Clock mode offset.
75  * param size_clk_mode Clock mode size.
76  */
77  void set_mode(SpiMode mode, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_clk_mode, uint32_t size_clk_mode);
78 
79  /*
80  * Set bit order durring transmission of the spi_slave module.
81  *
82  * param bit_order Spi clock mode
83  * param addr_spi_ctrl Address of the FPGA spi control reg.
84  * param size_spi_ctrl Size of the FPGA FPGA spi control reg.
85  * param offset_bit_order Bit order offset.
86  * param size_bit_order Bit order size.
87  */
88  void set_bit_order(SpiBitOrder bit_order, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_bit_order, uint32_t size_bit_order);
89 
90  /*
91  * Set symbol size used durring transmission of the spi_slave module.
92  *
93  * param sym_size Spi symbol size
94  * param addr_spi_ctrl Address of the FPGA spi control reg.
95  * param size_spi_ctrl Size of the FPGA FPGA spi control reg.
96  * param offset_sym_size Symbol size offset.
97  * param size_sym_size Symbol size size.
98  */
99  void set_sym_size(uint32_t sym_size, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_sym_size, uint32_t size_sym_size);
100 
101  /*
102  * Set full-duplex/half-duplex transmission mode of the spi_slave module.
103  *
104  * param duplex Duplex mode used for the transmission
105  * param addr_spi_ctrl Address of the FPGA spi control reg.
106  * param size_spi_ctrl Size of the FPGA FPGA spi control reg.
107  * param offset_duplex Duplex mode offset.
108  * param size_duplex Duplex mode size.
109  */
110  void set_duplex_mode(SpiDuplex duplex, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_duplex, uint32_t size_duplex);
111 
112  /*
113  * Set tx/rx symbol count.
114  *
115  * tx_cnt TX symbol count
116  * rx_cnt RX symbol count
117  * param addr_hd_rx_cnt Address of the FPGA half duplex RX count reg.
118  * param size_hd_rx_cnt Size of the FPGA half duplex RX count reg.
119  * param addr_hd_tx_cnt Address of the FPGA half duplex TX count reg.
120  * param size_hd_tx_cnt Size of the FPGA half duplex TX count reg.
121  *
122  * note Required only in Half-Duplex mode.
123  */
124  void set_hd_tx_rx_cnt(uint16_t tx_cnt, uint16_t rx_cnt, uint32_t addr_hd_rx_cnt, uint32_t size_hd_rx_cnt, uint32_t addr_hd_tx_cnt, uint32_t size_hd_tx_cnt);
125 };
126 
127 #endif
PinList
Definition: pinmap.h:37
MbedTester::MbedTester
MbedTester(const PinList *form_factor, const PinList *exclude_pins)
Construct a new MbedTester object.
MbedTester
The base class for controlling the FPGA CI Test Shield.
Definition: MbedTester.h:68
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