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qspi_test_utils.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018-2018 ARM Limited
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 #ifndef MBED_QSPI_TEST_UTILS_H
17 #define MBED_QSPI_TEST_UTILS_H
18 
19 #include "flash_configs/flash_configs.h"
20 #include "unity/unity.h"
21 
22 #define QSPI_NONE (-1)
23 
24 enum QspiStatus {
25  sOK,
26  sError,
27  sTimeout,
28  sUnknown
29 };
30 
31 class QspiCommand {
32 public:
33  void configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width,
34  qspi_bus_width_t alt_width, qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
35  int dummy_cycles = 0);
36 
37  void set_dummy_cycles(int dummy_cycles);
38 
39  void build(int instruction, int address = QSPI_NONE, int alt = QSPI_NONE);
40 
41  qspi_command_t *get();
42 
43 private:
44  qspi_command_t _cmd;
45 };
46 
47 struct Qspi {
48  qspi_t handle;
49  QspiCommand cmd;
50 };
51 
52 // MODE_Command_Address_Data_Alt
53 #define MODE_1_1_1 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE
54 #define MODE_1_1_2 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
55 #define MODE_1_2_2 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
56 #define MODE_2_2_2 QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
57 #define MODE_1_1_4 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
58 #define MODE_1_4_4 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
59 #define MODE_4_4_4 QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
60 
61 #define WRITE_1_1_1 MODE_1_1_1, QSPI_CMD_WRITE_1IO
62 #ifdef QSPI_CMD_WRITE_2IO
63 #define WRITE_1_2_2 MODE_1_2_2, QSPI_CMD_WRITE_2IO
64 #endif
65 #ifdef QSPI_CMD_WRITE_1I4O // Quad page program - command: 0x32
66 #define WRITE_1_1_4 MODE_1_1_4, QSPI_CMD_WRITE_1I4O
67 #endif
68 #ifdef QSPI_CMD_WRITE_4IO
69 #define WRITE_1_4_4 MODE_1_4_4, QSPI_CMD_WRITE_4IO
70 #endif
71 #ifdef QSPI_CMD_WRITE_DPI
72 #define WRITE_2_2_2 MODE_2_2_2, QSPI_CMD_WRITE_DPI
73 #endif
74 #ifdef QSPI_CMD_WRITE_QPI
75 #define WRITE_4_4_4 MODE_4_4_4, QSPI_CMD_WRITE_QPI
76 #endif
77 
78 
79 #define READ_1_1_1 MODE_1_1_1, QSPI_CMD_READ_1IO, QSPI_READ_1IO_DUMMY_CYCLE
80 #ifdef QSPI_CMD_READ_1I2O
81 #define READ_1_1_2 MODE_1_1_2, QSPI_CMD_READ_1I2O, QSPI_READ_1I2O_DUMMY_CYCLE
82 #endif
83 #ifdef QSPI_CMD_READ_2IO
84 #define READ_1_2_2 MODE_1_2_2, QSPI_CMD_READ_2IO, QSPI_READ_2IO_DUMMY_CYCLE
85 #endif
86 #ifdef QSPI_CMD_READ_1I4O
87 #define READ_1_1_4 MODE_1_1_4, QSPI_CMD_READ_1I4O, QSPI_READ_1I4O_DUMMY_CYCLE
88 #endif
89 #ifdef QSPI_CMD_READ_4IO
90 #define READ_1_4_4 MODE_1_4_4, QSPI_CMD_READ_4IO, QSPI_READ_4IO_DUMMY_CYCLE
91 #endif
92 
93 #ifdef QSPI_CMD_READ_DPI
94 #define READ_2_2_2 MODE_2_2_2, QSPI_CMD_READ_DPI, QSPI_READ_2IO_DUMMY_CYCLE
95 #endif
96 #ifdef QSPI_CMD_READ_QPI
97 #define READ_4_4_4 MODE_4_4_4, QSPI_CMD_READ_QPI, QSPI_READ_4IO_DUMMY_CYCLE
98 #endif
99 
100 #define ADDR_SIZE_8 QSPI_CFG_ADDR_SIZE_8
101 #define ADDR_SIZE_16 QSPI_CFG_ADDR_SIZE_16
102 #define ADDR_SIZE_24 QSPI_CFG_ADDR_SIZE_24
103 #define ADDR_SIZE_32 QSPI_CFG_ADDR_SIZE_32
104 
105 #define ALT_SIZE_8 QSPI_CFG_ALT_SIZE_8
106 #define ALT_SIZE_16 QSPI_CFG_ALT_SIZE_16
107 #define ALT_SIZE_24 QSPI_CFG_ALT_SIZE_24
108 #define ALT_SIZE_32 QSPI_CFG_ALT_SIZE_32
109 
110 #define STATUS_REG QSPI_CMD_RDSR
111 #define CONFIG_REG0 QSPI_CMD_RDCR0
112 #ifdef QSPI_CMD_RDCR1
113 #define CONFIG_REG1 QSPI_CMD_RDCR1
114 #endif
115 #ifdef QSPI_CMD_RDCR2
116 #define CONFIG_REG2 QSPI_CMD_RDCR2
117 #endif
118 #define SECURITY_REG QSPI_CMD_RDSCUR
119 
120 #ifndef QSPI_CONFIG_REG_1_SIZE
121 #define QSPI_CONFIG_REG_1_SIZE 0
122 #endif
123 
124 #ifndef QSPI_CONFIG_REG_2_SIZE
125 #define QSPI_CONFIG_REG_2_SIZE 0
126 #endif
127 
128 
129 #define SECTOR_ERASE QSPI_CMD_ERASE_SECTOR
130 #define BLOCK_ERASE QSPI_CMD_ERASE_BLOCK_64
131 
132 
133 #define SECTOR_ERASE_MAX_TIME QSPI_ERASE_SECTOR_MAX_TIME
134 #define BLOCK32_ERASE_MAX_TIME QSPI_ERASE_BLOCK_32_MAX_TIME
135 #define BLOCK64_ERASE_MAX_TIME QSPI_ERASE_BLOCK_64_MAX_TIME
136 #define PAGE_PROG_MAX_TIME QSPI_PAGE_PROG_MAX_TIME
137 #define WRSR_MAX_TIME QSPI_WRSR_MAX_TIME
138 #define WAIT_MAX_TIME QSPI_WAIT_MAX_TIME
139 
140 
141 
142 qspi_status_t read_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q);
143 qspi_status_t write_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q);
144 
145 QspiStatus flash_wait_for(uint32_t time_us, Qspi &qspi);
146 
147 void flash_init(Qspi &qspi);
148 
149 qspi_status_t write_enable(Qspi &qspi);
150 qspi_status_t write_disable(Qspi &qspi);
151 
152 void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str = NULL);
153 
154 qspi_status_t mode_enable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
155 qspi_status_t mode_disable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
156 
157 qspi_status_t fast_mode_enable(Qspi &qspi);
158 qspi_status_t fast_mode_disable(Qspi &qspi);
159 
160 qspi_status_t erase(uint32_t erase_cmd, uint32_t flash_addr, Qspi &qspi);
161 
162 bool is_extended_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
163 bool is_dual_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
164 bool is_quad_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
165 
166 #define WAIT_FOR(timeout, q) TEST_ASSERT_EQUAL_MESSAGE(sOK, flash_wait_for(timeout, q), "flash_wait_for failed!!!")
167 
168 
169 #endif // MBED_QSPI_TEST_UTILS_H
qspi_command
QSPI command.
Definition: qspi_api.h:92
qspi_t
struct qspi_s qspi_t
QSPI HAL object.
Definition: qspi_api.h:40
qspi_address_size_t
enum qspi_address_size qspi_address_size_t
Address size in bits.
qspi_alt_size_t
uint8_t qspi_alt_size_t
Alternative size in bits.
Definition: qspi_api.h:79
qspi_bus_width_t
enum qspi_bus_width qspi_bus_width_t
QSPI Bus width.
flash_init
int32_t flash_init(flash_t *obj)
Initialize the flash peripheral and the flash_t object.
qspi_status_t
enum qspi_status qspi_status_t
QSPI return status.
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